# This file is used by the simulation model as well as the ispLEVER bitstream
# generation process to automatically initialize the PCSD quad to the mode
# selected in the IPexpress. This file is expected to be modified by the
# end user to adjust the PCSD quad to the final design requirements.

DEVICE_NAME "LFE3-35EA"
CH0_PROTOCOL            "10BSER"
CH1_PROTOCOL            "10BSER"
CH2_PROTOCOL            "10BSER"
CH3_PROTOCOL            "10BSER"
CH0_MODE                "RXTX"
CH1_MODE                "RXTX"
CH2_MODE                "RXTX"
CH3_MODE                "RXTX"
CH0_CDR_SRC       "REFCLK_EXT"
CH1_CDR_SRC       "REFCLK_EXT"
CH2_CDR_SRC       "REFCLK_EXT"
CH3_CDR_SRC       "REFCLK_EXT"
PLL_SRC                 "REFCLK_EXT"
TX_DATARATE_RANGE       "HIGH"
CH0_RX_DATARATE_RANGE   "HIGH"
CH1_RX_DATARATE_RANGE   "HIGH"
CH2_RX_DATARATE_RANGE   "HIGH"
CH3_RX_DATARATE_RANGE   "HIGH"
REFCK_MULT              "20X"
#REFCLK_RATE            156.25
CH0_RX_DATA_RATE        "FULL"
CH1_RX_DATA_RATE        "FULL"
CH2_RX_DATA_RATE        "FULL"
CH3_RX_DATA_RATE        "FULL"
CH0_TX_DATA_RATE        "FULL"
CH1_TX_DATA_RATE        "FULL"
CH2_TX_DATA_RATE        "FULL"
CH3_TX_DATA_RATE        "FULL"
CH0_TX_DATA_WIDTH       "20"
CH1_TX_DATA_WIDTH       "20"
CH2_TX_DATA_WIDTH       "20"
CH3_TX_DATA_WIDTH       "20"
CH0_RX_DATA_WIDTH        "20"
CH1_RX_DATA_WIDTH        "20"
CH2_RX_DATA_WIDTH        "20"
CH3_RX_DATA_WIDTH        "20"
CH0_TX_FIFO       "ENABLED"
CH1_TX_FIFO       "ENABLED"
CH2_TX_FIFO       "ENABLED"
CH3_TX_FIFO       "ENABLED"
CH0_RX_FIFO        "ENABLED"
CH1_RX_FIFO        "ENABLED"
CH2_RX_FIFO        "ENABLED"
CH3_RX_FIFO        "ENABLED"
CH0_TDRV      "0"
CH1_TDRV      "0"
CH2_TDRV      "0"
CH3_TDRV      "0"
#CH0_TX_FICLK_RATE      156.25
#CH1_TX_FICLK_RATE      156.25
#CH2_TX_FICLK_RATE      156.25
#CH3_TX_FICLK_RATE      156.25
#CH0_RXREFCLK_RATE        "156.25"
#CH1_RXREFCLK_RATE        "156.25"
#CH2_RXREFCLK_RATE        "156.25"
#CH3_RXREFCLK_RATE        "156.25"
#CH0_RX_FICLK_RATE      156.25
#CH1_RX_FICLK_RATE      156.25
#CH2_RX_FICLK_RATE      156.25
#CH3_RX_FICLK_RATE      156.25
CH0_TX_PRE              "DISABLED"
CH1_TX_PRE              "DISABLED"
CH2_TX_PRE              "DISABLED"
CH3_TX_PRE              "DISABLED"
CH0_RTERM_TX            "50"
CH1_RTERM_TX            "50"
CH2_RTERM_TX            "50"
CH3_RTERM_TX            "50"
CH0_RX_EQ               "DISABLED"
CH1_RX_EQ               "DISABLED"
CH2_RX_EQ               "DISABLED"
CH3_RX_EQ               "DISABLED"
CH0_RTERM_RX            "50"
CH1_RTERM_RX            "50"
CH2_RTERM_RX            "50"
CH3_RTERM_RX            "50"
CH0_RX_DCC              "AC"
CH1_RX_DCC              "AC"
CH2_RX_DCC              "AC"
CH3_RX_DCC              "AC"
CH0_LOS_THRESHOLD_LO       "2"
CH1_LOS_THRESHOLD_LO       "2"
CH2_LOS_THRESHOLD_LO       "2"
CH3_LOS_THRESHOLD_LO       "2"
PLL_TERM                "50"
PLL_DCC                 "AC"
PLL_LOL_SET             "0"
CH0_TX_SB               "DISABLED"
CH1_TX_SB               "DISABLED"
CH2_TX_SB               "DISABLED"
CH3_TX_SB               "DISABLED"
CH0_RX_SB               "DISABLED"
CH1_RX_SB               "DISABLED"
CH2_RX_SB               "DISABLED"
CH3_RX_SB               "DISABLED"
CH0_TX_8B10B            "DISABLED"
CH1_TX_8B10B            "DISABLED"
CH2_TX_8B10B            "DISABLED"
CH3_TX_8B10B            "DISABLED"
CH0_RX_8B10B            "DISABLED"
CH1_RX_8B10B            "DISABLED"
CH2_RX_8B10B            "DISABLED"
CH3_RX_8B10B            "DISABLED"
CH0_COMMA_A             "1100000101"
CH1_COMMA_A             "1100000101"
CH2_COMMA_A             "1100000101"
CH3_COMMA_A             "1100000101"
CH0_COMMA_B             "0011111010"
CH1_COMMA_B             "0011111010"
CH2_COMMA_B             "0011111010"
CH3_COMMA_B             "0011111010"
CH0_COMMA_M             "1111111100"
CH1_COMMA_M             "1111111100"
CH2_COMMA_M             "1111111100"
CH3_COMMA_M             "1111111100"
CH0_RXWA                "DISABLED"
CH1_RXWA                "DISABLED"
CH2_RXWA                "DISABLED"
CH3_RXWA                "DISABLED"
CH0_ILSM                "DISABLED"
CH1_ILSM                "DISABLED"
CH2_ILSM                "DISABLED"
CH3_ILSM                "DISABLED"
CH0_CTC                 "DISABLED"
CH1_CTC                 "DISABLED"
CH2_CTC                 "DISABLED"
CH3_CTC                 "DISABLED"
CH0_CC_MATCH4           "0100011100"
CH1_CC_MATCH4           "0100011100"
CH2_CC_MATCH4           "0100011100"
CH3_CC_MATCH4           "0100011100"
CH0_CC_MATCH_MODE       "1"
CH1_CC_MATCH_MODE       "1"
CH2_CC_MATCH_MODE       "1"
CH3_CC_MATCH_MODE       "1"
CH0_CC_MIN_IPG          "3"
CH1_CC_MIN_IPG          "3"
CH2_CC_MIN_IPG          "3"
CH3_CC_MIN_IPG          "3"
CCHMARK                 "9"
CCLMARK                 "7"
CH0_SSLB                "DISABLED"
CH1_SSLB                "DISABLED"
CH2_SSLB                "DISABLED"
CH3_SSLB                "DISABLED"
CH0_SPLBPORTS           "DISABLED"
CH1_SPLBPORTS           "DISABLED"
CH2_SPLBPORTS           "DISABLED"
CH3_SPLBPORTS           "DISABLED"
CH0_PCSLBPORTS          "DISABLED"
CH1_PCSLBPORTS          "DISABLED"
CH2_PCSLBPORTS          "DISABLED"
CH3_PCSLBPORTS          "DISABLED"
INT_ALL                 "ENABLED"
QD_REFCK2CORE           "ENABLED"