DDR3 SDRAM Controller

 

Implementing the IP Module Using Lattice ispLEVER and Diamond SW

 

Notes about Customizing the IP Core for Functional Simulation Evaluation

 

A testbench and a set of Micron memory models are bundled in this IP Package to help users evaluate the IP in functional simulation. In the IPExpress GUI, when user selects the pre-defined Micron memory model (i.e Micron DDR3 1Gb -25E), the DDR3 timing parameters are automatically adjusted by the IPExpress GUI based on the pre-defined Micron memory model requirement.

If user wants to select different models other than the Micron memory with different frequency, the memory selection in IPexpress GUI should be set to Custom. In addition to that, all the timing parameters should be updated by the user manually in the Timing tab by checking the Manually Adjust option.

The evaluation functional simulation that comes with this IP core running with a default frequency of 400MHz(DDR3 bus)/200MHz(Local bus) for ECP3 device.

Note: For clear understanding of the steps listed below, please refer the section "Generated Files" of the User's guide document.A table in this section provides the directory path and description of each generated file.

Instantiating the Core

The generated DDR3 SDRAM Memory Controller IP core contains Verilog and VHDL files. The Verilog HDL includes black-box (_bb.v) and an instance template (_inst.v) that can be used to instantiate the core in a user top-level design.

A RTL top-level wrapper source file that can be used as an reference example to instantiate the IP core with the CLOCKING block is provided in <project_dir>\ddr_p_eval\<username>\src\rtl\top\<family>. Users may also use this top-level reference as the starting template for the top-level for their complete design.

Hardware Evaluation

Lattice's IP hardware evaluation capability makes it possible to create IP cores that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase on an IP license. The hardware evaluation capability is enabled by default. It can be disabled by right clicking on "Build Database" in the "Process for current sources" window of the Project Navigator. The setting is called "Hardware Evaluation" and the options are "Enable" or "Disable".
 

When the Hardware Evaluation feature is enabled in the design, it will generate a programming file that may be downloaded into the device. After initialization, the IP core will be operational for approximately four hours. After four hours, the device will stop working and it will be necessary to reprogram the device to re-enable operation. This hardware evaluation capability is only enabled if the core has not been licensed. During implementation, a license check is performed. If the hardware evaluation feature is disabled, a pop-up window will be displayed indicating a license failure. Click"OK" in the window and the bitstream will not be generated. If a license is detected, no pop-up window is displayed and core generation is completed with no restrictions.


Implementing the Core in a Top-Level Design

As described, the top-level wrapper file ddr3_sdram_mem_top_wrapper.v provided in <project_dir>\ddr_p_eval\<username>\impl supports the ability to implement the DDR3 SDRAM Controller for evaluation purpose.

Push-button top-level implementation of this top-level is supported via the Diamond project file <username>_eval.ldf (.syn for ispLEVER project file) located in \<project_dir>\ ddr_p_eval\<username>\impl\<synplify|precision>.

This design is intended only to provide an accurate indication of the device utilization associated with the core itself and should not be used as an actual implementation design without attaching user's backend.

Note for Preferences: A preference file is generated for each synthesis flow at the time of core generation. It contains important constraining information for the generated core implementation. Most cases, the net and path names for the preferences match with the synthesized netlist. In some cases, however, the synthesis tool may change one or more names of those nets and/or paths. This usually happens when a design hierarchy is changed due to the addition of user application or a different version of a synthesis tool is used. When this happens, user will have preference semantic errors/warnings affecting the implementation results. These errors/warnings must be eliminated in order to get the proper core operation and performance. Refer to the user guide's Preference Localization section for detail.

To use the project file:

  • Select File-> Open-> Project in Diamond SW. (Open Project under the File tab in ispLEVER.)
  • Browse to <project_dir>\ddr_p_eval\<username>\impl\<synplify|precision> in the Open Project dialog box.
  • Select and open <username>_eval.ldf (.syn for ispLEVER SW). At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project.
  • One lpf file is available in the \impl\<synplify|precision>directory named <project_name>_eval.lpf.
  • Implement the complete design via the standard Diamond (or ispLEVER) GUI flow. Please remain all options at their default values.


Running Functional Simulation

The functional simulation includes a configuration-specific behavioral model of the DDR3 IP Core, which is instantiated in an FPGA top level along with some test logic (CLOCKING block, and registers with Read/Write Interface). This FPGA top is instantiated in an eval testbench that configures FPGA test logic registers and DDR3 IP core registers. The testbench also includes Verilog test file testcase.v, this file can be found in <project_dir>\ddr_p_eval\testbench\tests\<family>.

For Verilog simulation, Aldec Active-HDL or ModelSim SE may be used.
For VHDL simulation, Aldec Active-HDL or Modelsim SE may be used to support mix-HDL simulation.

The generated IP core package includes the configuration-specific behavior model (<username>_beh.v) for functional simulation. ModelSim simulation is supported via testbench files provided in <project_dir>\ddr_p_eval\testbench. Models required for simulation are provided in the corresponding \models folder.
Users may run the eval simulation by doing the following with ModelSim:

  • Open ModelSim.
  • Under the File tab, select Change Directory
  • Set the directory to <project_dir>\ddr_p_eval\<username>\sim\modelsim.
  • Select OK.
  • Under the Tools tab, select TCL, then select Execute Macro
  • Select file <username>_eval_se.do

Note: For VHDL simulation, run the batch file, orc_cmpl.bat, if you have not done it before. It will compile the target device's simulation library for the provided ModelSim script. The batch file is found at [ispLEVER(Diamond)_install]\cae_library\simulation\vhdl\<family>\mti.

Users may run the eval simulation by doing the following with Active-HDL(Windows only):

  • Open Active-HDL
  • Under the tools tab, select Execute Macro
  • Select file \<project_dir>\ddr_p_eval\<username>\sim\aldec\<username>_eval.do
  • Select OK.

 

Static Timing Report file

Some of the preferences are over constrained to achieve maximum timing performance. User may observe timing violations when viewing the timing report. To check if the timing violations are within allowed limits, use the Post Route Trace preference files to generate the correct timing report.

1) Replace the preference file (.prf) in the project directory with the following Post Route Trace file. Rename the Post Route Trace preference file to match the project name.

  • post_route_trace.prf

2) From the GUI of the Project Navigator, right click on Place & Route Trace Report. Select Force One Level(For Diamond SW,right click Place & Route Trace,select Rerun).

  • The new timing report is generated.

Bitstream file generation

Any timing violation due to over constraints will trigger error in bitstream process.

Before generating bitstream file, select Tools-> Timing Checkpoint Options.. in the Project Navigator and check the "continue" option, instead of "stop" option. (ispLEVER only)

Limitations of this version:

  • For Linux platform, Aldec-HDL and Precision flow are not supported

Please ignore these warnings. They will not impact the functionality

  • [Ignorable PAR warnings]

    WARNING - map: Using local reset signal 'rst_n_c' to infer global GSR net.

    WARNING - par: Signal "clk_in_c" is selected to use Primary clock resources; however its driver comp "clk_in" is located at "U6", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it may suffer from excessive delay or skew.

    WARNING - par: The driver of primary clock net clk_in_c is not placed on one of the dedicated sites which for primary clocks. This primary clock will be routed to a H-spine through general routing resource or be routed as secondary clock and may suffer from excessive delay or skew.

  • [Ignorable Simulation Warnings]

       # WARNING: 200 us is required before RST_N goes inactive.

       # WARNING: 500 us is required after RST_N goes inactive before CKE goes active.

       # WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.

       # WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.

       # Other ACTIVE-HDL warnings during compilation may also be safely ignored.

Known Issues:

  • ispLEVER 8.1SP1 users: DDR3 Controller v1.2 is supported by ispLEVER 8.1SP1 but requires a patch.  This patch can be requested from Lattice techsupport.
    The patch name is  SP8.1.01.35.45.10_ECP3_DDR3_eclk_Patch.exe.

Reference Information

The following documents provide more information on implementing this core:

 

General Information


Copyright Notice

Copyright 2000-2010© Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This confidential and proprietary software may be used only as authorized by a licensing agreement from Lattice Semiconductor Corporation. The entire notice above must be reproduced on all authorized copies and copies may only be made to the extent permitted by a licensing agreement from Lattice Semiconductor Corporation.


Contacting Lattice

 

Mail:

Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR  97124
U.S.A.

Telephone:

1-800-LATTICE (USA and Canada)

 

1-503-268-8001 (other locations)

Website:

http://www.latticesemi.com(US)
http://www.latticesemi.com.cn(China)
http://www.latticesemi.co.kr(Korea)
http://www.latticesemi.co.jp(Japan)

E-mail:

techsupport@latticesemi.com
techsupport_china@latticesemi.com (China)

 

IP Module Information


About this Module

IP Name:

DDR3 SDRAM Controller

IP Version:

ver 1.2

IP Release Date:

DEC 2010

Target Technology:

Lattice ECP3


Software Requirements

Synthesis Tools Supported:

SynplifyPro D-2010.03L-SP1
Precision full-up 2010a.218

Simulation Tools Supported:

Active-HDL Lattice 8.2 sp1, ModelSim SE v6.5 or later

Lattice Tool Supported:

Diamond 1.1 or later,
ispLEVER 8.1sp1 or later