title | : | Integrated Circuit Quality and Reliability Electrical Engineering and Electronics ; 91
author | : | Hnatek, Eugene R.
publisher | : | CRC Press
isbn10 | asin | : | 0824792831
print isbn13 | : | 9780824792831
ebook isbn13 | : | 9780585138602
language | : | English
subject |  | Integrated circuits--Reliability.
publication date | : | 1995
lcc | : | TK7874.H535 1995eb
ddc | : | 621.3815
subject | : | Integrated circuits--Reliability.

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Integrated Circuit Quality and Reliability

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ELECTRICAL ENGINEERING AND ELECTRONICS
A Series of Reference Books and Textbooks

EXECUTIVE EDITORS

Marlin O. Thurston
Department of Electrical Engineering
The Ohio State University
Columbus, Ohio

William Middendorf
Department of Electrical
and Computer Engineering
University of Cincinnati, Ohio

EDITORIAL BOARD

Maurice Bellanger
Télécommunications, Radioélectriques,
et Téléphoniques (TRT)
Le Plessis-Robinson, France

J. Lewis Blackburn
Bothell, Washington

Sing-Tze Bow
Department of Electrical Engineering
Northern Illinois University
Northern Illinois University
De Kalb, Illinois

Norman B. Fuqua
Reliability Analysis Center
Griffiss Air Force Base, New York

Charles A. Harper
Westinghouse Electrical Engineering
and Technology Seminars, Inc.
Timonium, Maryland

Naim A. Kheir
Department of Electrical and
Systems Engineering
Oakland University
Rochester, Michigan

Lionel M. Levinson
General Electric Company
Schenectady, New York

V. Rajagopalan
Department of Engineering
Université du Québec
à Trois-Rivières
Trois-Rivières, Quebec, Canada

Earl E. Swartzlander
TRW Defense Systems Group
Redondo Beach, California

Spyros G. Tzafestas
Department of Electrical
and Computer Engineering
National Technical University
of Athens
Athens, Greece

Sakae Yamamura
Central Research Institute of
the Electric Power Industry
Tokyo, Japan

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1. Rational Fault Analysis, edited by Richard Saeks and S. R. Liberty
2. Nonparametric Methods in Communications, edited by P. Papantoni-Kazakos and Dimitri Kazakos
3. Interactive Pattern Recognition, Yi-tzuu Chien
4. Solid-State Electronics, Lawrence E. Murr
5. Electronic, Magnetic, and Thermal Properties of Solid Materials, Klaus Schröder
6. Magnetic-Bubble Memory Technology, Hsu Chang
7. Transformer and Inductor Design Handbook, Colonel Wm. T. McLyman
8. Electromagnetics: Classical and Modern Theory and Applications, Samuel Seely and Alexander D. Poularikas
9. One-Dimensional Digital Signal Processing, Chi-Tsong Chen
10. Interconnected Dynamical Systems, Raymond A. DeCarlo and Richard Saeks
11. Modern Digital Control Systems, Raymond G. Jacquot
12. Hybrid Circuit Design and Manufacture, Roydn D. Jones
13. Magnetic Core Selection for Transformers and Inductors: A User's Guide to Practice and Specification, Colonel Wm. T. McLyman
14. Static and Rotating Electromagnetic Devices, Richard H. Engelmann
15. Energy-Efficient Electric Motors: Selection and Application, John C. Andreas
16. Electromagnetic Compossibility, Heinz M. Schlicke
17. Electronics: Models, Analysis, and Systems, James G. Gottling
18. Digital Filter Design Handbook, Fred J. Taylor
19. Multivariable Control: An Introduction, P. K. Sinha
20. Flexible Circuits: Design and Applications, Steve Gurley, with contributions by Carl A. Edstrom, Jr., Ray D. Greenway, and William P. Kelly
21. Circuit Interruption: Theory and Techniques, Thomas E. Browne, Jr.
22. Switch Mode Power Conversion: Basic Theory and Design, K. Kit Sum
23. Pattern Recognition: Applications to Large Data-Set Problems, Sing-Tze Bow
24. Custom-Specific Integrated Circuits: Design and Fabrication, Stanley L. Hurst
25. Digital Circuits: Logic and Design, Ronald C. Emery
26. Large-Scale Control Systems: Theories and Techniques, Magdi S. Mahmoud, Mohamed F. Hassan, and Mohamed G. Darwish
27. Microprocessor Software Project Management, Eli T. Fathi and Cedric V. W. Armstrong (Sponsored by Ontario Centre for Microelectronics)
28. Low Frequency Electromagnetic Design, Michael P. Perry
29. Multidimensional Systems: Techniques and Applications, edited by Spyros G. Tzafestas
30. AC Motors for High-Performance Applications: Analysis and Control, Sakae Yamamura

Page ad

31. Ceramic Motors for Electronics: Processing, Properties, and Applications, edited by Relva C. Buchanan
32. Microcomputer Bus Structures and Bus Interface Design, Arthur L. Dexter
33. End User's Guide to Innovative Flexible Circuit Packaging, Jay J. Miniet
34. Reliability Engineering for Electronic Design, Norman B. Fuqua
35. Design Fundamentals for Low-Voltage Distribution and Control, Frank W. Kussy and Jack L. Warren
36. Encapsulation of Electronic Devices and Components, Edward R. Salmon
37. Protective Relaying: Principles and Applications, J. Lewis Blackburn
38. Testing Active and Passive Electronic Components, Richard F. Powell
39. Adaptive Control Systems: Techniques and Applications, V. V. Chalam
40. Computer-Aided Analysis of Power Electronic Systems, Venkatachari Rajagopalan
41. Integrated Circuit Quality and Reliability, Eugene R. Hnatek
42. Systolic Signal Processing Systems, edited by Earl E. Swartzlander, Jr.
43. Adaptive Digital Filters and Signal Analysis, Maurice G. Bellanger
44. Electronic Ceramics: Properties, Configuration, and Applications, edited by Lionel M. Levinson
45. Computer Systems Engineering Management, Robert S. Alford
46. Systems Modeling and Computer Simulation, edited by Naim A. Kheir
47. Rigid-Flex Printed Wiring Design for Production Readiness, Walter S. Rigling
48. Analog Methods for Computer-Aided Circuit Analysis and Diagnosis, edited by Takao Ozawa
49. Transformer and Inductor Design Handbook: Second Edition, Revised and Expanded, Colonel Wm. T. McLyman
50. Power System Grounding and Transients: An Introduction, A. P. Sakis Meliopoulos
51. Signal Processing Handbook, edited by C. H. Chen
52. Electronic Product Design for Automated Manufacturing, H. Richard Stillwell
53. Dynamic Models and Discrete Event Simulation, William Delaney and Erminia Vaccari
54. FET Technology and Application: An Introduction, Edwin S. Oxner
55. Digital Speech Processing, Synthesis, and Recognition, Sadaoki Furui
56. VLSI RISC Architecture and Organization, Stephen B. Furber
57. Surface Mount and Related Technologies, Gerald Ginsberg
58. Uninterruptible Power Supplies: Power Conditioners for Critical Equipment, David C. Griffith
59. Polyphase Induction Motors: Analysis, Design, and Application, Paul L. Cochran

Page ae

60. Battery Technology Handbook, edited by H. A. Kiehne
61. Network Modeling, Simulation, and Analysis, edited by Ricardo F. Garzia and Mario R. Garzia
62. Linear Circuits, Systems, and Signal Processing: Advanced Theory and Applications, edited by Nobuo Nagai
63. High-Voltage Engineering: Theory and Practice, edited by M. Khalifa
64. Large-Scale Systems Control and Decision Making, edited by Hiroyuki Tamura and Tsuneo Yoshikawa
65. Industrial Power Distribution and Illuminating Systems, Kao Chen
66. Distributed Computer Control for Industrial Automation, Dobrivoje Popovic and Vijay P. Bhatkar
67. Computer-Aided Analysis of Active Circuits, Adrian Ioinovici
68. Designing with Analog Switches, Steve Moore
69. Contamination Effects on Electronic Products, Carl J. Tautscher
70. Computer-Operated Systems Control, Magdi S. Mahmoud
71. Integrated Microwave Circuits, edited by Yoshihiro Konishi
72. Ceramic Materials for Electronics: Processing, Properties, and Applications, Second Edition, Revised and Expanded, edited by Relva C. Buchanan
73. Electromagnetic Compatibility: Principles and Applications, David A. Weston
74. Intelligent Robotic Systems, edited by Spyros G. Tzafestas
75. Switching Phenomena in High-Voltage Circuit Breakers, edited by Kunio Nakanishi
76. Advances in Speech Signal Processing, edited by Sadaoki Furui and M. Mohan Sondhi
77. Pattern Recognition and Image Preprocessing, Sing-Tze Bow
78. Energy-Efficient Electric Motors: Selection and Application, Second Edition, John C. Andreas
79. Stochastic Large-Scale Engineering Systems, edited by Spyros G. Tzafestas and Keigo Watanabe
80. Two-Dimensional Digital Filters, Wu-Sheng Lu and Andreas Antoniou
81. Computer-Aided Analysis and Design of Switch-Mode Power Supplies, Yim-Shu Lee
82. Placement and Routing of Electronic Modules, edited by Michael Pecht
83. Applied Control: Current Trends and Modern Methodologies, edited by Spyros G. Tzafestas
84. Algorithms for Computer-Aided Design of Multivariable Control Systems, Stanoje Bingulac and Hugh F. VanLandingham
85. Symmetrical Components for Power Systems Engineering, J. Lewis Blackburn
86. Advanced Digital Signal Processing: Theory and Applications, Glenn Zelniker and Fred J. Taylor
87. Neural Networks and Simulation Methods, Jian-Kang Wu
88. Power Distribution Engineering: Fundamentals and Applications, James J. Burke

Page af

89. Modern Digital Control Systems: Second Edition, Raymond G. Jacquot
90. Adaptive IIR Filtering in Signal Processing and Control, Phillip A. Regalia
91. Integrated Circuit Quality and Reliability: Second Edition, Revised and Expanded, Eugene R. Hnatek
92. Handbook of Electric Motors, edited by Richard H. Engelmann and William H. Middendorf

Additional Volumes in Preparation

Power-Switching Converters, Simon Ang

Page i

Integrated Circuit Quality and Reliability

Second Edition, Revised and Expanded

Eugene R. Hnatek

Tandem Computers Inc.
Cupertino, California

MARCEL DEKKER, INC.
New York Basel Hong Kong

Page ii

Library of Congress Cataloging-in-Publication Data

Hnatek, Eugene R.
Integrated circuit quality and reliability / Eugene R. Hnatek. 2nd ed., rev. and expanded.
p. cm. (Electrical engineering and electronics; 91)
Includes bibliographical references and index.
ISBN 0-8247-9283-1 (acid-free paper)
1. Integrated circuitsReliability. I. Title. II. Series.
TK7874.H535 1995
621.3815dc2094-33926
CIP

The publisher offers discounts on this book when ordered in bulk quantities. For more information, write to Special Sales/Professional Marketing at the address below.

This book is printed on acid-free paper.

Copyright © 1995 by MARCEL DEKKER, INC. All Rights Reserved.

Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, microfilming, and recording, or by any information storage and retrieval system, without permission in writing from the publisher.

MARCEL DEKKER, INC.
270 Madison Avenue, New York, New York 10016

Current printing (last digit):
10 9 8 7 6 5 4 3 2 1

PRINTED IN THE UNITED STATES OF AMERICA

Page iii

To my wife, Susan, for her patience, support, encouragement, and editorial help.
Additionally, I would like to publicly thank and praise the Lord Jesus Christ for His unconditional love, His faithfulness, His abundant grace and mercy, and for saving an unworthy sinner such as me through His death, burial, and resurrection.

Page v

PREFACE

The increased use of integrated circuits (ICs) in all types of products has been accompanied by a growing concern over IC failures. With the trend toward higher PC board complexity and the availability and use of denser ICs fabricated with new and complex process technologies, users have become increasingly concerned about inherent device quality. IC failures significantly impact a user's ability to do business in his chosen marketplace. What are the effects of device failures in the user's equipment? Equipment downtime, high warranty/repair costs, lawsuits, and loss of sales and goodwill. In the case of astronautics and aeronautics, repair might not be possible (e.g., a deep space probe that cannot be returned for repair, or an airplane that crashes), putting an extremely high price tag on the cost of a device failure, even to the point of loss of life. Consider an IC failure in computers that automate a steel manufacturing process, process banking transactions, or control the functioning of an automobile. The losses can be staggering, even immeasurable.

The semiconductor industry, by virtue of very-large-scale integrated systems on silicon, is performing on a single chip the same function as the systems industry of yesterday. Consequently, the engineering, manufacturing

Page vi

management, statistical quality assurance, and team concepts and methods learned from the systems industry are being applied to the IC industry.

The words reliability and quality are often used interchangeably as though they were identical facets of a product's merit; however, they are different. Getting an exact and agreed-upon definition of quality is difficult. Quality pertains to the population of faulty devices among the good ones as they arrive at the user's plant (i.e., bad devices that escape the supplier's detection: Type II errors). Some define quality as fitness for use. Others define it as conformance to specifications. The quality of an IC can be defined as its performance in its intended application. Quality is an inherent device characteristic that must be both designed into the IC during circuit design, simulation, and process development and manufactured in during wafer fabrication and assembly. Quality is this and more. It is also determined by customer perceptions and expectations and is what the customer gets out of a product and is willing to pay for.

Reliability is the probability that an IC will perform in accordance with expectations for a predetermined period of time in a given environment. Thus, reliability is quality on a time scale, so to speak, and testing (screening) compresses the time scale. To meet any reliability objective requires a comprehensive knowledge of the interactions of the basic design, its inherent weaknesses and sensitivities (failure mechanisms), and the application environment in which that design will operate.

Quality assurance historically has been an additive operation tacked on after the completion of manufacturing to confirm that all steps were performed properly via some means of inspection and/or testing. Quality assurance was focused on the negativecatch the defects. It was predicated on the premise that you can't build it right. But this has changed due to the pressures of global competition.

The focus has changed from the detection of defects to their prevention by means of a proactive and aggressive approach to quality. In the past, methods of increasing quality relied on testing. This was wrong on two fronts. First, you can't inspect or test quality into a product, and second, inspection personnel are not solely responsible for quality; each individual in the organization is responsible for quality. Thus, the way to produce a quality product is by assembling a cross-functional team up front during product definitionrepresenting design, package, process, software, and reliability engineering; manufacturing operations (wafer fabrication, assembly and test); and purchasing and marketingand by actively applying such techniques as design of experiments, quality function deployment, design for manufacturability, design-for-test, and design for reliability.

Testing and inspection are important in producing quality products. Testing is the means by which data are gathered, analyzed, and fed back to design and manufacturing for continuous improvement. In the past, electrical testing was

Page vii

relied on heavily as a gate to check the quality level of outgoing parts and prevent the shipment of defective parts. During the past 14 years IC quality has dramatically improved due to a lot of hard work on the part of IC manufacturers. This began with a paradigm shift from a detecting-defects mindset to a preventing-escapes (zero-escapes) mindset as they embraced total quality management and applied problem-solving and statistical techniques to the design and manufacture of ICs. Final parametric electrical testing by the supplier is important to verify conformance to specifications, to grade products by classification, and to feed back the results of critical electrical parameter measurements and end-of-line defect information to manufacturing so they can correlate these measurements to process measurements, allowing continuous improvement to take place. But testing has aggressively moved forward into the wafer fabrication area in the form of process monitors or test structures immediately following each process step. This results in a short (if not instantaneous) feedback path, allowing real-time corrective action and improvement, reducing waste, rework, and cost. The application of statistical techniques in the wafer fabrication and assembly areas has been responsible for reducing defects from more than 10,000 parts per million a few years ago to fewer than 1000 parts per million today (averaged across all IC manufacturers, fabrication and assembly facilities, technologies, and product lines) and even below 100 ppm on a very specific supplier, technology, and product basis.

In order to understand IC quality, one has to know where defects can occur during design, wafer fabrication and assembly, and test. This requires an understanding of the IC technology as well as the potential failure mechanisms that can occur.

Since the first edition of this book was published, much has changed, and the pace of change and technological innovation will continue unabated. The section in Chapter 1 entitled Trends summarizes the significant changes. Yet much has remained the same. ICs have the same potential failure mechanisms as they did in the '60s, '70s, and '80s, but due to the circuit packing density and submicrometer geometries, they are much more susceptible to them than in the past. We are also faced with the issue of wearout mechanisms when dealing with vertical layer thickness measured in Angstroms, such as oxide wearout and electromigration wearout.

This edition has been updated and reorganized to reflect the changes that have taken place and add to the original baseline and tool set established in the first edition, yet it retains those elements that are fundamental to producing quality ICs irrespective of technological change.

The keynote address at the 1994 IEEE International Reliability Physics Symposium forecast that market factors (including huge capital costs) will make 100% yields a necessity for any semiconductor manufacturer to survive. In the future, he stated, defects are going to go away. This is a bold prognostication

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indeed, considering the hundreds, if not thousands, of places in the IC design, wafer fabrication, assembly, test, and handling processes in which errors or defects can occur. One thing is certain: there will never be a dull moment. The future will be interesting, exciting, and extremely challenging. I look forward to it and hope that you do as well.

EUGENE R. HNATEK

Page ix

CONTENTS

Preface

v

1. Overview of Integrated Circuit Quality and Trends

1

Historical Perspective on IC Quality

1

Trends

5

References

22

Part I: Introduction to Integrated Circuit Manufacturing Processes

23

2. Front-End IC Fabrication Operations

27

Basic IC Materials

27

IC Design

30

Mask Making

35

IC Fabrication Sequence

39

Depositing Layers on the Wafer Surface

53

Chemical Vapor Deposition

68

Evaporation

68

Sputtering

74

Page x

Die Passivation

76

Typical IC Processes

78

References

98

3. Back-End Fabrication Operations

99

Wafer Probe Test

99

New Wafer Probe Methods

101

Scribe and Break

106

Assembling and Packaging the IC

107

Electrical Testing

151

Yield Considerations

172

References

175

Selected Readings

175

4. In-Line Process Monitors and Test Structures

177

Reference

203

Part II: Impact of New Technologies

205

5. Circuit Design Trends

207

What the DRAM Future Promises

207

Vertical Structures

213

Three-Dimensional ICs

222

Logic Simulation

225

References

226

6. Changing Fabrication Techniques

227

Lithography

227

Doping TrendsChanges in Diffusion Furnace Usage

243

Ion Implantation

246

Material Technology Trends

248

VLSI Metallization

258

Summary

292

References

292

Selected Readings

292

7. Packaging Technology Trends

293

New Package Solutions

295

Multichip Module Packages

298

Die Interconnection Techniques

302

Reference

307

Selected Readings

307

Page xi

8. Electrical Testing of VLSICs and ASICs

309

Introduction

309

The Purpose of Testing

310

Historical SSI and MSI Test Program Development Methodology

312

The Nature of VLSI Circuits as It Impacts Testing

313

Testing VLSIC Devices

317

Test Philosophy

317

Systems on Silicon

318

The Designer (User)-Foundry (Supplier) Interface

319

Test Specifications

321

Integrating Design and Test

323

The Simulator-Tester Relationship

325

Test Generation and Fault Simulation

329

Other Methods of Applying Simulation to Test

337

Testability

338

Design-for-Test

341

Engineering Workstations

343

ATE Software Verification

346

Conclusion

348

References

348

Selected Readings

350

Part III: Contamination and Manufacturing Errors

351

References

359

9. Contamination

361

Wafer Ecology

369

Sources of Contamination

370

References

418

10. Human-Derived Contamination

419

Human Traffic

419

Human Dust

421

Protective Garments

422

Reference

427

11. IC Processing Contamination

429

Photomasking and Photoresist Defects

432

Etch

441

Dry Processing

441

High-Temperature Processes

442

Ion Implantation

454

Page xii

Equipment Contamination

456

Wafer Processing Automation

457

Electrostatic Charge

466

Equipment Considerations that Could Produce Errors at Wafer Probe

476

Contamination During Bonding and Packaging Operations

479

References

488

Selected Readings

488

12. Contamination Control

489

References

492

13. Computer-Based Sources of Error in Design and Test

493

Circuit Design Overview

493

Sources of Error

495

References

522

14. Materials Issues

525

Introduction

525

IC Material Properties

526

Degradation

532

Dislocations

538

Mechanical Defects

541

Stress Concentrators

541

Dielectric Layers

547

Metallization

549

Package and Interconnection Issues

555

References

564

Part IV: Causes (Sources) of IC Failures

565

15. Fabrication-Related Causes of IC Defects

587

Bulk and Surface Failures

587

Processing Faults

589

Dielectric Breakdown

593

Ionic Contamination

603

Hot Carrier Effects

612

Metallization

616

Summary of VLSI Circuit Defects and Failure Mechanisms

650

References

652

Selected Readings

652

Page xiii

16. Packaging-and Assembly-Related Causes of IC Failures

655

Overview

655

Surface Passivation and Corrosion

658

Electrochemical Migration

661

Die Bonding Issues

662

The Physical Package

676

Hermetic Package Reliability

677

Plastic Package Reliability

683

External Package Moisture-Induced Failure Mechanisms

695

Human Causes of Error

699

Summary

701

References

702

17. Reliability Improvement

703

Overview

703

The Bathtub Failure Curve

704

The Arrhenius Equation and Temperature Acceleration

716

Activation Energy

723

Problems Encountered in Applying the Arrhenius Equation

728

References

732

Part V: Introduction to Screening

733

18. Screening

735

Introduction

735

ESS Overview

739

Most Commonly Employed Screens

744

Conventional Screening Procedures

757

Screening Sequence

758

Selected Stress Screen Discussion

759

Monitoring the Screening Program

770

Appendix Periodic Table of the Elements

771

Index

775

Page 1

1
Overview of Integrated Circuit Quality and Trends

Historical Perspective on IC Quality

The pace of industrial change has quickened during the past 14 years and will accelerate still further as America moves toward the 21st century. In the future, those companies that are keenly proficient at planning, implementing, and adapting to change will have a remarkable strategic advantage over their competitors. The basis of this proficiency will be flexibility in workers and managers, a less rigid corporate hierarchy, optimal use of technology, an emphasis on people, and widespread cooperation and teamwork within and outside of the organizationin essence, agile manufacturing.

Global competition has dramatically impacted the quality of products manufactured as measured by both customer expectations and satisfaction. Nowhere has change been so rapid, dramatic, or profound as in the U.S. semiconductor industryspecifically the design and manufacture of integrated circuits. Let's step back and revisit what happened.

The American mass production paradigm tolerated, even expected, a certain amount of waste (faulty product) and used testing to remove that from the product shipped. Quality control by definition was dedicated to the premise that you can't

Page 2

get it right. Inspection reigned: both outgoing testing by the integrated circuit (IC) suppliers and 100% incoming inspection testing by the using community.

United States IC manufacturers had an essentially complacent attitude toward quality. In the 1960s and 1970s, IC suppliers often had a huge bone pile of reject devices at final electrical test. There was no concerted effort to find out the root cause of these rejects and institute a corrective feedback loop back to design and manufacturing. Further, it was found that a good percentage of these devices (30%70%) were actually good parts but were failed (rejected) by the IC supplier's testing process. These are called Type I errors [1,2]. Also, during this time frame the users found a high percentage of rejects, as well, during their 100% incoming inspection testing. These were escapes from the IC supplier's final test area and are referred to in the literature as Type II errors [1,2].

These practices were brought to a screeching halt in 1980 when HewlettPackard dropped a bombshell. They announced that Japanese 16 K DRAMs exhibited one to two orders of magnitude less defects than did those same DRAMs produced by U.S.-based IC manufacturers. The Japanese aggressively and insightfully implemented the quality teachings (a.k.a. total quality management) of such visionaries as Drs. W. Edwards Deming and Joseph Juran and consequently forever changed the way that integrated circuits are designed, manufactured, and tested. Thus, the Japanese sounded a wake-up call to all of U.S. industry, not just the semiconductor industry, that shoddy quality products were not acceptablethey raised the bar for product quality and changed the focus from a domestic one to a global one.

The Hewlett-Packard announcement and subsequent loss of worldwide market share served to mobilize the U.S. IC industry and focus on quality to prevent its extinction (i.e., survival)it stirred the U.S. IC industry from its complacency. The result was a paradigm shift from an inspection mindset to a genuine concern for the quality of ICs produced via a prevention or zero escape (i.e., a build it right the first time) mindset. It was simply a matter of design and produce quality ICs or go out of business.

Some of the factors fundamental and inherent to this paradigm shift include

Quality is the sole responsibility of the IC supplier.

Quality must be built and manufactured into the product, beginning at design.

Design automation tools using accurate and continually refined models (logic simulation, process, fault simulation and grading, timing analysis, and testability analysis) are required for first-time functional success of a design.

Use of cross-functional teams to apply design for manufacturability, design for reliability, design for test, design for packaging, and design of experiments techniques at the IC concept stage.

Page 3

Use of quality function deployment to aid in determining what the customer wants.

Move testing farther up the IC manufacturing process, rather than being an end-of-the-line gate.

On-chip test structures and process monitors are used by the IC supplier to monitor the wafer fabrication processes and make appropriate corrections/adjustments in essentially real time.

The extensive use of continuous improvement statistical process control techniques has become a way of life for the IC supplier.

Since Hewlett-Packard's 1980 announcement, U.S. materials, equipment, and IC manufacturers have worked feverishly to improve the quality of their materials and products. The improvement has been spectacular. As of this date, ICs produced by U.S. manufacturers are truly world class. Quality is no longer a differentiator, it is the table stakes required to get into the game. Thus U.S. IC manufacturers cannot stop their continuous quality improvement efforts. They must maintain their focus on quality.

Every person in the semiconductor industry must be dedicated to the production of quality products. Unless every person has that dedication, production yields and volumes quickly suffer, profitability drops, and company survivability soon becomes an issue. This requires formalized quality procedures and a company-wide quality mindset.

So much for historical perspective.

Now to the specific issues that affect IC quality. From a global IC design, manufacturing, and use perspective, sources of poor quality typically include and can be found.

In the design phase

Process model errors/shortcomings

No specifications

Specification errors

Improper and inadequate component characterization

Design errors

Inadequate design reviews

In the manufacturing phase

Material incompatibilities

IC fabrication errors

Wafer probe testing errors

Packaging errors

Packaged part testing errors

Burn-in testing errors

Page 4

In OEM (original equipment manufacturer) construction phase

PCB assembly (soldering) errors

Processing damage

Fabrication errors

Acceptance testing errors

Board and system-level testing errors (timing errors!)

Handling (electrostatic discharge [ESD])

Improper part usage/application

In field operation phase

Environmentally induced sources of error (temperature, radiation, vibration)

Voltage transients

Handling

Untrained personnel

According to IBM (E. Fishkill, N.Y.; personal communication), the two challenges in improving quality during processing are to improve the overall defect density of the product and to identify and eliminate mavericksproduct that has been misprocessed and that has a significantly higher defect density and is inadvertently shipped to customers. Additionally, when dealing with the topic of IC quality one must consider more than the stand-alone IC. In today's environment one must view the IC and its total interconnection means to the PC board as an entity, a system if you will: the IC attachment to the PC board (i.e., solder joints); the PC board traces; the physical board layout and construction (ground planes, signal lines, cross-talk, power planes, electrical termination, thermal properties, etc.); PC board edge connectors and backplanes (board-to-board connection). This view must be taken because the IC is no longer the weakest link in system quality and reliability. Less than 5% of printed wiring assembly problems can be traced to the individual IC. The majority of problems are due to the following causes:

1. Connectors

2. Handling issues (mechanical damage, ESD)

3. PCB assembly problems (attachment to PCB, workmanship)

4. Solder joint integrity/reliability (attachment problems, mechanical support problems)

Why has the focus shifted from the individual IC to the total interconnection issue? The answer is severalfold:

1. ICs are of higher quality and more robust.

2. PC boards are more complex (multilayer with fine geometries).

3. The industrial environment is more severe.

Page 5

This does not mean that we lessen our concern for IC quality. Quite the contrary. IC quality is the basis for system reliability and the focus of this book. The following chapters present the details of where errors occur in the IC wafer fabrication, assembly, and test processes and how they manifest themselves in the finished product.

Before we embark on the details of the IC quality journey, it is important to understand (1) the impact integrated circuits have on electronic product design and content and (2) the many changes (trends) that are shaping the IC industry complexion and will affect IC quality and reliability.

Trends

Electronics is important; it has literally transformed the world. It is the key ingredient of a nation's industrial and defense competitiveness and quality of life. In the United States electronics has become the largest manufacturing sector. Electronics continues to spin off new markets and industries as it grows, and it is integrated circuit technology that is the engine that drives all electronics-based and knowledge-based markets. Integrated circuit manufacturing is an enabling technology; i.e., it makes many things possible.

Figure 1.1 is a diagram that depicts the electronics food chain, beginning with the raw materials at the apex of the inverted pyramid and proceeding through to semiconductor equipment, to semiconductor manufacturing, and, finally, to electronic systems. Notice the multiplier (leverage) effect in going from raw materials and equipment to semiconductor manufacturing (almost 4X), and from semiconductor manufacturing to electronics systems (8X). This diagram dramatically illustrates the importance of electronics both in a nation's economy and in the global economy.

IC Technology Acceleration

Developments in integrated circuit technology are proceeding at a rapidly accelerating pace. New technologies are supplanting existing ones faster than before, so much so that Texas Instruments officials have stated that, New technologies are coming on-line so fast that we cannot adopt them in our new products fast enough. (S. Golshan, Texas Instruments; personal communication).

The rapid changes taking place in integrated circuit design and technology development, and the pressure of bringing the resultant products to market rapidly, are bringing to bear fundamental changes in the thought processes of testing these circuits.

Testability must move forward to the circuit design stage and not wait until the design is fixed. As such, the circuit designer must address the issues of design-for-testability, built-in self-test, and fault coverage up front, on an equal-share-of-mind basis with the logic design.

Page 6

Figure 1.1
1993 and 1994 (forecast) worldwide electronics
marketplace. (Courtesy of ICE Corp., STATUS
1994.)

This chapter presents some of the significant trends that are taking place in the IC industry and that will ultimately impact upon testability.

Table 1.1 summarizes the salient integrated circuit trends that are occurring. Each of these items will be substantiated by supporting data. ICs are advancing on two fronts simultaneously, almost paradoxically:

1. At the very-large-scale integration/ultra-large-scale integration (VLSI/ULSI) level with increased on-chip functional integration (memories, microprocessors, digital signal processors, and ASICS, for example).

2. At the small-scale integration/medium-scale integration (SSI/MSI) glue logic level with high performance (blazing speed <1 ns, and ultra-low power consumption).

Several examples are presented to show the increase in technology complexity. The first compares a 7400 bipolar transistor-transistor logic (TTL) NAND gate with a 256 K complementary metal oxide semiconductor (CMOS) static RAM:

Page 7

Table 1.1 Integrated Circuit Trends

Technology is rapidly accelerating

Greater functional density (complexity)able to pack more into a smaller space.

Higher operating speed (MHz, MIPs).

Lower operating voltage (5 to 3.3 to 1.5 V).

Larger IC package sizes due to increased use of I/O-intensive ASICs.

More extensive use of ASICs and MCMs.

The ability to effectively test, package, and remove the heat from state-of-the-art ICs will limit their growth and significantly impact upon equipment design.

IC suppliers have stopped designing new logic families; building functions out of simple gates is no longer practical.

Higher quality products

Application of concurrent engineering, design-of-experiments, design-for-manufacturability, design-for-reliability, and design-for test practices at the inception of product development build quality into the product at the outset.

Increasing importance of design automation to increase first-time silicon functional success by designing quality into the product.

IC suppliers are moving to eliminate final electrical test. Instead, they use comprehensive, tightly guard-banded AC, DC, and functional tests at wafer probe. Final electrical test is used as a gross check for assembly defects.

Increased use of process models for each wafer fabrication tool to reduce defects and increase first time silicon success; i.e., the need for extremely tight process control.

Eliminate 100% incoming inspection and end-of-line testing.

Many designs with small manufacturing runs.

Multiple sourcing of new devices is on the wane.

Time is becoming a strategic weapon.

Decreasing product life cycles (24 years).

Shorter time to market.

Product development costs are increasing geometrically such that no one company can go it alone. Thus, the proliferation of strategic alliances: design/manufacturing/foundry.

Global dispersion of manufacturing.

Increasing appearance of fabless IC suppliers.

More services are outsourced than ever before as companies refocus on their core business.

Increased incidence of elimination of nonprofitable products, leading to obsolete and end-of-life parts issues.

7400 NAND gate

36 transistors

60 contacts

256 K SRAM

1.5 M transistors

4 M contacts

The second example compares 1970 state-of-the-art technology with 1989 state-of-the-art technology by number of mask steps and active layers:

Page 8

1970

NMOS Technology

4 active mask steps 20 major process activities

1989

Double metal CMOS technology

>10 active mask layers 50 major process activities

The third example of increased technology complexity is shown in the progression from SSI in the 1950s to VLSI circuits of the present time in Table 1.2.

Figure 1.2 compares feature size, metal layers, and unloaded gate delay for bipolar technology from 1978 to 1991. Also shown is a cross-section diagram of a 1991 state-of-the-art bipolar IC with four layers of interconnect (metallization). Figures 1.3, 1.4, and 1.5 show the increase in density trends for memories (1 K to 256 M) and microprocessors (4 bit to 32 bit), the increase in IC die size trends for the same memories and microprocessors, and the reduction in feature sizes for production as well as experimental circuits, respectively. From Figure 1.3 it is seen that memory density doubles every 3 years, memory die size increases by approximately 50% every 2.5 years (Fig. 1.4), and tight production memory feature size decreases at a rate of approximately 25% every 2 years (Fig. 1.5).

CMOS has become the primary technology for fabricating integrated circuits, moving from a small percentage (12%) of all ICs manufactured in 1982 to 82% forecast by 1996. Bipolar technology has become a special technology having flip-flopped with the percentage of CMOS ICs from 45% in 1982 to 10% of all projected ICs manufactured in 1997. These data are shown in Fig. 1.6.

VLSICs, due to their small geometries, have much higher operating frequencies and thus speeds. IC operating frequencies will increase in the manner shown in Fig. 1.7. In fact, digital ASICs and VLSICs look like radiofrequency (RF) circuits, and must be treated as such, with proper transmission line termination, cross-talk protection, and grounding, for example.

Then, too, the operating voltage is being reduced due to both the physical limitations of materials used to manufacture ICs and the high levels of integration being achieved. Specifically, the smaller geometries required for start-of-the-art ICs (i.e., 64 Mb, 256 Mb, and 1 Gb DRAM) require lower power supply voltages, due to the dielectric and metallization thickness issues and transistor breakdown characteristics. The portable personal computer is driving the trend toward reduced operating voltage, going from 5 V to either 3.0 or 3.3 V now, and eventually to 1.5 V. This change (5.0 to 3.3 V) will double the battery life by reducing power dissipation. However, as the voltage is reduced, the operating speed (frequency) is reduced, the devices become more sensitive to static discharge handling, and there are smaller noise margins. All of this means that special care will be required when handling lower voltage ICs during equipment manufacturing.

Page 9

Table 1.2 Progressive IC Technology

Dates

Integration level

Number of transistors

Equivalent gates

Typical functions or systems

Typical number at I/Os

1950
SSI

140

110

Single circuit function (e.g. transistors)

14

Late 1960s
MSI
40400

10100

Functional network
24

Late 1970s
LSI
404500

1001000

Hand calculator or digital watch

48

Mid 1980s
VLSI
4500300,000
100080,000
Microprocessors
64300

Present
ULSI
Over 300,000
Over 80,000
Computer on a chip
200400

Page 10

Year
Feature size (m)
Metal layers
Process keys
Unloaded gate delay

1978
4
1
Oxide isolation with diffused junction

5 10 ns

1980
3
1
Oxide isolation with implanted junction

1 5 ns

1981
2
2
Oxide isolation with implanted junction

500700 ps

1983
1.5
2,3
Oxide isolation with implanted junction

300500 ps

1985
2
3
Poly emitter and resistors, silicide interconnect

70150 ps

1988
1.5
3
Poly emitter and resistors, silicide interconnect

50 70 ps

1991
0.8
4

Poly emitter and resistors, silicide interconnect, stepper or direct-write lithography

10 50 ps

Advances in ECL Technology

Figure 1.2
(a) Bipolar IC technology summary. (b) Schematic cross
section of a typical interconnect structure.

The low operating voltage road map that has been plotted is as follows:

64 Mb DRAM

33.3 V

256 Mb DRAM

2.5 V

1 Gb DRAM

1.5 V

Page 11

Figure 1.3
Integrated circuit density trends. (Courtesy of ICE Corp., STATUS 1994.)

What kind of protective packages will be required to house these die? Since about 1984 a fundamental transformation has been occurring in earnest, from through-hole insertion packages (dual-in-line packages) to surface-mount packages (quad flat pack, leadless chip carrier, small outline J lead, etc.). Surface-mount technology (SMT) will grow from 44% in 1993 to 75% of all packages by 1998, as shown pictorially in Figure 1.8, being led by the small outline integrated circuit/small outline J-lead (SOIC/SOJ) and plastic leadless chip carrier/plastic quad flat package (PLCC/PQFP) package styles (Table 1.3). The change to SMT packages impacts upon handling during PC board assembly,

Page 12

Figure 1.4
Integrated circuit die size trends. (Courtesy of ICE Corp.,
STATUS 1994.)

leading to a host of quality and reliability usage issues. With surface mount technology, ICs can no longer be viewed individually, but rather must be considered in conjunction with their mounting on the PC board and the solder as a system.

Adding to the package style transformation is the rapid increase in the number of external package leads (or pins). Figure 1.9a illustrates the dramatic growth trend in pin count from 68 in 1980 to 512 in 1990. Figure 1.9b shows the pin count trend for memories, microprocessors (MPUs) and ASICs, historically from 1960 to the beginning of the century. Integrated circuit packages with pin counts of 900 to 1000 will be in production by the year 2000. Larger package sizes (measured by the number of leads) are required to accommodate large die sizes (as was shown in Figure 1.4), especially of application-specific integrated circuits (ASICs) which are input/output (I/O) intensive (versus memories), and which make less efficient use of silicon real estate. Figure 1.10 shows the trends

Page 13

Figure 1.5
Integrated circuit feature size trends. (Courtesy of ICE Corp., STATUS 1994.)

relating the number of signal pins to the gate count. Memories, being orthogonal structures, have the lowest I/O pin count versus gate count; gate arrays (ASICs) have the highest. Table 1.4 shows the gate-to-I/O pin ratio for microprocessors.

The large number of leads had led to a shift to smaller (fine pitch) lead spacings (50 to 25 to 10 mil) and a corresponding increase in testing and handling (lead damage), assembly, and electrical performance (cross-talk, ringing, and spurious noise) problems. The high gate (or transistor) counts per IC demand innovative packaging techniques such as the use of multichip modules (MCMs) to increase system performance and decrease size. MCMs, and the ASICs and VLSICs that constitute MCMs, present some serious test problems. Figure 1.11 depicts the relationship between increased gate count, increased pin (lead) count, and viable package style: dual-in-line package, quad flat package, pin grid array, and MCM.

All of the aforementioned technology trends lead one to the following conclusionthe growth of VLSI (including ASIC) and ULSI circuits will be limited by (1) the ability to package the devices. (2) the ability to effectively remove internally generated heat from the chip-package combination, and (3)

Page 14

Figure 1.6
19821998 IC technology trends and projected trends. (Courtesy of ICE Corp., STATUS 1994.)

Figure 1.7
Growth in device speed.

Page 15

Figure 1.8
IC package market share. (Courtesy of ICE Corp., STATUS 1994.)

the ability to properly test the devices, thus significantly impacting upon equipment/product design, performance, quality, and reliability.

Electrical testing of very-large-scale and ultra-large-scale integration devices may account for as much as 45% of total product costs (Fig. 1.12), and these costs may escalate as VLSI and ULSI devices continue to shrink.

Table 1.3 Industry Usage of IC Package Styles

1993

1998

Package type

Units (M)

Percent of total

Units (M)

Percent of total

19931998 CAGR (%)

Plastic dip

21,350

52

12,900

23

-10

Cerdip

1300

3

725

1

-11

Sidebraze dip

50

<1

35

<1

-7

Ceramic PGAa

175

<1

280

<1

10

Plastic PGAa

150

<1

675

1

35

SOICb

8100

20

19,410

34

19

SOJ

2300

6

9560

17

33

PLCC

4175

10

6300

11

9

PQFP

1725

4

4200

7

19

LLCC/LDCC

375

1

515

1

6

Otherc

1000

2

2400

4

19

Total

40,700

100

57,000

100

7

a Includes ball grid arrays (BGAs).

b Includes UTSOPs, QSOPs, and TSOPs.

c Includes TAP-on-board, COB, flatpacks, metal cans, etc.

Source: ICE Corp., Status 1994.

Page 16

Figure 1.9
(a) Package pin count growth trends. (b) Pin count trends for memories, microprocessors, and ASICs. (Courtesy of ICE Corp.,
STATUS 1994.)

Page 17

Figure 1.10
I/O pin count versus complexity. (Courtesy of ICE Corp., STATUS
1993.)

Table 1.4 The Growing Gate-to-I/O Pin Count Ratio: Microprocessor (mP) Size Versus Pin Count

mP

Word size (bits)

Manufacturer

Approximate no. of transistors

Pin count

Gate/pin ratioa

4004

4

Intel

2,300

16

48

6800

8

Motorola

4,000

40

33

8085

8

Intel

15,000

40

125

8086

16

Intel

29,000

40

242

WE32100

32

Bell Laboratories

180,000

132

341

68020

32

Motorola

200,000

114

439

80386

32

Intel

275,000

132

521

HP9000

32

Hewlett-Packard

450,000

83

1350

aGate/pin ratio was estimated using four transistors per gate in CMOS technology and three transistors per gate for nMOS and pMOS technology.

Page 18

Figure 1.11
Package style trend chart as a function of gate and pin counts.

Figure 1.12
Very-large-scale IC test development costs swamp product design and
development costs. Test development effort increases as a percentage
of total device development costs of next-generation IC technology.

Page 19

The Issue of Quality

In today's environment quality is not an issue. It is a given! The starting point to participating in the global marketplace is a high-quality product as determined by the user (customer). Thus, quality is the price (table stakes if you will) of getting into the game, and to stay in the game, a total quality system based on a continuous quality improvement process must be put into place. Quality is the never-ending driving force to competitiveness.

Quality must be designed and built into the product at the outset. One cannot wait until the IC is manufactured and then use testing to provide a good product. Quality must be built into the IC by assembling a multi-disciplined design team that jointly addresses design, manufacturability, fault coverage, testability, and reliability issues before the design begins, throughout the design process, and then carrying on right into the production stage. This process is aided by the availability of capable design automation tools in conjunction with accurate and continuously refined logic and process model libraries.

In the early 1960s, it was indeed rare that one obtained first-pass working (functional) silicon for even a simple device such as a 7404 logic device. However, with currently available design automation tools, first-time functional silicon is obtained almost 100% of the time with such complex circuits as megabit memories, 32-bit microprocessors, and ASICs. This happens because a given integrated circuit, by virtue of these computer-aided tools,

Is debugged before it is ever manufactured (via logic simulation, timing analysis, design rules check, and layout analysis)

Has its fault coverage and testability established up front during circuit design by the implementation of design-for-test (DFT) and built-in self-test circuitry and techniques

Has eliminated costly hit-and-miss design-fab-design-fab iterations

Has the est strategy and production test vector set developed during IC circuit design

Because of this concern for quality in conjunction with the evolution of design automation tools, there has been a dramatic improvement in the quality and reliability of integrated circuits during the past 10 years (see Fig. 1.13). But, quality improvement is never over. It is a never-ending daily taskto continuously improve and make higher quality ICs.

Electrically Testing ICs

As was both stated and alluded to earlier, electrically testing an integrated circuit is a complex issue compounded by the many technological trends simultaneously taking place. In this small section I just want to emphasize two points, since a

Page 20

Figure 1.13
Trends in reliability goals. Circles, long-term failure rate
goals (FIT); squares, infant mortality goals (DPM).

later chapter (Chapter 8) discusses the issues of testing VLSICs and ASICs in greater detail.

1. As device complexity increases, fault coverage decreases, requiring the use of design-for-test (DFT) techniques.

a. On-chip test structures.

b. On-chip circuits incorporating boundary scan or level-sensitive scan design (LSSD) to ease testing.

c. Built-in self-test.

2. A transformation in electrical testing of VLSICs and ASICs is occurring. Test generation is moving closer to and becoming a part of the design environment (i.e., integrated design and test).

Other Trends

In the 1960s and 1970s, the integrated circuit industry was characterized by a small number of standard products manufactured in high volume: 100 or so standard products (designs) each with an average of 500,000 devices manufactured. With the availability of design automation tools to virtually everyone (especially systems designers), and the establishment of silicon foundries and third-party design houses, the integrated circuit industry has changed such that it is now characterized by thousands of designs with small manufacturing runs (200 or so devices on average). This change is shown in Fig. 1.14. Thus, the industry has seen a major shift from a small number of high-volume parts to a large number of small-volume parts. Compounding the issue is that many of the

Page 21

Figure 1.14
Worldwide IC designs.

thousands of designs will never get to production. The designs and operating functions are being changed, modified, upgraded, or dropped altogether. Nonetheless, these devices need to be electrically tested. Are the parts good? To what specifications? How good are they? Will they work in my application? Test vectors must be developed rapidly to support the manufacturing/production function, thus putting much stress on both the circuit designer and test engineer.

Lastly, there is the issue of time. IC design cycles are decreasing. This, plus the complexity of ICs and the development costs, requires cost-sharing partnering arrangements to bring out products rapidly. Time is a twofold issue. Product life cycles (both ICs and equipment) are decreasing rapidly. Generally speaking, glue logic ICs have a life of 7 years, memories 5 years, microprocessors 37 years, and ASICs 1 year or less. Then there is a shorter time to market. IC suppliers must bring out even more complex IC designs at an ever increasing rate, yet the development cost of these designs is accelerating at a rate typified by the following example:

8086

Microprocessor

$25M

80386

Microprocessor

$100M

80486

Microprocessor

$250M

A 12 calendar-year time to market is not uncommon for VLSI circuits. Because of these time pressures, coupled with the competitive nature of the industry, the IC suppliers must recover their design and process development and test development costs up front.

Not only are the IC suppliers faced with shorter prototyping and product release times, but they must bring the IC to market when scheduled or incur a serious profit shortfall as shown in Fig. 1.15. Thus, time-to-market is critical because it affects both market share and profit.

Both of these issues of time place enormous stress on test strategy

Page 22

Figure 1.15
The high costs of arriving late.

development. For complex devices, the IC suppliers simply cannot test for all possible usage conditions (Intel's 80486 microprocessor, for example). What we are coming to is the need for application-specific testing. However, the issues are the same. The IC suppliers cannot afford to fail good devices in their electrical test areas (Type I errors), since this increases their costs and all users must pay for these, nor can they pass bad devices (Type II errors) to the user since a given user will pay for these parts. In both cases the IC supplier's reputation will suffer and it will lose its market share.

Thus, in summary, the many IC technology trends taking place will have a significant impact on the failure mechanisms encountered, testability, quality, application usage, and reliability.

References

1. R. H. Williams and C. F. Hawkins, Errors in testing, International Test Conference Proceedings, 1990.

2. R. H. Williams et al., Testing error data and calculations in an IC manufacturing process. International Test Conference Proceedings, 1992.

3. Wonder chipshow they'll make computing power ultrafast and ultracheap, Business Week, July 4, 1994, pp. 8692.

Page 23

PART I
INTRODUCTION TO INTEGRATED CIRCUIT MANUFACTURING PROCESSES

In the IC industry change is the norm. Circuit design and wafer fabrication processes are being changed, modified, and innovated to increase both the electrical performance characteristics and producibility (yield) of finished ICs. Memories (DRAMs, SRAMs, EPROMs, Flash), are the vehicles used to demonstrate and refine new and/or modified processes by virtue of their high production volumes and repetitive on-chip structures where asset (equipment) utilization and lowest cost are important. They are process drivers. Application-specific ICs (ASICs) are technology drivers that demonstrate new and/or modified designs where cycle time is important. Once these design and process innovations are refined, they filter downward to all areas involving mature products that may be restructured, redesigned, or restepped for large wafer sizesor a combination of all of these in order to decrease die size, obtain more die per wafer, decrease the cost per die, and increase profits and inherent device quality levels.

At the same time, users have become more concerned about inherent device quality because of higher printed circuit board (PCB) densities, and the availability and use of dense very-large-scale integration (VLSI) devices fabricated with new and complex process technologies. The failure of a VLSI device

Page 24

Figure I.1
Integrated circuit manufacturing process overview.

Page 25

in a circuit board has a much more pronounced effect on the end-equipment operation than did a simple gate failure in prior generations of the equipment design. Thus, the increased use of both integrated circuits and VLSI circuits in electronic systems has been accompanied by an increased concern over IC rejects and IC quality.

In this section, the IC manufacturing process is discussed solely from a perspective that details the factors in this process that affect the finished IC quality, rather than from a theoretical design perspective. Up front it must be stated that everything in an IC is in an unstable environment as a result of the complex chemical makeup and physics of materials interactions (on an atomic particle level) that come into play in the fabrication and assembly processes. The materials want to diffuse into each othersilicon into the bonding wires; aluminum from bonding wires into the package and die attach pads; oxygen from the cavity into silicon; moisture and contaminants in the cavity, and the like. These factors are affected and accelerated by time and temperature conditions and impact device quality.

Although several typical wafer fabrication (process) sequences are presented, they are to be considered as generalized examples to demonstrate to the reader the steps involved in making an IC and are subject to much variation from supplier to supplier as the state of the art changes. The various processing steps discussed are valid in and of themselves, but when combined to form the total process may vary in where they fit into the sequence, if they are used at all, or in how many times each step is used in a given process. Furthermore, there is much variation within each processing step from supplier to supplier and among the product lines of a given supplier, such as the length of time and the temperature under which impurities are diffused into a wafer.

Figure I.1 presents a global overview of the integrated circuit manufacturing process which greatly simplifies its inherent complexity but serves to highlight the salient process steps for the reader.

Page 27

2
Front-End IC Fabrication Operations

The IC manufacturing process involves the disciplines of chemistry, physics, materials science, thermodynamics, and statistics in a complex interrelationship in front-end (wafer fabrication) and back-end (assembly and test) operations.

Basic IC Materials

Semiconductor materials are crystalline, with a simple physical and chemical structure. They are neither good conductors of electricity nor good insulators. While there are many semiconducting compounds and elements, silicon is the primary material for ICs. Monocrystalline silicon in its pure, intrinsic form exhibits few useful properties. However, the carefully controlled addition of trace amounts of specific impurities to dope the silicon makes it possible to alter its characteristics in an extremely useful manner.

Semiconductor-grade silicon is refined from common beach sand. This is reduced to polycrystalline high-purity silicon in the form of long, slender rods. These rods are then changed to single-crystal silicon by means of either the Czochralski (CZ) or the float-zone method. A new development, magnetically

Page 28

grown Czochralski (MCZ) silicon crystals, has been shown to have lower defect densities and less warpage than conventional CZ silicon. MCZ also has been found effective in linearizing oxygen defects through the crystal rather than allowing the concentration at the seed end that has typified earlier silicon, resulting in low leakage currents.

The resultant crystals are then ground to a uniform diameter with diamond grinding equipment. Each crystal is sawed into thin slices, or wafers. These wafers, which are as brittle as glass and are between 10 and 20 mils thick, are etched and lapped on both sides to remove any structural damage that might have occured during sawing. Wafers that will be used to make ICs are then polished to a mirror finish on one side.

After polishing, the wafers are thoroughly cleaned. Cleaning involves solvent degreasing using heated detergent solutions under ultrasonic agitation and wiping. The final cleaning is often chemical etching. This produces a wafer suitable for use in manufacturing integrated circuits. Most IC suppliers buy prepared wafers (in 5-in., 6-in., and 8-in. diameters) of silicon ready for the first manufacturing step with the desired resistivity.

The crystalline structure (lattice) of silicon is basic to semiconducting action. Pure silicon at room temperature is a poor conductor of electricity because each atom in the crystal has four other silicon atoms around it, which in turn are bound to four neighboring atoms, and so on. So all the outer electrons in a perfect silicon crystal are linked and are not available to conduct electricity, if the effects of temperature are ignored.

Due to thermal energy, however, at any temperature above absolute zero (0°K), some of these relatively weak covalent bonds are broken, where the number of such broken bonds is a function of the temperature. Broken bonds free the electrons involved, which are then available to conduct electricity. Similarly, broken bonds corresponding to the absence of an electron (Known as a hole) are free to move through the crystal lattice. The electrons are negative charge carriers, while the holes comprise, in effect, positive charge carriers (absence of an electron). (One can consider the holes as analogous to bubbles in a liquid, in which the bubbles, which are actually the absence of liquid, are free to move through the liquid.) Both types of charge carriers are capable of conducting an electric currentor, more precisely, their ordered movement may comprise an electric current. However, if other elements are introduced as substitute atoms into the silicon crystal lattice, the electrical properties of silicon can be altered in a controlled manner. The substitution of dopant atoms that are appropriate for this purpose are certain members of Groups III and V of the Periodic Table of Elements (see Appendix) that contain three and five valence electrons, respectively. Among the Group III elements that have been used to dope silicon are boron, gallium, and indium. Probably the most widely used of these is boron, which has only three electrons in its outermost orbit.

Page 29

When boron is present in the crystal lattice, it is deficient by one electron of the four needed for covalent bonding with neighboring silicon atoms. To provide the missing fourth electron, it accepts one, thereby producing a hole (corresponding to the absence of the electron it accepted). The Group III elements are known as acceptors, their presence in the silicon crystal lattice produces p-type silicon, and they conduct by means of positive charge carriers (holes).

Conversely, elements in Group V of the Periodic Table that contain five electrons in their outermost orbits (e.g., phosphorus) are known as donor elements. In the silicon crystal lattice, when they share electrons with their nearest neighbors only four electrons are needed, leaving one unused electron. This electron is then free to carry current. When silicon is doped with donor atoms, it is known as n-type silicon, and conduction occurs by negative charge carriers (the free electrons).

Doping Silicon

Active circuit elements such as metal oxide semiconductor (MOS) transistors and bipolar transistors are formed in part within the silicon substrate. To construct these elements it is necessary to selectively introduce impurities, that is, to create localized n-type and p-type regions by adding the appropriate dopant atoms.

The process of introducing controlled amounts of impurities (Group III or Group V atoms) into the lattice of monocrystalline silicon is known as doping. Basically, an appropriate compound of the desired element (very often its oxide) is deposited on the surface of a silicon wafer, which is subjected to elevated temperature. The dopant then diffuses into the silicon. As long as there is an excess of dopant present on the silicon surface, the surface concentration of these atoms in the silicon will be determined by the solid solubility of the element in silicon, which is a function of temperature alone. Maximum solid solubilities of typical silicon dopants range from 5 × 10²⁰ atoms/cm³ for boron through 1.4 × 10²¹ atoms/cm³ for phosphorus, and up to 1.8 × 10²¹ atoms/cm³ for arsenic.

The elements that are used as dopants are impurities only in the sense that they represent a departure from pure silicon crystal. The silicon itself is very pure, as are the dopant elements. In fact, silicon is the purest raw material ever produced in large quantities. Impurity levels of one part or less per billion are common.

Dopant elements may be added to the silicon at several points in the IC manufacturing process as will be discussed in the balance of this chapter. The effects of dopants give silicon nearly any desired resistivity, and either p- or n-type conductivity. The boundary between a p-type region and an n-type region is called a p-n junction. The active portion of a semiconductor device consists of p- and n-type regions and the junctions between them.

The dominant role of silicon as the material for integrated circuits is attributable in large part to the properties of its oxide. Silicon dioxide is a clear

Page 30

glass with a melting point higher than 1400°C. It plays a major role both in the fabrication of silicon devices and in their operation. The combination of desirable properties of SiO₂ is unique. SiO₂ is stable in a wide range of ambient environments, and a high-quality film can be conveniently grown on single-crystal silicon by means of thermal oxidation.

IC Design

The structure of an integrated circuit is complex both in the topography of its surface and in its internal composition. Each element of a IC has an intricate three-dimensional architecture that must be reproduced exactly in every circuit. The structure is made up of many layers, each of which is a detailed pattern. Some of the layers lie within the silicon wafer and others are stacked on the top. The manufacturing process consists of forming this sequence of layers precisely in accordance with the plan of the circuit designer.

Before examining how these layers are formed it will be helpful to take an overall look at the procedure by which an integrated circuit is transformed from its conception, by the circuit designer, to a physical reality.

Circuit design starts with a functional block diagram or description of how the circuit must operate. This block diagram shows the operation of the circuit without any of the design specifics. The circuit designer is concerned with the electrical functions of the finished device or circuit parameters and then designs the individual on-chip semiconductor components required to produce the desired circuit function. The circuit designer also selects the processing steps that will be required to manufacture the circuit. Next, the actual design of the IC begins. The size and approximate location of every circuit element are estimated. Much of this preliminary design work uses computer-aided design (CAD), with the aid of engineering workstations that can simulate the operation of the circuit without actually physically constructing the circuit in much the same way that electronic television games simulate the action of a table-tennis game or a space war. The circuit designer monitors the behavior of the circuit voltages, using a logic simulator, and adjusts the circuit elements until the desired behavior is achieved.

The inputs to the logic simulator are the assembled network description and a sequence of design verification tests, either supplied by the customer or developed by the supplier. The computer applies this sequence of tests to the input of the assembled network. When simulation is complete, a printout of the logic states of inputs, outputs, and selected internal points as a function of time is obtained. In essence, the computer is performing a function similar to breadboarding the circuits but in this case a more concise picture of the circuit response versus time is achieved. A study of the simulation printout is made to verify the correctness of the stored network.

After the stored network is verified, a propagation delay program estimates

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the capacitance associated with each node in the network and calculates the propagation delay through each logic gate. The designer analyzes this information for possible speed problems and determines which interconnection paths must have minimum capacitance. When the chip layout has been completed, the exact node capacitances are automatically computed, based upon layout information. The results are reexamined as a final check for proper AC performance.

Computer simulation is less expensive than assembling and testing a breadboard circuit made up of discrete circuit elements; it is also more accurate. The main advantage of simulation, however, lies in the fact that the designer can change a circuit element merely by typing in a correction on a keyboard, and can immediately observe the effect of the modification on the behavior of the circuit. The topic of circuit design for VLSI circuits using engineering workstations is discussed in greater depth elsewhere in this volume.

Figure 2.1 is a schematic diagram of a 709 operational amplifier as an illustrative example of a completed IC schematic design. This is a very simple and archaic IC measuring 38 × 38 mils but is useful for showing the different masking steps.

Once the designer is satisfied with the circuit simulation, the automatic circuit layout (transforming the circuit schematic diagram to a physically realizable topographical implementation), namely, the artwork generation, giving the precise position of the various circuit elements, begins. Either the designer calculates the physical dimensions required to produce the desired electrical parameters or the information is stored in the computer (the design data base) and the CAD system determines the circuit elements that will be used. Typically, the vertical dimensions determine diffusions, chemical vapor deposition (CVD), and doping thickness specifications. The horizontal dimensions determine the wafer pattern dimensions and are the basis for a scaled drawing of the finished circuit called a composite drawing. During this phase, any constraints, such as pin configuration, critical speed paths, and any peculiarities of the circuit, are fed into the CAD system. Modifications to the automatic placement and wire routing can be manually entered to fulfill any special circuit constraints. These modifications are automatically checked for layout rule violations.

After all modifications have been made, a computer-driven plotter produces a symbolic drawing of the circuit. The layout specifies the pattern of each layer of the integrated circuit. The goal of the layout is to achieve the desired function of each circuit in the smallest possible space. However, the older method of drawing circuit layouts by hand (Fig. 2.2) has not been entirely replaced by the computer. Many parts of a large-scale integrated circuit are still drawn by hand before being submitted to the computer.

At each stage of this process, including the final stage when the entire circuit is completed, the layout is checked by means of detailed computer-drawn

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Figure 2.1
709 Operational amplifier (op amp) schematic diagram (From Ref. 1.)

plots. Since the individual circuit elements can be as small as a few micrometers across, the checking plots must be greatly magnified. Typically, the plots are 500 times larger than the final size of the circuit.

Figure 2.3 shows the results of a CAD of a complementary MOS (CMOS) ALU bit slice, as an illustrative example. The functional block diagram is shown in Fig. 2.3a. Since the carry section of an ALU often limits its overall performance, the designer may wish to experiment with its circuitry in schematic form, as shown in Fig.2.3b. Transistors can then be sized and detailed timing simulations performed. Figure 2.3c is a schematic diagram of the ALU showing

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Figure 2.2
Hand-drawn composite. (From Ref. 1.)

all transistors. Once the transistor-level circuitry is verified as correct via logic simulation and timing analysis, the layout can be generated (Fig. 2.3d).

The time required to complete the task of circuit design and layout varies greatly with the nature of the circuit. For microprocessors, typically the most difficult circuits to design, the design can take several years and hundreds of engineers. For memories that contain a largely repetitive pattern, the design and layout is accomplished more quickly.

Current LSI or VLSI circuit composite layer drawings may be as much as 20 ft square in size or larger for layout checking and verification purposes (see Fig. 2.4). These drawings are then reduced to the chips' final dimensions using a technique known as digitizing.

When the design and layout of a new circuit is complete, the computer memory contains a list of the exact position of every element in the circuit. From that description in the computer memory a set of plates, called photomasks (see Fig. 2.5), is prepared. Each mask holds the pattern for a single layer of the circuit. Since the circuits are so small, many can be fabricated side by side simultaneously on a single wafer of silicon. Thus each photomask, typically a glass plate about 610 in. on a side, has a single pattern repeated many times over its surface.

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Figure 2.3
Computer-aided design (CAD) layout example of CMOS ALU bit slice. Beginning with
the functional block diagram (a); replacing the carry block with transistor schematics (b);
leading to a computer transistor level schematic (c); and culminating in the
circuit layout (d).

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Figure 2.4
Computer-generated plot of 32-bit microprocessor chip
measures 17 ft². This IC contains 275,000 transistors,
which is small by today's standards. (Photograph by
Chuck O'Rear, courtesy of Intel Corporation,
copyright © 1986.)

Mask Making

Generation of the masks is a very detailed process. Typically, it involves generating a complete pattern for each layer of the circuit from the computer memory. This is done by scanning a computer-controlled light spot across a photographic plate in the appropriate pattern.

Figure 2.5
Example of a photo mask. (From Ref. 1.)

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This primary pattern, called the reticle, is checked for errors and corrected or regenerated until it is perfect. Typically the reticle is 10 times the final size of the circuit. An image of the reticle that is one-tenth its original size is then projected optically on the final mask. The image is reproduced side by side hundreds of times in a process called step-and-repeat. The constraints on both the mechanical system and the photographic system are demanding; each element must be correct in size and position to within less than 0.2 mm. The original plate created by the step-and-repeat camera is copied by direct contact printing to produce a series of submasters. Each submaster serves in turn to produce a large number of replicas, called working plates, that will serve for the actual fabrication process. The working plate may be either a fixed image in an ordinary photographic emulsion or a much more durable pattern etched in a chromium film on a glass substrate. Chrome masks, which are used almost exclusively today, have some distinct advantages over emulsion masks. They last for 15 times as many exposures and they have lower defect levels. A typical mask-making sequence is summarized in Table 2.1.

A complete set of correct masks is the culmination of the design phase in the development of the integrated circuit. Figure 2.6 shows the resultant masks for the 709 operational amplifier of Fig. 2.1. The application sequence of these masks in the fabrication process is shown in Fig. 2.7. The plates are delivered to the wafer fabrication facility, where they will be used to produce the desired sequence of patterns in a physical structure. This manufacturing facility receives silicon wafers, process chemicals, doping materials, and photomasks. Figure 2.8 summarizes the IC design sequence discussed thus far.

The masks, in addition to containing the IC detailed patterns, also have alignment marks and special test sites for process control measurements. Because of the complexity of the circuit patterns, alignment of the masks is very difficult. To simplify this process, alignment guides (or marks) are placed on each mask. These marks can take various shapes, with crosses and squares being the most popular.

Each manufacturing step produces a change in the silicon wafer, which is usually irreversible. If the process is flawed, very expensive scrap is made. The key to control is measurement. Too often variables are in such tiny areas that they cannot be measured, or the measurement is destructive. But if the

Table 2.1 Typical Mask-Making Sequence

1. Circuit layout
5. Generate master plates

2. Digitizing
6. Generate submaster plates

3. Pattern (reticle) generation
7. Generate working plates

4. Step and repeat operation

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Figure 2.6
Masks for 709 operational amplifier. (From Ref. 1.)

measurement is not made and a processing error occurs, the money spent on further wafer processing is wasted.

One solution to this problem is to put a small area for special process control test patterns on each wafer. These patterns range from simple rectangular regions for measuring sheet resistance of diffused layers, or dot patterns for checking alignment of photoresist patterns, to transistor structures typical of those buried deep within an IC. Measurements made on these structures can reveal much about the lot-to-lot reproducibility of processes, and can help pinpoint problems. This information more than compensates for that small area of each wafer that cannot then be used for salable devices.

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Figure 2.7
Application of photolithography to produce 709 operational amplifier ICs. (From
Ref. 1.)

Figure 2.8
Integrated circuit design flow showing steps from circuit design to
photomask generation sequence (From Ref. 2).

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IC Fabrication Sequence

The fabrication of integrated circuits consists of a series or sequence of the following process steps:

Photolithography

Junction formation

Dielectric formation

Silicon deposition

Doping

Metal deposition

Figure 2.9 shows a typical manufacturing sequence using these steps from circuit design to final test for silicon gate (CMOS) technology. More detailed discussions are now presented for each of these processing steps.

One of the major reasons for the use of silicon in fabricating ICs is its ability to grow a natural oxide (silicon dioxide). This oxide layer serves several functions in the manufacturing process.

Surface passivation: A layer of silicon dioxide reduces the susceptibility of the wafer surface to processing contaminates in two ways: It physically prevents the contamination from reaching the silicon, and since the layer grows down into the silicon wafer, continually creating a new surface, contaminates that may be present on the old surface are drawn up into the oxide where they are less dangerous.

Diffusion barrier: During the IC doping process, the dopants actually diffuse (penetrate) into the oxide surface. However, they move more slowly in the oxide than in the silicon. By property selecting the oxide thickness, the dopant is prevented from reaching the wafer surface.

Surface dielectric: At the end of the fabrication sequence the active regions in the wafer are connected by strips of aluminum running along the top of the oxide. The insulating property of the oxide prevents the metallization layer from electrically shorting to the silicon wafer. Shorting can occur if the oxide is too thin and ruptures under a voltage stress, e.g., ESD, or if there are pinholes present in the oxide for any reason. The structure is actually that of a capacitor, with the oxide serving as the dielectric. The region on the device where the oxide serves this function is called the field oxide.

Oxidation

If a wafer of silicon is heated in an atmosphere of oxygen or water vapor, a silicon dioxide film forms on its surface. The film is hard and durable and adheres well. It makes an excellent insulator. The silicon dioxide is particularly important in the fabrication of integrated circuits because it can act as a mask for the selective introduction of dopants.

As a first step in making an IC, the wafer is put in a high-temperature

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Figure 2.9
Typical silicon-gate CMOS manufacture sequence. (Courtesy of ICE Corp.)

Page 42

Figure 2.9
(Continued)

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furnace where an oxide layer is grown over its entire surface. The temperature is usually between 1000°C and 1200°C, and the atmosphere contains oxygen. The exact thickness can be accurately controlled by selecting the appropriate time and temperature of oxidation. For example, a layer of oxide 0.1 mm thick will grow in 1 h at a temperature of 1050°C in an atmosphere of pure oxygen. A layer five times thicker will grow in the same time and at the same temperature in steam.

Forming an oxide layer 10,000 Å thick consumes about 4500 Å of silicon and takes about 4 h to grow. Color changes with thickness, similar to oil film on smooth water, because of changes in the wavelength of reflected light. The color is used to judge the thickness and uniformity of the layer. Oxide layers are sometimes formed by anodizing or, alternatively, by a deposition process. Deposition gives a thick layer without consuming the substrate.

Oxidation and process temperatures are selected out of compromise. The temperature has to be high enough to cause the desired result in an efficient amount of time, but should be as low as is practical to minimize the inducement of crystal defects (this is true for all IC processing steps). At the upper end, 1200°C is the maximum temperature. At 1200°C, wafer warpage becomes excessive (especially for large-sized wafers) and the quartzware starts to sag and has a limited lifetime.

An important aspect of the oxidation process is its low cost. Several hundred wafers can be oxidized simultaneously in a single operation (batch process). The wafers are loaded into slots in a quartz boat, separated by only a few millimeters, and the boat is placed in the quartz tube of a furnace similar to a diffusion furnace. The setup of Fig. 2.10 is typical. The high-temperature furnace has a cylindrical heating element surrounding a long quartz tube. A

Figure 2.10
Open-tube oxidation-diffusion apparatus. (From Ref. 1.)

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purified stream of an oxygen-containing gas passes through the tube. The boats of wafers are loaded into the open end and slowly pushed into the hottest part of the furnace. The temperature in the process zone is controlled to an accuracy of better than one degree. Nitrogen is a protective environment and, in some processes, a carrier gas. Steam for oxidation is obtained by boiling the water in the flask, wet oxygen by bubbling O₂ through water heated to about 95°C, and dry oxygen by venting the oxygen tank into the tube directly.

Often the entire oxidation procedure is supervised by a small process control computer that monitors the temperature, directs the insertion and withdrawal of the wafers, and controls the internal environment of the furnace.

Photolithography

Fabrication of integrated circuits requires a method for accurately transferring the circuit patterns on each mask to the wafer. The IC is built up layer by layer (see Fig. 2.7), each layer receiving a pattern from a mask prescribed in the circuit design. The photoengraving process known as photolithography, or simply masking, is repeatedly employed for this purpose.

Photolithographic processes are employed in defining all geometries in a device pattern. Lithography involves the patterning of metals, dielectrics, and semiconductors. The patterns can be transferred into a material using either positive or negative masking techniques. The most common patterning technique employed in silicon processing uses a negative-density photomask to produce a positive-density pattern in negative photoresist. (The areas that are desired to be left on a wafer are clear on the photomask.) Ultraviolet (UV) exposure of the negative resist (through the clear areas of the mask) cross-links it, rendering it resistant to the developer-etchant. After development, the undesired material is removed by wet or dry etching where it is not covered by the photoresist.

The difficulties of lithography include resolution and etchability. While acceptable resolution may be achieved in most fabrication steps, the most critical gate processing in field effect transistor fabrication requires less than 0.5-mm resolution for state-of-the-art devices. In addition, some layers that must be patterned are not easily etched or may have poor selectivity compared to masking materials. Wet etchants usually achieve poorer resolution than plasma-etching techniques.

Most IC processes require a set of 510 such patterns, sometimes more. Each pattern must be aligned precisely with those already on the wafer. In making complex ICs, patterns must be aligned to within typically less than 0.2 mm across the entire area of a 200-mm (8-in.) wafer, for example. The difficulty is that line widths of 0.5 mm are commonly used in making ICs. A complex IC contains thousands of these 0.5-mm lines. So the patterns in all masks must align with each other to within substantially less than 0.5 mm. Without accurate mask alignment, yield drops rapidly to zero.

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For first mask alignment there is no pattern on the wafer to align to. The pattern has to be aligned to the crystal structure of the wafer. Since the crystal structure is not visible, the alignment operator aligns the mask pattern to the major wafer flat (Fig. 2.11). This is why all of the patterns are at right angles to the flat.

With manual alignment systems, the wafer flat is positioned on the aligner stage to an accuracy of ±2 degrees. On automatic aligners this step is automatically controlled.

After alignment to the flat, the wafer is automatically positioned under the mask and the exposure subsystem activated. First mask alignment requires no operator attention after the flat is positioned, and is the least critical in the entire process. All subsequent masks are aligned to patterns existing on the wafer via alignment marks in an automated alignment system.

It should be noted that within a mask set, two or three of the masks are more critical than the others. Also, within a particular mask level there are usually parts of the circuit that are more alignment sensitive than others.

A method of mask alignment and exposure used through the 1970s was called contact printing. In this method (which was useful through MSI device complexity) the mask is held just off the wafer surface and is visually aligned with the patterns in the wafer. The machine holding the wafer and mask for this operation can be adjusted to an accuracy of 12 mm. After alignment is achieved, the mask is pressed into contact with the wafer and then impinged with ultraviolet radiation to expose the photoresist. The space between the wafer and the mask is often evacuated to achieve intimate contact; atmospheric pressure squeezes the

Figure 2.11
First mask align. (From Ref. 2.)

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wafer and the mask together. In another variation, proximity printing, the mask is held slightly above the wafer during exposure.

Variations in the masking process arise from the need to print very small features with no defects in the pattern. If the mask were to be positioned very far from the surface, diffraction of the ultraviolet radiation passing through the mask would cause the smaller features to blur together. Thus hard contact would be preferred. However, the use of contact printing resulted in a number of yield and production problems, all due to the constant physical contact of the mask and the photoresist layer: damage to both mask and photoresist layer, poor dimensional control, and short mask life.

This brought about the projection alignment and exposure system, in which the mask and wafer never touch. Using projection alignment, the image of the mask is projected onto the wafer through an optical system. In this case mask life is virtually unlimited since there is no mask or photoresist damage. Projection alignment has become the standard production method for LSI and VLSI devices.

The concurrent increase in wafer size and decrease in device geometries presents a continuing problem in designing optics capable of forwarding an accurate image over the larger area. A replacement method for projection alignment currently being used for state-of-the-art ICs is called direct write.

The basic photoresist process (Table 2.2) may vary considerably from IC supplier to supplier, depending on the type of photoresist used, device features, and proprietary considerations. The photolithographic-photoresist processing steps are pictorially depicted in Fig. 2.12. The numbers in the following discussion refer to the respective steps shown in the figure. To form a doped pattern (which is contained on a mask) in the wafer by diffusion or implantation, openings must first be made in the oxide layer. The most basic masking step

Table 2.2 Basic Photoresist Process Steps

1. Substrate preparation: oxidation, CVD

2. Surface preparation: clean, dehydrate, prime

3. Application of resist: spin, spray, roll, dip

4. Soft bake: low-temperature cure to dry resist

5. Expose: align and expose to selectively polymerize the resist

6. Develop: dissolve the unpolymerized resist

7. Visual inspection (develop check): verify accurate image transfer to the photoresist

8. Hard bake: higher temperature cure to completely dry and polymerize the resist

9. Strip resist: organic, asher, or acid removal of resist

10. Etch: oxide

11. Visual inspection (final inspection): verify accurate image transfer to the layer

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Figure 2.12
Photolithographic-photoresist process.

involves the etching of a pattern into an oxide. An oxidized wafer (1) is first coated with photoresist, a light-sensitive polymeric material (2). Photoresist may be applied to the wafer by many different techniques, including dipping, brushing, spraying, or roller coating. The most popular, however, is the use of a spinner to apply the solution (photoresist dissolved in a solvent).

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In spinning, a wafer is held in place by vacuum on a wafer holder. Resist is then dispensed onto the center of the wafer, which starts to spin. The physics involved in the process force the resist toward the edges of the wafer, while providing a uniform coat of solution. The excess is spun off the wafer. As the liquid film (coat) spreads over the surface, the solvent evaporates, leaving the polymeric film. A mild treatment is given to dry out the film thoroughly and to enhance its adhesion to the silicon dioxide layer under it.

A combination of spin speed and the viscosity of the resist is responsible for the thickness of the resist following its application. Each resist has different specified high and low spin speeds for maximum uniformity. If the spin speed is too low, an excessive edge beam will form; if too high, a nonuniform layer will result because of uneven evaporation of the solvent in the resist. Although the process appears to be a simple one, it is nonetheless fraught with the possibility of contamination.

The most important property of the photoresist is that its solubility in certain solvents is greatly affected by exposure to ultraviolet radiation. For example, a negative photoresist cross-links and polymerizes wherever it is exposed. Thus exposure through a mask followed by development (washing in the selective solvent) results in the removal of the film wherever the mask was opaque. The photoresist pattern is further hardened after development by heating.

The photoresist-coated wafer is exposed to ultraviolet light (3) through the appropriate photomask pattern to expose areas of the resist. Two methods receiving attention as possible replacements for ultraviolet exposure in the future are X-ray and electron-beam (e-beam) exposure. The exposure renders the photoresist soluble in a development solution (4). Next, the wafer with its photoresist pattern is placed in a solution of hydrofluoric acid. The acid dissolves (etches) the oxide layer wherever it is unprotected, but it does not attack either the photoresist or the silicon wafer itself (5). After the acid has removed all the silicon dioxide from the exposed areas the wafer is rinsed and dried, and the photoresist pattern is removed by another chemical treatment (6). The etching operation serves a dual purpose: to remove portions of the top layer of the wafer through the holes, or openings, in the photoresist layer; and to transfer the pattern with those dimensions into the top layer of the wafer. The etch operation must not disturb the underlaying wafer surface. Etching down into the underlying layer can drastically change the physical dimensions as well as electrical and functional characteristics of the deviceeven to the point of catastrophic failure.

Other films are patterned similarly. For example, a warm solution of phosphoric acid selectively attacks aluminum and therefore can serve to pattern an aluminum film. Often an intermediate masking layer is needed when the photoresist cannot stand up to the attack of some particular etching solution. For

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example, polycrystalline silicon films are often etched in a particularly corrosive mixture containing nitric acid and hydrofluoric acid. In this case, a film of silicon dioxide is first grown on the polycrystalline silicon. The silicon dioxide is patterned in the standard fashion and the photoresist is removed. The pattern in the silicon dioxide can now serve as a mask for etching the silicon film under it, since the oxide is attacked only very slowly by the acid mixture.

The regions now free of oxide can be accessed by diffusion or implantation to add dopants to these areas.

Doping

Dopant elements may be added to the silicon at several points in the IC manufacturing process. Principal compounds used for doping silicon are listed in Table 2.3.

There are two techniques for selectively introducing dopants into the silicon crystal: duffusion and ion implantation.

Diffusion

Diffusion is a naturally occurring time- and temperature-dependent process used in IC production that introduces small amounts of impurities into the silicon substrate material and permits the impurity to spread into the substrate after the photomasking sequence has taken place (i.e., after the open areas are made in the oxide coating and the photoresist is removed).

If silicon is heated to a high temperature, say 1000°C, the impurity atoms

Table 2.3 Commonly Used Silicon Dopants

Element

Dopant type

Compound

Formula

Normal state

Antimony
n
Antimony trioxide
Sb₂O₃
Solid

Arsenic
n
Arsenic trioxide
As₂O₃
Solid

Arsine
AsH₃
Gas

Phosphorus
n
Phosphorus pentoxide
P₂O₅
Solid

Phosphorus oxychloride
POCl₃
Liquid

Phosphorus tribromide
PBr₃
Liquid

Phosphine
PH₃
Gas

Silicon pyrophosphate
SiP₂O₇
Solid

Boron
p
Boron trioxide
B₂O₃
Solid

Boron tribromide
BBr₃
Liquid

Diborane
B₂H₆
Gas

Boron trichloride
BCl₃
Gas

Boron nitride
BN
Solid

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begin to move slowly through the crystal. Certain key impurities (boron and phosphorus) move much more slowly through silicon dioxide than they do through silicon itself. This important fact enables one to employ thin oxide patterns as impurity masks. For example, a boat of wafers can be placed in a furnace at 1000°C in an atmosphere containing phosphorus. The phosphorus enters the silicon wherever it is unprotected, diffusing slowly into the bulk of the wafer. After enough impurity atoms have accumulated, the wafers are removed from the furnace, and solid-state diffusion effectively ceases. Of course, every time the wafer is reheated the impurities again begin to diffuse; hence all planned heat treatments must be considered in designing a process to achieve a specific depth of diffusion. The important variables controlling the depth to which impurities diffuse are time and temperature. For example, a layer of phosphorus 1 mm deep can be diffused in about an hour at 1100°C. Diffusion times range from a few seconds to many hours, depending on the desired depth of the diffused layer to be produced.

To achieve maximum control, most diffusions are performed in two steps. The predeposition, or first step, takes place at a furnace temperature selected to achieve the best control of the amount of impurity introduced. The temperature determines the solubility of the dopant in the silicon, just as the temperature of warm water determines the solubility of an impurity such as salt. After a comparatively short predeposition treatment the wafer is placed in a second furnace, usually at a higher temperature. This second heat treatment, the diffusion drive-in step, is selected to achieve the desired depth of diffusion.

Predeposition

To dope a semiconductor wafer, the appropriate atoms must first be made available on the surface of the wafer. Several methods are available for this purpose. An appropriate compound of the desired element in the form of a solution of controlled viscosity can be painted on the surface of the wafer, or spun on in the same manner in which photoresist is normally applied. For spin-on dopants, viscosity and spin rate are controlled to achieve the desired dopant film thickness. After evaporation of the solvent, the wafer is normally subjected to a selected high temperature to complete the predeposition diffusion. Excess dopant is then removed (usually by etching) prior to dopant drive-in.

Another method of predeposition employs a low-temperature chemical vapor deposition (CVD) process to deposit an oxide of the desired element on the wafer. In this case, the dopant is introduced as a gaseous compoundusually in the presence of nitrogen (or other inert gas) as a carrier or diluent, and generally with an excess of oxygen present to ensure deposition of the dopant as an oxide. Typically used gases are arsine, phosphine, diborane, and boron trichloride. In this operation, the oxygen concentration must be carefully controlled, since the presence of too much oxygen can lead to oxidation of the

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silicon surface of the wafer, in which case the silicon dioxide formed would block entry of the dopant.

Yet another method employs a doped layer of silicon dioxide in contact with the surface of the wafer. Inasmuch as the solid solubility of dopant is greater in silicon than in silicon dioxide, at elevated temperature the dopant will migrate from the SiO₂ into the silicon.

Following this predeposition operation, the concentration of dopant at the surface of the wafer will be that determined by the temperature and solid-solubility relationship, decreasing with depth beneath the surface. The depth of penetration and the amount of predeposition diffusion will be a function of both predeposition time and temperature. Dopant is usually introduced only at selected locations on the wafer surface by means of an appropriate mask (often silicon dioxide), which blocks or inhibits introduction of the dopant wherever it is present.

Diffusion Drive-In

Following dopant predeposition, a dopant wafer is subjected to a (different) elevated temperature, during which the dopant atoms further diffuse into the silicon crystal lattice. The rate at which they diffuse, or are driven into the wafer, can be controlled by the specific temperature employed. As diffusion progresses, the concentration of dopant, which remains greatest at the point of dopant introductionthe wafer surfacedecreases as the dopant atoms migrate further into the crystal lattice. The dopant atoms migrate further into the crystal lattice. The dopant profile for a specific purpose is thus achieved by control of the diffusion step. Dopant drive-in is usually performed in an oxidizing atmosphere to regrow a protective layer of silicon dioxide over the newly diffused area.

In the formation of p-n junctions by solid-state diffusion, the impurities diffuse laterally under the oxide mask about the same distance as the depth of the junction. The edge of the p-n junction is therefore protected by a layer of silicon dioxide. This is an important feature of the technique, because silicon dioxide is a nearly ideal insulator, and many electronic devices will not tolerate any leakage at the edge of the junction.

Ion Implantation

Until the early 1970s diffusion was the primary doping procedure used in IC fabrication. However, the increased use of MOS devices and smaller geometries pointed to several deficiencies or limiting features of the diffusion process:

1. Diffusion cannot provide the control required for low-concentration doping of the gate region of MOS devices.

2. Diffusion creates a higher concentration of the dopant at the wafer

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surface. What does this mean? Since current travels where the dopants are concentrated during device operation, any surface contamination severely affects an MOS device's operation.

3. The side diffusion (Fig. 2.13) inherent in the diffusion process limits how closely individual on-chip devices can be placed next to each other, creating larger chip size, slower speed, and lower yield circuits.

4. Each high-temperature heat treatment required for diffusion affects yield in two ways: (1) it causes some crystal damage in the wafer and (2) it diffuses unwanted contaminates into the wafer.

The ion implantation process was developed to overcome these deficiencies. Additionally, ion implantation (1) provides the ability to dope the wafer through a thin oxide layer and (2) allows the use of photoresist and other layers as the doping mask. The ion implantation process, which does not occur naturally, uses high-voltage ion bombardmant of selected impurities into controlled and selected regions of the wafer at room temperature to achieve the desired device operating characteristics without any intervening chemical reaction or diffusion. In this process, a compound of the desired element is ionized (stripped of one or more of its electrons) in the gaseous state. The desired ions are then separated from all other ions present by deflecting them through a magnetic fieldin much the same manner as a mass spectrometer uses to separate materials on the basis of their charge-to-mass ratio.

The separated ions are accelerated to a high energy by passing them through a potential difference of tens of thousands of volts and focused onto the surface of the wafer, which they penetrate to a depth that depends upon their mass and kinetic energy. They can thus be implanted at selected depths within the wafer. The wafer can be selectively masked against the ions either by a patterned oxide layer, as in conventional diffusion, or by a photoresist pattern. For example, phosphorus ions accelerated through a potential of 100,000 V will penetrate the photoresist to a depth of less than half a micrometer. Wherever they strike bare silicon they penetrate to an average depth of a tenth of a micrometer. Thus even a 1-mm layer of photoresist can serve as a mask for the selective implantation of phosphorus.

Figure 2.13
Side diffusion. (From Ref. 2.)

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As the accelerated ions plow their way into the silicon crystal they cause considerable damage to the crystal lattice. It is possible to heal most of the damage, however, by annealing the crystal at a moderate temperature. Little diffusion takes place at the annealing temperature, so that the ion implantation conditions can be chosen to obtain the desired distribution. For example, a very shallow, high concentration of dopant can be conveniently achieved by ion implantation. A more significant feature of the technique is accurately controlling the concentration of the dopant. The ions bombarding the crystal each carry a charge, and by measuring the total charge that accumulates the number of impurities can be precisely determined. Hence ion implantation is used whenever the doping level must be very accurately controlled. Often ion implantation simply replaces the predeposit step of a diffusion process. Ion implantation is also used to introduce impurities that are difficult to predeposit from a high-temperature vapor. For example, the use of arsenic as a shallow n-type dopant in MOS devices coincides with the availability of suitable ion implantation equipment.

A unique feature of ion implantation is its ability to introduce impurities through a thin oxide. This technique is particularly advantageous in adjusting the threshold voltage of MOS transistors. Either n-type or p-type dopants can be implanted through the gate oxide, resulting in either a decrease or an increase in the threshold voltage of the device. Thus by means of ion implantation it is possible to fabricate several different types of MOS transistors on the same wafer.

While ion implantation is more precise than photomasking, wafers can be processed only one at a time, rather than in large batches. Nonetheless, as device design moves increasingly toward smaller, shallower, and lower concentration dopings, better doping control, and more doped layers per process, ion implantation will become the dominant doping technique. Diffusion will still find a use in the doping of the less critical layers and will continue to be the preferred doping method for lower integration level circuits. Figure 2.14 shows a carousel of wafers awaiting ion implantation.

For all ICs the oxidation, photomasking, and diffusion or implantation sequence must be repeated several times to create the desired device structure.

Table 2.4 summarizes the salient features of the ion implantation process step just discussed, while Table 2.5 highlights the various ion implantation methods currently being used.

Depositing Layers on the Wafer Surface

The uppermost layers of integrated circuits are formed by depositing and patterning thin films on the surface of the wafer. These layers can be dielectrics, semiconductors, or conductors and are placed on the wafer by a variety of

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s

Figure 2.14
Technician prepares a carousel of gallium arsenide wafers for insertion into ion implantation
system. (Courtesy of Sanders, division of Lockheed Aircraft Corp.)

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Table 2.4 Ion Implanation

Advantages
Disadvantages

Good overall doping accuracy
Complex equipment required

Unaffected by surface films
Slow for heavy doses

Low temperature process
Wafer heating limits ion rate

Can mask patterns if desired
May need diffusion step

Can implant deep layers, including dielectrics
Possible bombardmant damage

Scanning may cause local doping variations

Can implant dopants through thin oxide layer; useful for adjusting threshold voltage of MOS transistors

Not a batch process

techniques. The use of these thin films is critical in providing the desired levels of performance in LSI and VLSI circuits. In fact, because the fabrication of LSI and VLSI circuits contains more thin film steps than diffusion steps, these circuits are essentially film technology driven. This represents a significant departure from the diffusion-driven fabrication of SSI and MSI circuits. Therefore thin-film technology is probably more critical to the overall yield and performance of these circuits than are the diffusion and oxidation steps.

Thin-film layers are used at places in the fabrication process where rapid low-temperature growth is essential. One such use is the selection of areas on the wafer that are to be oxidized. This is because silicon nitride oxidizes much more slowly than does silicon. Thus, a layer of silicon nitride can be vapor

Table 2.5 Ion Implantation Methods

Low/medium current

Serial, electrically scan ion beam across wafer

One wafer at a time, very slow for higher doses

Most useful for low doses

High current

Batch, wafers repeatedly moved under beam

Used for higher doses and/or throughout

High energy (very high voltage)

For deeper dopant penetration

Can produce buried dielectric layer

Focused ion beam

Implantation writing, eliminates lithography

Serial, very slow

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deposited, patterned, and used as a oxidation mask. The resulting surface is much flatter than would be the case if the thick oxide were grown everywhere and selectively removed. For n-channel MOS devices there is the additional advantage that an ion implantation step involving boron can be added just before the oxidation step, relying on the nitride pattern as a mask. This procedure results in a heavily doped p-type region located precisely under the oxide, which acts as an obstacle to the formation of channels from adjacent elements in the device.

This channel stopper diffusion step is necessary in high-performance n-channel MOS technology. Without selective oxidation a special masking step would have to be added. The spacing between elements would then necessarily be larger; thus selective oxidation leads to greater circuit density. Bipolar integrated circuits also benefit greatly from the use of selective oxidation. By replacing the conventional diffused isolation with oxide isolation the space taken up by one bipolar transistor is reduced by more than a factor of four.

Another use of thin film is for the planarization of the wafer surface. The starting material for an IC is essentially flat. However, the process of photolithographic graphic patterning, combined with the growth or deposition of both insulating and conducting films, results in an increasingly nonplanar structure as the wafer proceeds through all fabrication steps to the metallization stage. Typically, the gate oxide of a MOS transistor may be 90200Å thick, whereas the thickness of a neighboring field oxide may be as much as 3,0007,000 Å. This presents a severe problem in maintaining step coverage of metallization patterns, often resulting in a break in continuity at the step.

Step coverage refers to how well the interconnection material will adhere to the nearly vertical sides of the contact holes in the insulting oxide that reach down to the previous connecting layer. The more vertical the edges, the more likely the interconnection material will have a problem adhering to the inside and outside corners of the contact-hole step. Ideally, suppliers would like the height of that step to be zero, but this is not possible since an insulator is needed in most cases. This problem is especially serious in VLSI circuits, where the lateral dimensions are reduced but the metallization and oxide thicknesses are relatively unchanged. In these applications, techniques for flattening these steps, commonly referred to as planarization, greatly improve the process yield.

One solution is to thin the oxide without increasing the possibilities of punchthrough or pinholes that would cause catastrophic circuit failure by using nitride layers.

The local oxidation step itself results in considerable planarization, especially if the silicon is pre-etched so that the final oxide is fully recessed. Other approaches are aimed at removing the abrupt step when a cut is made in the oxide by taper control means using material such as PSG and polymide with such techniques as ion implantation damage and plasma etching.

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The list that follows summarizes the uses for thin films:

1. Thick field oxides for MOS ICs as well as for high-voltage devices. These are usually deposited over a base layer of thermally grown oxide to avoid a high trap density at the silicon surface.

2. Films where the previously grown layer has been removedfor example, deep diffusions of the type used for buried layers and isolation wells. These often utilize fresh masking and redoping at some point during the diffusionprocess.

3. Insulating layers over a metallization layer to form a base for the next layer of metal.

4. Planarization of wafer surface.

5. Passivation layers to protect the IC from physical abuse during mounting and packaging.

Traditionally, physical vapor deposition (PVD) techniques (i.e., evaporation and sputtering) have been used to deposit aluminium, alloys of aluminum, and a variety of silicides. The problems encountered with PVD, however, include the incorporation of oxygen and carbon in the deposited films, poor step coverage (which is marginal with evaporated films), and films with poor composition control, large volume shrinkage, and high stress. Although cosputtering from individual targets of a refractory metal and silicon improves composition control, other film properties are still difficult to control.

Chemical vapor deposition (CVD) can produce pure, reproducible thin films with good composition control. CVD films have lower stresses and, generally, have conformal step coverage.

The predominant methods for depositing thin films are

1. Oxidation (discussed earlier)

2. Epitaxy

3. Chemical vapor deposition

4. Evaporation

5. Sputtering

Each of the latter four are now discussed.

Use of Dielectric Layers*

When used in insulating applications in multilevel VLSI circuits, dielectric films must possess the following attributes:

*Portions of this section used with permission from Ref. 3.

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Must sustain relatively high dielectric breakdown fields

Should have a low dielectric constant, to minimize parasitic capacitance between conductors, and a high electrical resistivity

Must have a low loss factor for high-frequency applications

Must be free of pinholes and microcracks

Should have low compressive stress and excellent adhesion properties

Must allow hydrogen to diffuse through them during annealing to remove the interface states

Must be able to getter or to block alkali ions

For VLSI circuits all dielectric films must be readily depositable at temperatures compatible with other device structural materials and device performance requirements. Deposition must be done with excellent compositional control and good step coverage. In some cases the films must be flowed thermally for contour tapering or planarization. Finally, dielectric films must be patternable by precision lithography and selective etching.

Table 2.6 lists the major uses for dielectric films in the fabrication of VLSI circuits. Some of these will be discussed in greater detail.

Vertical insulation of conductor levels may be considered the most important application of deposited dielectrics in advanced multilevel VLSI devices. In addition to providing defect-free electrical insulation between layers, deposited dielectric films must ensure the continuity and uniformity of subsequently deposited conductor films that are frequently deposited over steep topography.

For high-temperature insulation, this is usually accomplished by fusion tapering or planarization of a glass, typically CVD phosphosilicate glass (PSG). The high temperature (10001100°C) required to soften PSG is undesirable and, for many ICs, intolerable. This is especially true in the fabrication of advanced devices with short channel lengths and shallow junctions where lateral and vertical diffusion of dopants must be minimized. Also, devices that must resist high levels of radiation require processing temperatures substantially lower than those acceptable for commercial IC production.

Lower process temperatures are also desirable to avoid the generation of crystallographic defects and wafer warpage, and to avoid the diffusion of contaminants.

Fusion tapering of silicate glasses solves the problems of metal coverage in most device applications. However, for high-density multilevel VLSI devices with the most stringent demands on precision lithography, creation of a nearly planar surface may offer certain advantages, such as improved metal definition, step coverage, and linewidth control.

The processing of interlevel insulation for aluminum and alloy conductors at the upper levels of device structures must be kept at temperatures not exceeding

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Table 2.6 Major Applications of Dielectric Materials in VLSI Technology

In device structures for

Isolation of circuit elements

Vertical insulation of high-temperature conductor levels in multilevel structures (polysilicon, silicides, refractory metals)

Vertical insulation of low-temperature conductor levels in multilevel structures (aluminum, aluminum alloys)

Over-metal top passivation

Contour leveling or planarization

Alkali ion and moisture barrier

Impurity gettering

Sacrificial material in lift-off patterning

High-permittivity gate dielectrics

Storage capacitor dielectrics

Redundant layers over grown silicon dioxide structures

Stress compensation

Alpha particle shielding

Antireflection films

For temporary layers and processing aids as

Masking structures against oxidation

Gettering layers for impurities

Solid-state diffusion sources

Diffusion and ion implant capping layers

Photolithographic masks for etching

Taper etching control layers

Sacrificial planarization media

Inorganic etch masks

X-ray-transparent membranes for X-ray masks

Components for multilayer resist structures

Source: Ref. 3.

500°C. Such temperature control is necessary to avoid excessive alloying with silicon in contact areas. In addition, the formation of hillocks, spikes, extrusions, and crystallites from aluminum layers must be minimized to prevent subsequent shorts by keeping the temperature at the lowest possible level, preferably below 300°C.

Polymides also have been demonstrated as an interlevel dielectric material, but are used only to a limited extent due to a number of technical problems. In small-geometry structures, a crevice or void may form in the nonflowed dielectric if the spaces between vertical (but not sloped) steps to be covered with metal approach two times the intermetal dielectric thickness, which leads to reliability

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problems created at the etch-back operation. This is a good example of how increased lateral scaling can become limited by thin-film deposition technology. Another example is the limitation of lithographic and dry etching techniques for resolving and delineating microfeatures.

Instead of planarization of the dielectric surface, one can planarize the contacts of vias by selective bias sputtering of tungsten or molybdenum to fill the openings.

Epitaxial Silicon Layer Deposition

Epitaxial growth is the deposition of a single-crystal film on the surface of a single-crystal substrate such that the crystal orientation of the film is the same as that of the substrate. In epitaxy, the atomic structure on the surface of the original wafer (substrate) is continued into the growing layer. Growth is carried on at high temperature in an atmosphere containing a silicon compound that is deposited on the hot wafer. To achieve a high-quality single-crystal layer on the wafer, many factors must be controlled. The wafer surface must be immaculately clean, the source must be very pure, the growth rate critically controlled, and the system free of leaks and contamination.

The epitaxial process starts with an extensive wafer cleaning process in which all particulate contaminates and surface stains or residues must be removed. This process usually includes mechanical scrubbing and chemical cleaning to remove both organic and inorganic contaminates.

Typically, to grow an epitaxial layer, hydrogen gas is bubbled through a volatile silicon compound such as silicon tetrachloride, causing it to vaporize. The mixture of vapor plus hydrogen is fed to a reaction chamber where the silicon wafer is heated to about 1200°C. The silicon tetrachloride dissociates, and silicon is deposited on the surface of the heated slice to form the epitaxial layer, which grows at about 1 mm (0.04 mil) per minute. Conductivity of the epitaxial layer is controlled and arranged to be either p-type or n-type by introducing the requisite amount of a suitable dopant vapor into the hydrogen stream with the silicon tetrachloride vapor. The surface of the epitaxial layer conforms closely to the surface of the wafer and does not require any additional preparation for subsequent processing.

Deposition temperature, film quality, system design, and process control are the general considerations used to select a silicon source. Deposition temperature influences the deposition (or film growth) rate, the formation of crystal defects, energy consumption, and autodoping (the most critical factor). Any dopant from either the wafer itself or a diffused region will out diffuse during epi growth. The out-diffused atoms will be recombined in the growing epi film, changing its resistivity.

The growth rate is critical in the maintenance of single-crystal growth and

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the prevention of pattern shift. If the growth rate is too fast, the epi on (111) wafers will grow at an angle to the wafer surface.

Epitaxial layers range in thickness form 2 to 20 mm. These are the layers in which the final devices will be formed. The original silicon acts as a host surface for the epitaxial layer and as a mechanical support.

The epitaxial technique has been used predominantely for forming the low-resistivity buried layer in bipolar ICs. Recently, however, the epitaxial technique has become increasingly important to MOS circuits that require a deposited silicon layer for

Reduced susceptibility to soft errors (alpha particle strikes)

Reduced susceptibility to latchup of CMOS parts

Use as the top-layer gate electrode (this gate oxide film, which is a polysilicon structure, is referred to as polysilicon)

Impact of the Epitaxial Process on IC Device Type*

Epitaxial-silicon process requirements vary from one IC type to another. For example, bipolar digital ICs require a different epitaxial layer than do bipolar linear ICs. Also, the increased use of epitaxial silicon in MOS applications has created more stringent process requirements than those that have been adequate for bipolar applications. Let's briefly address some of the salient considerations of the epitaxial process as related to IC type.

Bipolar Digital ICs

In a bipolar digital IC, effective epitaxial layer thickness is important. The effective thickness is determined by deposition temperature, deposition rate, and autodoping. All these factors must be controlled simultaneously during deposition.

Closely associated with the effective thickness of the epitaxial silicon layer is the requirement for a sharp doping transition from the buried layer to the epitaxial layer. The transition width, the characteristic change of doping concentration, determines several important device parameters. For example, any uncontrolled spread of dopants in the transition region reduces the effective epitaxial layer thickness and adversely affects device speed and breakdown voltage.

In bipolar applications, autodoping is the amount of buried layer dopant, typically arsenic, that is reincorporated in the growing epitaxial film. (Autodoping is not a problem with antimony-doped buried layers.) Arsenic atoms are released into the gas stream of the reactor by HCI etching used prior to deposition. Arsenic can also be released by sublimation.

*Portions of this section are reproduced with permission from Ref. 4.

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Arsenic autodoping, technically, is minimized at higher growth temperatures because the rate of incorporating these dopant atoms in silicon is lower. However, since out-diffusion of dopant atoms from the buried layer into the deposited epitaxial silicon layer and subsequent gradation of the transition region increase at higher temperatures, the process trade-offs favor lower temperatures for overall transition-width control.

Arsenic autodoping can be further reduced by operating an epitaxial reactor at reduced pressure (lower than atmospheric) during deposition. When epitaxial silicon is deposited at reduced pressure, high mainstream gas flow through the reactor and vapor-phase diffusion (away from the wafers) combine to reduce the reincorporation of dopant atoms, particularly slow-diffusing dopants like arsenic, into the growing silicon layer. Low-pressure operation allows minimal reincorporation of arsenic dopant atoms, even at low temperatures.

It is important to realize that the transition width is affected by the amount of autodoping, but not totally controlled by it. Control of transistion width and effective epitaxial thickness takes a combination of good crystal quality grown at low temperature to minimize out-diffusion, and controlled autodoping at reduced pressure.

An abrupt transition width can be achieved very effectively by emphasizing process control. Proper control of process sequence and gas flow, and the accurate ramping of temperature, can be used to enhance bipolar digital device characteristics.

Important process-control techniques include steps such as a low-temperature purge following the HCI-etch step and a cap, purge, and grow, technique in which a very thin, undoped epitaxial layer is grown to cap and seal buried layers.

Slip of the crystal planes (resulting from poor process control) and epitaxial silicon defects, in general, are also important process factors for bipolar digital applications. Because these devices can be as large as 50,000 mil2,, any slip will probably result in a defective device, usually as a collector-to-emitter short.

For similar reasons, defects such as stacking faults, spikes, and particles must also be controlled. A poor or dirty wafer surface can cause a film crystal defect called a stacking fault. The fault starts at the wafer surface and propagates to the film surface. Stacking faults are detected by etching the surface (Fig. 2.15).

The realization of 1-mm line widths requires very tight control of surface defects and contamination, which will take a whole new approach to epitaxial defect control. There is a tendency to think of epitaxial silicon as an early in the fabrication process step; thus defect control does not readily appear as important as in later process step such as metallization. But any kind of defect in epitaxy decreases yield dramatically when using state-of-the-art design rules.

Bipolar digital applications are further complicated by the need for

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Figure 2.15
Stacking fault. (From Ref. 2.)

controlling pattern integrityan apparent shift or distortion of the buried layer as it appears through the epitaxial silicon layer. The occurrence of these problems adversely affects lithography following epitaxial depositions because subsequent masks cannot be aligned to the pattern of buried layers, seriously affecting both device performance and packing density.

In the past, designers have compensated for such pattern changes, specifically shift, by offsetting subsequent mask levels. However, this uses more silicon area than is necessary for the transistor and is thus not desirable for VLSI designs.

Pattern shift occurs on (111)-oriented silicon wafers. The delineation of the buried layer shifts laterally, following the crystal lattice, during epitaxial growth. The apparent shift of the buried-layer pattern is a common result of epitaxial depositions that use chlorinated source gases at atmospheric pressure.

Pattern shift can be eliminated by the use of silane as a silicon source. Silane does not contain chlorine, and thus does not cause shift and distortion problems. In addition, silane epitaxial deposition, which typically occurs at 50°C to 100°C lower temperature than dichlorosilane or silicon tetrachloride, provides the advantages of less out-diffusion from substrates or from buried layers, giving sharper doping transitions for high-density circuits.

With chlorinated source gases, pattern shift can be controlled by adjusting growth temperature, growth rate, and growth pressure. For example, pattern-shift problems can be solved by using high deposition temperatures and lower growth rates. But high temperatures are contrary to the control of effective epitaxial layer thickness, as previously discussed. Deposition at reduced pressure also reduces the amount of pattern shift and accordingly allows for lower process temperatures (around 1080°C).

Pattern distortion can occur on both (111) and (100) silicon wafers and is caused by the same growth rate versus orientation phenomena that causes pattern shift. Whereas in pattern shift the underlying buried layer appears to change position, pattern distortion is a change in pattern shape. Again, this makes subsequent alignments difficult.

Distortion is more of a problem on (100) wafers, a fact that complicates the recent trend to (100) wafers for advanced bipolar digital applications. The (100) material has the advantage of less slip.

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The epitaxial deposition process criteria that control shift are similar but not the same for distortion. While reduced pressure deposition is effective for the control of distortion on (111) wafers, it is not as effective on (100) wafers. Generally, a temperature near 1100°C to 1150°C is necessary, along with reduced pressure to adequately control distortion.

Reduced pressure and temperature become tuning mechanisms for achieving pattern integrity; an engineer ends up trying to optimize several variablestemperature and pressure in conjunction with source gas and silicon crystal orientation. Such tuning is necessary to optimize shift and distortion, which are not necessarily controlled equally by the same set of variables, and to optimize epitaxial layer thickness.

Pattern shift of less than 0.1 mm and minimal distortion is required for VLSI. (Pattern integrity is not part of a supplier's guaranteed specifications.)

Figure 2.16 illustrates some of the functional areas of a bipolar digital IC that depend on the quality of epitaxial silicon deposition.

Bipolar Linear ICs

Bipolar linear applications for epitaxial layers have traditionally been less demanding than bipolar digital ones, but this is changing with more advanced

Figure 2.16
Typical bipolar digital IC cross section. (From Ref. 4.)

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designs. Now the process requirements for epitaxial layers in linear applications are approaching the same tolerances as required for bipolar digital ICs because of the demand for higher precision devices (see Fig. 2.17).

A bipolar linear IC is characterized by a thicker epitaxial layer than a bipolar digital IC. Because linear ICs operate at higher voltages, epitaxial layers must typically be 1020 mm thick. These thicker epitaxial layers affect pattern integrity. Total pattern change is a sum of shift and distortion per micrometer of growth. For example, at 1100°C and atmospheric pressure deposition, pattern distortion on (111) wafers can be as much as 2 mm per 1 mm of silicon growth.

In the past, relatively large line widths on linear IC patterns allowed for a corresponding degree of pattern distortion that could be compensated for in the mask set. Today's denser linear circuit designs do not.

The need for pattern integrity is also forced because more advanced linear designs incorporate dual buried layers. The second layer is added to provide an isolation up-diffusion that meets the down-diffusing isolation junction. (The net effect of the two diffusions places the isolation junction in a small area.) Because these two isolation diffusions must be aligned accurately, little, if any, pattern shift can be tolerated.

Figure 2.17
Typical bipolar linear IC cross section. (From Ref. 4.)

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Dual buried layer designs further complicate the epitaxial deposition process because they create boron autodoping. While arsenic can be controlled by reduced pressure, boron cannot; this complicates the process control of resistivity (as high as 10 W-cm) and transition width in linear applications.

MOS ICs

Present-day designs have been scaled to the point where CMOS circuits must now be fabricated in epitaxial silicon if they are to function properly. (An epitaxial layer is used for latch-up protection as well as for an alpha-particle barrier, for example.) This adds complexity to the fabrication sequence, increases costs, and adds new challenges for the epitaxial process step (see Fig. 2.18).

For example, a semiconductor supplier is eventually driven to epitaxial silicon to solve CMOS latch-up problems. (Latch-up, caused by the formation of a parasitic SCR, results in a circuit malfunction, especially at low supply voltages.) As CMOS devices get smaller the tendency for latch-up increases. Design changes, such as the addition of a guard ring, can cure latch-up problems, but this negates the advantages of scaling. Accordingly, a processing fix using epitaxial silicon becomes the best alternative. Twin-well structures are also

Figure 2.18
Typical MOS IC cross section. (From Ref. 4.)

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gaining increased use, to both reduce latch-up and to increase alpha-particle immunity, and thus increase reliability.

MOS epitaxial layers typically have high resistivity, in the range of 1050 W-cm. Resistivity uniformity is an important requirement for MOS applications as well. For example, threshold-voltage distribution is a direct function of resistivity of CMOS devices. Tighter control of this parameter will reduce the dependence on ion implantation for threshold control. Such process results require excellent temperature control. Threshold voltage control is also very much a function of reactor chamber purity and autodoping.

The MOS structure begins as a heavily doped wafer onto which a lightly doped epitaxial layer is deposited. As with bipolar applications, it is desirable to have a sharp doping transition between the substrate and epitaxial layer, which is also thin.

The difficulty is that the heavily doped substrate is often boron, a difficult atom to control as noted previously. When heated, boron is released from the front and back of the wafer. Part of this problem is solved by using a backseal to cut the source of boron from the back of the wafer. (While antimony-doped substrates, which are used for n/n⁺ structures, are easier to control than boron, p/p⁺ substrates with boron are generally a preferred process because of the use of state-of-the-art n-well technology.) While backsealing is necessary for some CMOS applications, it is a costly operation.

Two process alternatives for backsealing are in situ mass transport of silicon and the application of an oxide layer on the back of wafers prior to epitaxial processing.

In MOS applications where epitaxial silicon is used, active MOS devices are built totally within the epitaxial layer. Thus, the control of crystal quality is an important process factor. For MOS, epitaxial silicon layers must be as close as possible to the silicon of perfect, polished single crystal wafers. This requirement is the toughest to attain in terms of what is a tolerable allowance for slip, particles in the epitaxial layer, dislocations, and metallic contaminationall things that could potentially affect the MOS devices.

Wafer size, for example, is a key factor in achieving crystal quality. Maintaining control of slip is generally more difficult as wafer diameters increase. One cause of slip is the result of the release of built-up stresses that are secondary to radial temperature gradients across wafers. Larger wafers have more possibilities for radial temperature gradients. However, studies have shown that slip is also contributed to by the effects of oxygen content, backside damage, and internal gettering. When all these variables are properly controlled and the process optimized for temperature gradients, slip can be virtually eliminated.

Along with crystal quality, epitaxial wafer flatness must also be comparable to that of polished wafers to accommodate projection lithography.

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Chemical Vapor Deposition

Chemical vapor deposition (CVD) is a widely used method for deposition of high-quality films on the surface of the wafer, which function as dielectric layers or conductors (metallization). The primary advantages of CVD are the low deposition temperatures at which high-purity compounds can be synthesized, the great variety of materials that can be formed economically and relatively easily, and the adaptability of CVD processes to automated production of wafers. The increased density and complexity (small geometry size) of both MOS and bipolar ICs, the aforementioned advantages, and the increased use of nonsilicon substrates (IIIV compounds) has led to increased use of CVD.

In the CVD method a chemical containing atoms of the material to be deposited is introduced into the system reaction chamber. In the chamber, the chemical (in the gaseous state) reacts with another gas, freeing the desired material. The freed material (in atom or molecular form) then deposits on the substrate. The unwanted by-products of the chemical reaction leave the reaction chamber and are exhausted to the facility's fume scrubber system. This deposition process is governed by complex chemical relationships and requires a well-controlled contamination-free environment. There are essentially five techniques currently used for CVD film deposition. The key features of these are compared in Table 2.7.

In the past, CVD has been the source of high-purity insulating films of silicon nitride and silicon dioxide with excellent control of film conformality. The polycrystalline silicon film in the important silicon-gate MOS technology is usually laid down by means of chemical vapor deposition. Silane gas (SiH₄) decomposes when it is heated, releasing silicon and hydrogen. Accordingly, when the wafers are heated in a diluted atmosphere of silane, a uniform film of polycrystalline silicon slowly forms on the surface. In subsequent steps the film is doped, oxidized, and patterned.

Chemical vapor deposition is also being used for the deposition of conductive films, especially silicides. The basic advantages of CVD-deposited silicides include excellent control of film purity, including silicon and oxygen content, and good step coverage.

Chemical vapor deposition seems to create the strongest insulating layeran important reliability factor, since the formation of voids and cracks in the silicon dioxide can lead to shorts between conducting layers. However, CVD has been beset by some problems that are currently being addressed. Specifically, CVD has been a source of defects, which are aggravated as die sizes increase and multiple layer interconnections increase.

Evaporation

Metal films are used to interconnect the components formed in the wafer surface by means of a surface wiring technique. The wiring is accomplished by the

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Table 2.7 Comparison of CVD Film Deposition Techniques

Atmospheric pressure CVD (APCVD)
Low-pressure CVD (LPCVD)

Plasma-enhancement CVD (PECVD)

Photochemical CVD (PHCVD)

Laser-activated CVD (LCVD)

SiO₂, PSG, ASG, BSG

Requires continuous cleanup to minimize particles

Inadequate step coverage

High defect density

High-temperature process

SiO₂

Superior to APCVD

Better step coverage conformality than APCVD

Lower particle density than APCVD

Improved deposition thickness uniformity

Low deposition rates

Useful for VLSI circuits

High-temperature process

Produces high-quality
SiO₂, SiNxOy insulating films for low-temperature aluminum inter-metal insulators and for top-layer passivation

SiO₂, SiNxOy, Si₃N₄, Al₂O₃

Low-pressure reaction

Similar deposition rates to LPCVD

Very-low-temperature process

Lack of commercial large-scale reactor systems

Post deposition annealing may be necessary to reduce possible damage caused by vacuum UV radiation

Thermal energy not required for PHCVD reaction, but it improves film quality

SiO₂, Si₃N₄

High film deposition rates attained

Useful for depositing films on large areas or localized sites

Localized site deposition allows maskless generation of patterns

Materials key:SiO₂, silicon dioxide;Al₂O₃, aluminum oxide;PSG, phosphosilicate glass;BPSG, borophosphosilicate glass;BSG, borosilicate glass;Si₃N₄, silicon nitride;SiNxOy, silicon oxynitride.

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deposition of a thin (10,00015,000 Å) layer of metal on the wafer. This metal xlayer, after being patterned through a photomasking process, connects the devices as required by the circuit operation. The metal strips on the wafer surface are called stripes or interconnects. Generally, a wafer heating step called alloy follows deposition to insure good electrical contact between the metal and the wafer surface. Additionally, patterned conductive films function as the gate electrodes in MOS structures, and are used as electrodes in thin-film capacitors. Metals and alloys used for these purposes are aluminum and aluminium alloys, titanium/tungsten, doped polysilicon, refractory metals and their silicides, and gold.

Aluminum has been the traditional interconnect metal because it meets the requirements that a metal must have to be compatible with silicon technology:

It should have good current carrying density.

It should possess superior adhesion to SiO₂.

It should have the ability to be etched or plated to form high-resolution patterns (i.e., 0.1 mil with 0.1 mil spacing).

It should make good, low-ohmic contacts to both p-type and n-type silicon without destabilizing the silicon properties.

It should adhere well to the oxide and also to insulations deposited between layers of multilayer interconnection structures.

Resistivity should be low initially and should not increase as a result of subsequent processing or operation at high temperatures or power levels.

The metallization does not form intermetallic compounds that are resistive or weak either at the silicon-metal interface or with the bonded lead wires. It must be pure.

It does not degrade significantly in the atmosphere before hermetic packaging or after packaging in molded plastic.

It should resist current-induced electromigration and electrochemical corrosion.

It should resist abrasion.

Preferably, the metal or metals can be deposited by vacuum deposition.

The metallization should be metallurgically compatible with the external bonding system.

It should have controllable alloying characteristics.

It should have the capability of withstanding high temperatures without bond effect.

Evaporation, the simplest method for depositing a thin film, is commonly employed to lay down the metallic conducting layer in most integrated circuits. The metallic charge to be evaporated, usually aluminum, is placed in a crucible, and the wafers to be coated are placed above the crucible in a movable fixture called a planetary. During evaporation the wafers are rotated to ensure the maximum uniformity of the layer. The motion of the planetary also wobbles the

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wafers with respect to the source in order to obtain a continuous aluminum film over the steps and bumps on the surface created by the preceding photolithographic steps. After a glass bell jar is lowered over the planetary device and a high vacuum is established, the aluminum charge is heated by direct bombardment with high-energy electrons. The wafers may be heated to between 100°C and 300°C before evaporation in order to improve adhesion or to alter the metal films' properties. The result is a pure metal film, typically about a micrometer thick, being deposited on the wafer. Figure 2.19 shows wafers in a typical rotating planetary electron-beam vacuum system.

A typical aluminum metallization process is shown in Fig. 2.20.

Figure 2.19
Metallization dome. (From Ref. 1.)

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Figure 2.20
Metallization process: (a) wafer prepared for metallization; (b) aluminum evaporation;
(c) photoresist coating; (d) patterned photoresist; (e) etched metallization; (f) completed
process. (From Ref. 1.)

Aluminum, however, does have some shortcomings. One is electromigration, which is caused by the movement of aluminum atoms as a result of the current density in the metallization while the circuit is in operation. It is also enhanced by thermal gradients that arise in the lead from the heat generated by the flowing current. The metal thins and eventually separates completely, causing an opening in the circuit. Electromigration occurs over time and may not show up until a device has had many hours of operation. This problem can be overcome by using a metal layer design that supports the current being carried, employing wide overlap regions at contacts, a consistent film thickness (especially over steps), slope etching, or the addition of copper to the aluminum.

Electromigration becomes more of a worry as the level of integration increases. The higher number of components in the circuit creates more current flow and generates more heat.

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Another aluminum-related problem arises during the alloying step. The alloy is a heating process required to insure good ohmic contact. There is an upper limit to the temperature of this step. At 577°C a curious phenomenon occurs between the aluminum and the silicon. While each will not melt individually at this temperature, in combination they do. In metallurgy this is known as a eutectic point. Physically, a liquid alloy forms down into the wafer. In structures with deep diffusions the alloyed region may not pose a problem. However, in shallow structures (and this is the trend) the junction is shorted out by the alloy.

Still another major concern is over techniques to smooth successive layers of metal and dielectric, since the fine geometric features of VLSI circuits require a highly uniform surface. Metals create problems because their thermal coefficients of expansion differ from silicon. This leads to formation of hillocks, or small surface irregularities, as the metals cool.

To address these shortcomings, interconnection technology has advanced as dimensions have grown tighter. Progress in metallurgical understanding, coupled with process and equipment improvements, has led to significantly better performance and reliability.

At the gate level, polysilicon has been the dominant interconnection material, offering low threshold voltage, good step coverage, and uniform, fast, and economical deposition. Also, it is a high-temperature material, facilitating annealing after etching and implanting operations. At the device level, aluminum alloy films provide better control over electromigration and pitting than pure aluminum does, and better evaporative and sputtering deposition processes give control over the film's microstructures and improved step coverage.

However, as dimensions continue to decrease, the limits of both these technologies are being reached. Below 2 mm the resistance of polysilicon impedes high-speed performance. Below 1 mm, aluminum's control over electromigration is insufficient and its contact resistance is a problem. Thus new materials such as metal silicides and refractory metals must come into play. The advantage of silicon-based conductorsdespite their slower electrical responselies in their compatibility with the underlying silicon substrate. Silicides are a mixture of metal and silicon, while polysilicon can be doped with ions to produce conductors that approximate silicon in physical and chemical properties.

Additionally, multilevel vertical interconnect structures have been developed to solve the problem of interconnecting densely packed, shrinking geometry VLSI and ULSI devices. These include up to four (Fig. 1.2) and 5 (Fig. 2.21 and 2.22) metal layers and three or four polysilicon layers. However, all of these significantly complicate the IC fabrication process by adding more masking steps and affect finished device quality.

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Figure 2.21
Cross section illustration of a 5-layer metal layer, 4-level dielectric device structure.

Sputtering

Sputtering is another method of depositing both thin metal films and insulators onto the wafer. Sputtering is a physical process. Unlike evaporation, the material to be sputtered does not have to heated.

The sputtered process takes place in an evacuated chamber. Ionized argon atoms are introduced into the chamber, which contains the wafers and the target of the film material to be sputtered. The target is maintained at a negative potential relative to the positively charged argon atom. The positive ion accelerates toward the negative charge. When it strikes the target, some of the target material is broken loose. This loose material settles on everything in the chamber (i.e., the wafers), since the chamber is maintained at a vacuum.

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Figure 2.22
SEM section views illustrating 5-metal structure, including
precision contact vias.

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The cleanliness and water content of the argon gas are critical, as is the cleanliness of the vacuum chamber walls. The presence of any contaminate can change the film composition, introduce unwanted oxidation, and seriously affect the sputtering process.

Die Passivation

As a final process step before packaging, all suppliers coat the wafer with a passivation or glassivation film, which serves a fourfold purpose: It protects the surface of the wafer from contamination (moisture and deleterious impurities, such as alkali ions, and prevents aluminum corrosion of interconnect lines); it provides physical protection during chip separation and packaging operations; it provides mechanical strengthening; and it serves to smooth the vertical IC dimensions.

The dielectric film material intended for use as an overcoat must consequently have effective impurity barrier properties, be physically hard, be rugged, and have perfect film integrity. It should also possess slightly compressive intrinsic stress for maximal strength and be depositable at a relatively low temperature compatible with aluminum metallization.

This added step pays off in protection before and after packaging, in higher yields, and in better reliability. The glass is etched off the thin-film bonding pads and from between the circuits, where the wafer is cut into dice with scribing tools. The rest of the circuit is protected against contaminants (alkali ion migration) and scratching of the metallization during probe testing, bonding, and packaging.

The materials used to form this barrier surface layer include silicon nitride, aluminum oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma silicon nitride (SiNxHy), plasma silicon oxynitride (SiOxNyHz), and polyimide. The use of PSG films is increasing due to several desirable attributes: (1) It provides good thermal match to underlying semiconductor material, (2) it is more dense and void free than silica, (3) it provides tapered oxide cut (good metallization step coverage), (4) it is effective in immobilizing sodium ions in MOS technology, and (5) it enhances the stability of bipolar ICs. Phosphosilicate glass is also used in gallium arsenide technology as a mask for zinc and tin dopants. Often an SiO₂-PSG-SiO₂ sandwich is used instead of a single PSG layer, since this avoids direct contact between the aluminum and the PSG. Moreover, the upper layer of SiO₂ provides better adhesion to the photoresist that is used in cutting the contact holes in this composite layer.

Phosphosilicate glass films can be grown by the reaction of phosphine gas with oxygen at between 300°C and 500°C.

Chemically vapor-deposited PSG glass protection layers provide for

1. Scratch protection. Soft metal interconnections, typically aluminum, can be easily abraded and shorted to each other. If pure SiO₂ is used,

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it crazes because of tensile stress and mismatch of Si, Al, and SiO₂ phosphorus is usually added to prevent crazing.

2. Sodium contamination. MOS thresholds are adversely affected by sodium near critical Si/SiO₂ interfaces. Phosphorus helps better the sodium.

3. Corrosion resistance. Plastic packages permit water vapor to penetrate to the die resulting in corrosion of aluminum unless prevented by CVD PSG. The CVD PSG becomes more permeable in water with excessively high phosphorus concentration.

4. Loose particle protection. CVD PSG prevents foreign material from shorting a conductive element by isolating it.

Silicon nitride has many excellent qualities for a surface-passivating film. It has high resistivity (10¹⁶W-cm), high dielectric strength (~10⁷ V/cm), and excellent resistance against chemical and ambient attack; it is an excellent mask against sodium ion migration and it has superior stability against thermal and electrical stress. Silicon nitride (Si₃N₄) films are used in both silicon and gallium arsenide device technology. They require a higher deposition temperature (10001300°C) than films of silicon dioxide or doped silicon dioxide, so that their use is dictated in situations where they provide improved properties. However, they are extremely sensitive to even small amounts of water or oxygen. Often Si₃N₄ is used in conjunction with silicon dioxide to obtain a combination of characteristics that neither can provide alone. The first layer is silicon dioxide (SiO₂) for protection of the die surface, while the second layer, typically Si₃N₄ or oxynitride, prevents pinholes in the SiO₂ that would result in moisture penetration and eventual corrosion of the metal layer if not protected.

Unlike silicon dioxide, Si₃N₄ is an excellent barrier to alkali ion migration, so it is used extensively as a protective layer in MOS technology for this reason. But silicon nitride films are poorer than silicon dioxide in their ability to block electron movement through them. Consequently, they are often used in conjunction with silica films to provide a barrier to both electron and ion transport. Furthermore, film thickness is greatly restricted by the low diffusivity of nitrogen through it. Consequently, all silicon nitride films used in silicon and gallium arsenide technology are deposited today.

Since silicon nitride is about 100 times more resistant to thermal oxidation than silicon, it can be used as a mask in a number of silicon-based VLSI schemes which require selective oxidation of the semiconductor. Finally, it is used in radiation-hardened devices because of its superior radiation resistance over silicon dioxide.

Silicon nitride film can be deposited by rf sputtering, direct sputtering, or chemical vapor deposition. Currently, plasma silicon nitride (SiNxHy) film is favored for use as a passivation film because of its impurity barrier effectiveness

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and compressive stress. A potential disadvantage of these films is their hydrogen content. Hydrogen is undesirable because it can increase MOS device instability and render films thermally unstable due to its release upon heating much above the temperature of deposition. Furthermore, silicon nitride and polyimide have been used as passivation coatings over the PSG layer.

Normally residual stress (built in during fabrication) in metal lines is not a problem; it anneals itself out during use (dislocations move and readjust). However, with a glass layer on top, the stresses don't necessarily anneal out, because of interface (composite material) issuesa complex situation. The stresses build up, eventually leading to metal rupture. Studies conducted at Jet Propulsion Laboratory regarding metal interconnect and stress voiding have shown that the metal microstructure has a first-order effect on stress along the line length; the passivation type has a first-order effect on stress through the line thickness and stress distribution correlates with metal voiding susceptibility and rate. Furthermore, as regards the built-in mechanical stress during wafer fabrication, device geometry impacts reliability. Devices with smaller widths have reduced lifetimes and high stress levels. Variations in device hot carrier lifetimes of over two orders of magnitude have been observed within a given wafer and have been correlated with physical stress.

Typical IC Processes

A given process integrates many combinations of the various operational steps previously presented optimized for a specific functional circuit implementation. In this section the reader is presented with several typical processes to illustrate how these steps are combined in sequence to produce the desired integrated circuit. It should be noted that there are many variations of each of these processes, each optimized for an IC supplier's specific performance and/or yield factors. Just enough detail is provided to give the reader a flavor of what is involved. The two major technologies in use today are CMOS (~79%) and bipolar analog (~10%) (see Fig. 1.6). As such, both are used as illustrative examples showing the detailed wafer fabrication process steps.

Bipolar Process

Figure 2.23 illustrates the major processing steps for fabricating an n-p-n transistor and a diffused resistor in a typical bipolar IC. The following steps refer to the diagrams in Fig. 2.23.

a. A starting wafer about 10 mils (0.010 in.) thick is sliced from a single crystal ingot of p-type silicon.

b. An oxide layer is grown to protect the surface of the silicon during

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Figure 2.23
Typical bipolar IC fabrication sequence. (From Ref. 1.)

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Figure 2.23
(Continued)

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the ensuing operations, and the entire surface is covered with a layer of photoresist.

c. The mask containing the buried layer pattern is placed on top, and the photoresist is exposed to ultraviolet light. This buried layer will subsequently form a low-resistance collector-emitter conductance path for the bipolar transistor. The portion of the photoresist exposed to the light polymerizes, and the rest is dissolved.

d. The oxide that is not protected by the polymerized photoresist is etched away; n⁺-dopant is diffused through the windows into the p-substrate forming the buried layer, and the polymerized photoresist and oxide are washed away.

e. A thin layer of n-type silicon is grown on the silicon in an epitaxial reactor, and a new oxide layer is grownoxide masking is repeated.

f. The entire top surface is again covered with a layer of photoresist.

g. The p-type dopant is diffused through the windows. The diffused regions connect with the underlying p region (the substrate) and form isolation pockets in the epitaxial layer. The edge of the junction is under the oxide.

h. The p-type dopant is diffused into the unprotected regions, and the wafer is covered with another oxide layer.

i. Again the wafer is covered with photoresist. The resist is exposed through the mask, which outlines all shallow n regions, and the oxide is etched away in the unpolymerized areas.

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j. A shallow layer of high n-type dopant concentration is diffused into the unprotected areas.

k. Another oxide layer is grown.

l. The wafer is covered with photoresist for the fifth time. The resist is exposed through a mask in the areas where contact to the devices must be made, and the unprotected oxide is removed.

m. The entire wafer is covered with a thin metal film.

n. With one more series of photolithographic steps, the portions of the metal layer not needed for interconnection are removed.

Typical CMOS Process

Figure 2.24 shows the wafer fabrication process flow for a twin-well two-metal silicon gate process. The detailed process steps are shown in Fig. 2.25.

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Figure 2.24
Twin-well silicon-gate CMOS manufacturing sequence. (Courtesy of ICE Corp., STATUS 1994.)

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Figure 2.24
(Continued)

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Figure 2.25
Details of twin-well two-metal silicon-gate CMOS process sequence.
(Courtesy of ICE Corp., STATUS 1994.)

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Figure 2.25
(Continued)

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Figure 2.25
(Continued)

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Figure 2.25
(Continued)

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Figure 2.25
(Continued)

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Figure 2.25
(Continued)

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Figure 2.25
(continued)

References

1. E. R. Hnatek, A User's Handbook of Integrated Circuits, John Wiley and Sons, New York, 1973.

2. P. Van Zant, Microchip Fabrication, Semiconductor Services, 1984.

3. W. Kern, Part-2b-Deposited Dielectrics for VLSI, Semiconductor Int., July 1985, pp. 122129.

4. P. S. Burggraaf, The Forces Behind Epitaxial Silicon Trends, Semiconductor Int., October 1983, pp. 4551.

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3
Back-End Fabrication Operations

Once the wafer fabrication sequence is completed the wafer is still not ready to use. Several manufacturing operations remain to be performed: wafer probe test, scribe and break, assembly process (packaging), and electrical test. These are termed back-end operations, since they occur subsequent to wafer fabrication.

Wafer Probe Test

Once the wafer has metal contact regions, the devices can be electrically tested. While a full range of electrical tests cannot be made at this point in the manufacturing process, each die on the wafer is probed to determine whether it functions correctly. Testing at this stage is a valuable tool.

Wafer probing usually entails a very short test that guarantees the functionality of the IC and checks for gross DC (direct current) parametric failures. The elimination of parts with defects is very cost effective because these parts are not assembled in their packages, thus minimizing scrap and material costs.

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The roles of parametric testing are varied, ranging from quality control to process control to design verification to device characterization. (Only the first two are applicable to wafer probe test.) Of the hundreds of different device parameters that could be measured, a relative few are usually sufficient for this purpose. Measured DC parameters typically include threshold voltages, breakdown voltages, contact sheet resistance, leakage currents, saturation currents, and transistor beta. Alternating current (AC) measurements are basically measurements of capacitance.

Very little test time is spent on guaranteeing specification limits, because the die's performance may change when packaged. For example, leakage current measurements at wafer probe are significantly affected by daylight or building lighting systems (photons) such that this parameter must be relaxed at wafer probe. Conductance limits must also be relaxed due to the contact resistance effects of the probes. However, multichip modules (MCMs) have driven the need for fully tested (known good) dice such that many IC manufacturers perform full DC and AC parametric and functional tests at wafer probe over the operating temperature range.

Also during wafer probe testing measurements are made on special test structures that are fabricated on the wafer during normal processing. Test structures are discrete elements or combinations of discrete elements, such as transistors, resistors, and capacitors that are specially designed and fabricated to facilitate measurements of AC and DC parameters. Usually there are anywhere from 3 to 16 test sites on a given wafer, with several different types of structures within each site. Larger numbers of test sites are often used during initial process development for a new device, with fewer needed for monitoring an established process. Chapter 4 presents a more in-depth discussion on test structures and process monitors.

Computer-controlled automatic test equipment (ATE), which has an array of needlelike probes that descend on the contact pads to make electrical connections to each device, quickly tests each circuit and then steps to the next one. Defective devices are automatically marked with an ink dot and are discarded after the wafer is separated into individual dice in the next manufacturing stepscribe and break. The automatic test equipment also keeps accurate statistics on the number of good circuits per wafer, their location, and the relative incidence of various types of failure. This information is helpful in developing yield improvement programs.

Two areas of criticality in electrically testing the finished ICs both at wafer probe test and at final electrical test are the accuracy of the software for running the ATE and the calibration of the ATE. Both of these factors impact the ability to separate good (acceptable) devices from unacceptable devices in accordance with the established guardband or specification test limits. Inaccuracies or errors in the ATE software as well as the ATE being out of calibration could cause

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acceptable devices to be rejected (Type I errors) or conversely could cause unacceptable devices to be accepted (Type II errors). Thus, both software accuracy and ATE calibration are critical in uncovering manufacturing defects and thus determining finished device quality. As such, software verification is necessary to ensure the viability of the software to properly measure the desired electrical parameters. Chapter 8 discusses the issue of software verification. A detailed discussion of measuring equipment/instrumentation (ATE) calibration can be found in Ref. 13. Additionally, regularly scheduled preventative maintenance and system calibration in conjunction with running system diagnostic routines for each workshift will prevent the possibility of electrically testing ICs on an ATE system that has drifted out of specification.

Lastly, a fault in the inking machine could cause either good dice to be inked as rejects or reject dice to be passed as acceptable dice. Thus, the inking machine should be checked periodically to verify that it is operating according to its specifications.

New Wafer Probe Methods

With the shrinking of minimum feature sizes, traditional methods of detecting defects and identifying their causes, such as optical inspection and mechanical probing of dice, are no longer effective or valid. Instead, integrated circuit suppliers are looking at alternative and more accurate methods of defect detection.

In the future the role of the wafer probe test in the manufacturing sequence will change significantly. The implementation of wafer probe will change from contact probing to contactless probing (e-beam, photon excitation, or laser) to eliminate contact resistance effects on high input/output (I/O) count devices, thus allowing AC performance to be measured. Wafer probe testing has become more comprehensive and complete, taking over the role for verifying conformance to specification limits from final electrical test. This represents a shift in emphasis from final test to wafer probe test.

Electron-Beam Probing

Electron-beam probing, a combination of the scanning electron microscope and electronics to measure secondary electrons, is one means of probing small geometry devices.

Traditional methods of mechanically probing ICs for faulty interconnects are suitable for larger geometry devices, but cannot be used successfully with parts below about 1 mm. Mechanical probes cannot be used with VLSI devices for a number of reasons: They are too large to contact a single interconnection, they are too difficult to position, and they can damage the devices both physically and electrically through the electrical capacitance they impart to the device under test (DUT).

The e-beam probing systems, however, can test probe lines of less than 1

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mm nondestructively without contributing to the capacitance of the DUT. Unique to e-beam probing is the ability to produce a number of different voltage contrast images, and to test through a passivation layer. Additionally, e-beam probing is fast and offers high spatial resolution. With mechanical probing equipment, spatial resolution can present difficulties. Trying to put a prober wire on a line that cannot even be seen in the optical microscope poses a significant problem.

An important application of e-beam testing equipment is voltage waveform measurement of nodes within the IC. Time resolution of 200 ps and voltages of 1 mV are currently achievable.

Basically, an e-beam probe system is a dynamic voltage contrast system in which voltage information is displayed either as a micrograph in the stroboscopic mode or as a waveform in the sampling mode. The qualitative voltage contrast appears superimposed to the normal topography and material contrasts. In operation, when an electron beam strikes an interconnection, some of the primary electrons, backscatter electrons, are bounced back from the point of impact with about the same energy they had on first impact.

The other primary electrons release local electrons at the interconnection. These leave the device under test as secondary electrons, and have less energy than the backscatter electrons (Fig. 3.1). The backscatter electrons are not part

Figure 3.1
Electron activity when an e-beam strikes an interconnection.

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of the measurement criteria; it is the secondary electrons that yield the measurement, and these are collected by a detector.

An electrical field is created when a voltage is applied to an interconnection. While this strongly affects the secondary electrons if that line is probed, it has little influence on the energetic backscatter electrons.

If a positive voltage is applied, the slowest of these secondary electrons are turned back in the direction of the interconnection, which makes the number of secondary electrons collected by the detector considerably smaller than in the no-voltage state or when a negative bias is applied (Fig. 3.2). This voltage change also causes a shift in the energy of all secondary electrons by a specific value. A spectrometer can measure this voltage change.

Quantitative voltage measurements are provided by the secondary electron analyzer in the system, which often permits the evaluation of voltages as low as 1 mV. In the quantitative voltage measurement mode, the e-beam prober yields information on rise and fall times, as well as amplitudes and delays on internal IC signals.

The voltage measurement mode is most widely used, and it is the mode where the e-beam is meant to have as little influence on the device operation as possible.

Figure 3.2
When voltage is applied, creating an electrical field, the
slow secondary electrons are turned back toward the
interconnection.

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In the current impressing mode, the e-beam is given an active role in testing. In this mode, the e-beam is used as a micrometer-scaled current source to take advantage of absorbed currents flowing into the irradiated area. It may also be used as a source of carrier multiplication in thin insulating films or in p-n junctions.

The block diagram of commercially available e-beam tester linked with a computer-aided design (CAD) system for diagnostic testing of VLSI circuits is shown in Fig. 3.3. This tester automatically generates a logic-state map of the device under test (DUT) to check the internal behavior of the individual on-chip circuits.

For every metal pattern on the chip's surface, a logic value is measured for comparison with the expected value derived from logic simulation. The electron-beam tester creates a logic-state map of the device under test that has all the top surface metal wire patterns displayed in different colors according to expected logical values. To prepare the logic-state map, each interconnection pattern at the mask-pattern level is linked to a circuit node on the logic-circuit diagram. A set of connecting lines linked to the same node is called a net. By using assigned net numbers, the tester correlates actual metal-wire patterns on a chip to nodes on the circuit diagram. The tester assigns metal-wire patterns to simulated results.

With the system of Fig. 3.3, the DUT is mounted on its XY fixture in the electron-beam vacuum chamber with test patterns applied through an large-scale integrated (LSI) driver stage. The electron-beam tester, with a

Figure 3.3
An electron-beam tester analyzes the internal operations of individual circuits in a VLSI chip.

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scanning area of 500 mm², develops an image from the top surface wires of the DUT that are at low voltage or logical zero levels while under test. The voltage contrast image signals are digitized and transferred to the host computer.

But when electron-beam testing takes place without a conventional LSI tester, inspection takes too long, which also is a problem in laser probing. To test an LSI chip, logic-state maps are prepared over the entire chip surface for a large number of test patterns and then matched against the logic states predicted from the CAD data base. A 10-mm² chip, for example, involves 400 observation areas. To shorten test time, an operator must localize the chip defect with a conventional LSI tester before final diagnosis by the electron-beam tester.

Currently, e-beam probing is well established as a vital tool to the IC designer working with submicrometer technologies. The e-beam prober is mandatory for the designer to test the complete design in silicon and it is a useful tool in failure analysis work. As shown, e-beam systems are unlikely to find their way onto the production lineother than as an important adjunct to automatic test equipment.

Laser Probing

Logic-mode and image-mode analysis are two laser probing techniques for testing VLSI parts without contact. With logic-mode analysis, the logic state at the point of laser irradiation is checked; image-mode analysis provides a contrast image of photo-induced current produced when a laser scans the surface of a VLSI circuit in two dimensions. Both probing techniques can be performed in a normal environment, which is a distinct advantage over electron-beam probing techniques, which must take place in a vacuum.

One commercially available laser probing system combines both techniques to locate and diagnose faults in VLSI parts. The source, a helium-neon laser, has a wavelength of 632.8 nm. An acoustic-optic modulator controls its output power and pulse level. The power of the object lens on the microscope determines the diameter of the laser beam focused on the surface of the DUT. Using an XY mirror and mirror-drive circuitry, the operator can focus the laser beam precisely at any point on the surface of the DUT.

The status and performance of the DUT are analyzed by laser irradiation producing photo-induced current, which is detected and amplified in the photo-induced current detector stage and then stored in memory. Power and test stimuli are applied to the DUT through a logic tester, which also monitors output signal status. During logic-mode analysis, data stored in the photo-induced current memory give a display of the logic state at the point of laser irradiation. In the image-analysis mode, a contrast image of the area scanned by the laser beam comes from data stored in the photo-induced current memory.

During fault diagnosis using image-mode analysis, contrast in the photo-

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induced current image of a good device is compared with that of a faulty device under test. Because of the large number of images obtained from the extensive test pattern sequence applied, it is difficult to judge which section of the device under test is defective.

To pinpoint the malfunction, the system displays the photo-induced current image of a good device in green on the color monitor; the photo-induced current image of the DUT appears in red. The areas that are functionally identical and thus good will appear yellow when the images are superimposed. The section that is malfunctioning will appear in red or green, depending on the image-contrast level.

For logic-mode analysis, the system probes nodes that seem to be propagating signal errors. It compares the output data with the simulation data from the device design data base. With the logic-mode probing technique and special software created for this on-line system, the operator can detect gate propagation and gate faults automatically.

The drawback to this system is the lengthy time to diagnose faults during image-mode analysis. About 8 hr is needed to diagnose a fault in a 10-mm² chip using a 100-step test pattern and 10X objective lens. The system's 10X lens has a visual field of only 1.8 mm, requiring subdivision of a large VLSI chip's surface into several areas for multiple laser scans. To cut diagnostic time, optical lenses with wider fields are being developed.

Electro-Optic Sampling

In another development, an electro-optic sampling technique using a continuous wave (CW) laser and backside reflection geometry approach has been used to measure internal waveforms of high-frequency ICs, specifically GaAs ICs. The details of this approach may be found in Ref. 3.

Scribe and Break

The wafer must now be separated into individual IC chips (dice); originally this was accomplished by scribing and breaking, a process very similar to glass cutting. Lines are scribed across the slice (wafer) between the circuits in each direction using a fine diamond point. Then the slice is placed on a rubber pad, stress is applied by running a roller over it, and the slice breaks up into the individual chips. Sawing the wafer with a diamond saw (the most widely used method) and laser scribing are also used to separate the dice and are discussed in Chapter 15. The chips are sorted by visual inspection to pick out and reject those that were marked with the ink spot during the probe test. Each chip or die is a complete IC. However, not all the circuits will work. Defects in a wafer cannot be avoided, and a single defect can ruin an entire circuit. For example, a scratch only a few micrometers long can break an electrical connection. It is

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impossible both physically and economically to repair the defective circuits; they are simply discarded. As one might expect, the larger the die, the greater the chance for a defect to appear and render the circuit inoperative. The yield (the number of good circuits per wafer) decreases with the size of the die, both because there are fewer places on a wafer for larger dice and because larger circuits are most likely to incorporate a defect.

At first it might appear most economical to build very simple, and therefore very small, circuits because more of them would likely be good and small circuits are inexpensive to make. However, there is more involved than just the size of the die. The costs of testing, packaging, and assembling the completed circuits into an electronic system must be taken into account. Once the circuits are separated by sawing the wafer into dice, each die must be handled individually. (We no longer have a batch process.) From that point on, the cost of any process step such as packaging or testing is not shared by hundreds or thousands of circuits. For very-large-scale and high-I/O-count application-specific integrated circuits (ASICs), packaging and testing costs often dominate the other production costs. Thus, it is extremely important to isolate defective circuits from good ones as soon as possible in the assembly and test sequence to minimize the cost.

Assembling and Packaging the IC

The completed circuit must undergo one last fabrication operation: packaging. It must be placed in some kind of protective housing and have connections with the outside world, because the IC with its components, e.g., the aluminum interconnects, will not tolerate either physical or chemical contaminants (abuses). There are many types of packages, but all have in common the fact that they are much larger and stronger than the silicon die themselves.

The ultimate requirements of the final system greatly influence the circuit package used. The package determines the system's form factor, its component density, and its ability to perform reliably in a particular operating environment and temperature range. A package has four basic functions:

1. To provide a means for connecting the die to the outside world electrically so that the IC can be used.

2. To protect the sensitive IC from any hostile environment that could, in time, degrade circuit performance.

3. To provide adequate mechanical protection.

4. To act as a path for heat resulting from power dissipation in the IC; the package must dissipate that heat to the surrounding air or conduct it to a heat sink.

The type of package selected for a particular application is generally evaluated on the basis of several factors: environmental capability, application

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usage (including electrical performance and thermal characteristics), manufacturability [including printed circuit board (PCB) assembly], reliability, and durability, comparative interconnecting cost, comparative package cost, component density per unit volume, and comparative system size.

Generally, IC package types are classified as either hermetic or nonhermetic (plastic or molded). At present, the majority of packages in current use (>90%) are plastic and will continue to be plastic because of their economy, simplicity of assembly, and ruggedness. Hermetic (ceramic or metal) packages are widely used in military equipment and in applications where the external environment is extremely harsh or corrosive. They are very expensive and their use is declining, although some VLSICs and ASICs absolutely need the benefits provided by the ceramic material. Nonetheless, hermetic packages represent a very small percentage of the IC packages produced.

The quality of a hermetic seal is expressed in terms of a maximum allowable leakage rate, which necessarily applies only to package types possessing an internal cavity. Noncavity packages cannot leak, but if not properly constructed, they can allow contaminants to reach the silicon chip.

Packages are also classified by the materials that are used in their manufacture (ceramic, metal, glass, and plastic); by the package configuration itselfTO-5 style, flat-pack, dual-in-line package (DIP), small-outline IC (SOIC), pin grid array (PGA), and leadless chip carrier (LCC), for example; and by the PCB interconnection methodthrough-hole or surface-mount technology (SMT). The TO style, DIP, and PGA packages are through-hole mountable while the flatpack, SOIC, and LCC are surface mountable.

Packaging Materials

Packaging materials are chosen for chemical inertness and compatibility with silicon assembly temperatures. Matched coefficients of thermal expansion, tensile strengths, and modulus of elasticity are also desirable. The four main package materials are metal, glass, ceramic, and plastic.

Most metal packages use ATM F-15 alloy, commonly known as Kovar, as the structural material for sealing glass to metal. Kovar has a temperature coefficient of expansion close enough to that of glass to prevent the glass-to-metal seal from cracking over a wide range of temperatures. Oxidized Kovar forms a good bond between itself and the glass. However, the metal is easily oxidized, which requires that the external leads of the IC package are plated, usually with gold. The gold prevents oxides from forming and interfering with soldering and welding.

Kovar's primary disadvantages are low electrical and thermal conductivity (for a metal). Clad or laminated high-conductivity materials with glass-compatible expansion coefficients are sometimes used instead of Kovar. Cladding also allows precious metal to be placed only at the chip attachment area,

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eliminating the usual method of plating the entire lead frame. Typically, all the package leads are mechanically connected by a frame and cut apart after the packaging is completed. Lead frames for plastic packages are selectively plated and then spot gold-plated in the desired chip-bonding area, improving the process.

Although glass-to-metal packages provide a good seal and, by virtue of their simplicity, reduce fabrication costs by more than 50%, their thermal conductivity and heat dissipation are poor. This has limited the glass-to-metal package to low-power, less heat-sensitive devices. Alternative designs include ceramic bases for better heat conduction and an all-glass ring for lead sealing. In addition, glass plates serve as substrates for many hybrid film circuits. The flatness and uniformity specifications are satisfied at surprisingly low cost. Special glass and plastic materials are often used to coat, protect, and seal completed IC chips.

Ceramic is a good material for hermetic packages. Its thermal conductivity is high, and its expansion coefficient is compatible with glass. Typical ceramic materials are alumina (8599% Al₂O₃) and beryllia, which has a much higher heat conductivity than alumina, and is favored for high-power circuits.

But Kovar and ceramic packages are very expensive compared with plastic. Thus plastic is the material of choice for IC packages. Plastic or molded packages are made by assembling and interconnecting the chip on a substrate or lead frame and molding the entire structure (except for lead ends) in plastic to form the package body. Epoxy is the most widely used plastic material. Molded packages are not considered hermetic because the resin-lead interface does not form a true seal. In the past, the primary concerns with using plastic packages were moisture absorption leading to a corrosion process, different thermal coefficients of expansion for all the materials involved (lead frame, silicon die, gold ball bonding wire, die attach material, and plastic molding compound), package cracking, delamination, aluminum metal deformation, and wire bond failure [2]. The issue of moisture is extremely important since all plastic materials absorb moisture. However, moisture/water by itself is not corrosiveit takes an ion such as chlorine, bromine, or phosphorus to provide the corrosion mechanism. That is why IC suppliers strive for low pinhole count; low phosphorus; Si₃N₄ passivation; high-purity, low-chlorine-content plastic (<5 ppm Cl); and low-bromine-content mold release agents. Some suppliers also use a die coat in addition to the passivation layer to protect the die and the wire bonds.

Since the 1970s IC manufacturers have worked to improve the materials, materials match, and manufacturing processes used to manufacture plastic molded packages. The plastic packaging process has shown significant improvement in reliability such that plastic packages are now on a par with the ceramic packages for most applications. Some of the relevant improvements include:

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Careful selection of materials for die attach and molding provide improved package integrity.

Improvements in plastic materials, including

Low ionic impurities

Low moisture adsorption

Better adhesion properties

Matching of thermal coefficients to die/lead frame

High glass transition temperature

Higher thermal conductivity

Low coefficient of thermal expansion

Improved passivation layer, including

Better adhesion to die

Less pinholes or cracks

Use of low ionic impurity (phosphorus) compounds such as silicon nitrides

Lower water-vapor adsorption

Thermal properties better matched to substrate

Die planarization using spun-on glass techniques

Matched TCEs (thermal coefficients of expansion) of all materials used.

Use of die overcoat.

Cleaner die assembly processreduced chlorine and bromine content.

Improved molding processes resulting in better adherence to lead materials.

Lead-lock frames minimizing separation of the plastic and the lead frame.

Improved lead frame materials. Etched copper lead frames have higher thermal and electrical conductivity than Alloy 42. However, mold tools must be carefully designed for copper lead frames; they create greater variations in package flatness with changes in die/pad size then Alloy 42 for thin package applications, and some molding materials don't adhere as well to copper as they do to Alloy 42. Thus, the lead frame must be matched with the application.

Package Types

Ten years ago, nearly all semiconductors were packaged in dual-in-line packages (DIPs) and connected with traditional wire bonding. Surface-mount packages and the infrastructure necessary to assemble and mount them were then developed, but later than the industry predicted. Even though some of these packages have been available for 10 years, surface-mount usage has been increasing only since the late 1980s.

Today, two basic package mounting techniques exist: through-hole (DIPs and single-in-line packages, called SIPs), and surface-mount [small outlines (SOs), thin small outlines (TSOPs), quad flat packs (QFPs), and ball grid arrays

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(BGAs)]. These packages are available in plastic, ceramic, or metal alloy. Methods for interconnecting packages into a system include tape-automated bonding (TAB), flip chip, and wire bondingthe most widely used method.

Two other types of packaging, multichip modules (MCMs) and chip on board (COB), also are available. An MCM interconnects different multiple bare dice inside a package or module. COB refers to the assembly term for attaching bare dice to a substrate. COB can be used in an MCM, and an MCM can be assembled into a surface-mount package like a BGA.

This section presents the popular through-hole and surface-mount packages. Chapter 7 discusses some of the newer package styles, including the ball grid array and multichip module.

TO-Style Packages

The TO-style package, used predominantly for analog or linear ICs, is a modified version of the conventional transistor-outline package, with more leads. TO-style packages have 2, 8, 10, 12, or 14 pins protruding from the bottom of the base or header. The base is usually a gold-plated Kovar header, which provides for hermetic glass-to-metal seals around the pins. The die is usually soldered directly to the header with a gold-tin (or other material) eutectic solder preform. Then the package is hermetically sealed by welding a nickel cap to the header flange. Figure 3.4 depicts an eight-lead TO-99 package and Fig. 3.5 a two-lead TO-3 package, which is primarily used for high current voltage regulators.

Flat Packs

The original 10- and 14-lead flat packs were manufactured for military applications because of their small size (0.25 in. × 0.25 in.), as shown in Fig. 3.6 and 3.7, respectively. The leads of flat packs attach parallel to the seating plane and for the flat packs shown typically originate from two sides of the package. The metal-glass flat pack consists of a one-piece base and a ring in which the Kovar leads are sealed. The glass is a ceramic compound (e.g., alumina), which provides excellent resistance to thermal and mechanical shock. The chip is mounted on the Kovar gold-plated base, and wire bond connections are made to the protruding leads. The large volume of glass around the Kovar leads ensures a reliable hermetic seal. Lids are attached by a layer of solder material between the ring and lid. The lid in this example is metal (gold-plated Kovar). Figure 3.8 is a cross-sectional view of a glass-metal flat pack.

Ceramic flat packs are constructed similarly to the metal type with base, ring, and lid of either alumina or beryllia. The cross section of a typical ceramic flat pack is shown in Fig. 3.9.

The flat pack has found extensive use beyond its military roots by having leads emanating from all four sides of the package case. Known as the quad flat

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Figure 3.4
Eight-lead TO-99 metal can package. (From
Ref. 1.)

pack or QFP, it is a widely used SMT package for encasing VLSICs and ASICs due to its low height profile and high pin count applicability (>200 leads). Figure 3.10 shows a dimensional outline of a typical QFP. The package can be constructed of either ceramic or plastic (PQFP) material.

Many large I/O count VLSIC and ASIC dice operate at very high frequencies and dissipate watts of power (an oxymoron to the classical definition of a CMOS IC). As such, packages for these devices (QFP and PGA) are either ceramic or plastic with an embedded metal layer to dissipate the heat. Figure 3.11 shows two versions of the latter package: (a) a 208-pin (available to 308-pin) PQFP with 0.5-mm lead pitch that uses an aluminum layer molded to the package body to disperse heat (a heat spreader) and (b) a cross section of a 208-pin PQFP that can dissipate up to 3 W of power using an embedded copper heat slug attached to a printed circuit board (PCB), which supports a copper lead frame. The slug provides a high efficient thermal path, allowing heat to dissipate easily. The exposed heat

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Figure 3.5
Two-lead TO-3 metal can package used for high-current voltage
regulators. (From Ref. 1.)

slug on top of the package allows a heat sink to be attached for even better cooling. In addition to thermal issues, ceramic packages such as shown in Fig. 3.12 are used to minimize electrical signal distortion and provide proper electrical termination for high-speed circuitry, resembling a complex multilayer PC board in construction. For example, the ceramic package for Intel's 386 microprocessor has 7 layers, the 486 package has 10 layers, and the Pentium has 16 layers.

Comparing Figs. 3.6 and 3.7 with Figs. 3.10 through 3.12 shows the advance and complexity of this package style due to the dramatic increase in the level of IC integration, i.e., I/O pin count. The quad flat pack comes with lead center spacings of 10, 15, 20, and 25 mils and in excess of 600 I/O pins.

The Dual-in-Line Package

Up until the mid to late 1980s the IC package of choice, because of its ease of use and low cost, was the dual-in-line package (DIP), and primarily the

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Figure 3.6
Ten-lead flat package. (From Ref. 1.)

Figure 3.7
Fourteen-lead flat package. (From Ref. 1.)

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Figure 3.8
Cross section of typical glass-metal flat pack. Internal bonding is ultrasonically bonded 0.001-in. Al wire. Die attach is performed with an AuSi
eutectic (98% Au and 2% Si). (From Ref. 1.)

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Figure 3.9
Cross section of typical ceramic flat pack. Die attach is made with an AuSi eutectic (98% Au and 2% Si) on the gold metallized depression
of the bottom ceramic piece part. (From Ref. 1)

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Figure 3.10
Plastic quad flat pack.

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Figure 3.11
Plastic QFPs with an embedded metal layer dissipate heat: (a) 208-pin power quad
flat pack; (b) 208-pin power quad flat pack with an embedded copper heat slug.

plastic DIP. The DIP's pin count range is from 8 to 64 leads, but the majority of devices produced usually are in the 1420 lead range. The DIPs are readily pluggable, they offer extensive socketing for test, burn-in, and production use, and they are designed to accommodate automated assembly techniques and are generally used in applications where size and space are not a premium consideration. Lower assembly costs result because of the 100-mil grid spacing, which permits relaxed tolerances and wider PC lines.

Cavity Dual-in-Line Packages

Cavity dual-in-line packages can be either glass-to-metal or ceramic in construction.

Figure 3.13 shows the cross section of a typical ceramic DIP package. The ceramic DIP is a multilayered structure with thick-film conductors on an internal layer and another layer cut out to form a cavity in which the chip is placed. Conductors extend from the chip compartment to exposed terminating pads at

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Figure 3.12
Ceramic QFP packages, such as this 164-pin, 450-gate GaAs array,
dissipate heat effectively and minimize signal distortion.

Figure 3.13
Typical ceramic DIP, in cross section. Die attach is made with an AuSi eutectic (98% Au and 2%
Si) on the gold metallized depression of the bottom ceramic piece part. (From Ref. 1.)

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the outer edge. The pads are brazed to a lead frame. The ceramic DIP seal is made by sealing the leads in glass at low temperature, adding the ceramic cover, and sealing it to the glass by firing at a higher temperature until the glass is devitrified.

Noncavity DIPs

Plastic or molded DIPs were popular because they were extremely rugged and impervious to mechanical shock and vibration, and their manufacturing costs were lowi.e., the molding process was readily adaptable to high production rates and the user could assemble them with automatic insertion and PC board soldering equipment.

The primary problem and area of concern with the plastic DIP has been the entry of moisture and contaminants into the packageall plastic materials absorb moisture. The entry path for moisture to a plastic-packaged chip is along the lead frame; this path may be opened during either the plastic curing process or the lead-bending operation. Capillary action can then bring moisture to the point where the lead frame separates from the plastic, allowing moisture to make its way to the chips. To reduce the chance of creating this path, molding procedures were developed that minimized the separation along the lead frame, and lead frames were designed to eliminate the capillary paths or at least to increase the length of the path. The silicon die, the lead frame, the die attach and the molding compound materials used were selected to have similar thermal coefficients of expansion, modulus of elasticity, and tensile strengths to minimize thermal stress-activated separations from occurring. Additionally, the resistance of the molded package to moisture penetration was increased by the development of new plastic materials that do not contribute ionic species that reduce chip life.

To protect the die from a hostile environment, the molded package should completely surround the die and the internal wiring, with materials that are impervious to penetration by gases and liquids.

While plastic packages do not have the heat dissipation capability of other package material types, they do possess the capability of meeting the wide temperature operating limits demanded of military equipment. However, they are usually specified for either 0 to 70°C, or -25 to 85°C operation, whereas the military range is -55 to +125°C. Additional chip processing, such as the deposition of a thick glass protective layer on top of the normal silicon dioxide passivating film or a silicon die coating, makes the IC chip itself more impervious to moisture and contaminants; thus the plastic encapsulation need provide only mechanical protection. Figure 3.14 depicts the cross section of a typical plastic DIP.

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Figure 3.14
Cross section of plastic DIP package.

Thus, to be reliable the package must be molded of an inert material that keeps the IC chip, lead wires, wire bonds, and lead frame in compression throughout the worst-case operating and junction temperature range. Furthermore, the molding compound should provide a thermal coefficient expansion match between itself, the lead frame, and the IC chip, and should possess high dimensional stability to a high temperature and high tensile strength.

However, the widespread usage of the DIP is rapidly declining because it cannot meet the performance demands of currently produced ICs. Key areas of shortcoming are speed (electrical performance), interconnection count and density (400-plus I/Os), larger die sizes, thermal performance, and inability to take advantage of reduced die geometriesleading to wasted PCB real estate.

A conventional DIP has 100-mil pin spacing, and each additional pair of pins adds a 0.100-in. increment to the length of the DIP. Thus, as the pin count of a DIP increases, its PCB space utilization efficiency drops sharply. For example, an 18-pin DIP with a 0.039 in.² chip occupies about 0.28 in.² of board space. But a 40-pin DIP accepting a maximum die size of 0.05 in.² requires 1.25 in.² of board space.

Critical to all applications is the increase in parasitic resistance, inductance, and capacitance as pin count grows and increases conductor length from the die to the terminals toward the ends of the package. Impedances generated by DIP traces during circuit operation now limit digital clock rates to about 500 MHz. Most system designs do not suffer from this speed limitation, but the faster systems may be victim to a related effect. In a 40-pin DIP, the longest trace is about six times longer than the shortest lead and seven times longer in a 64-pin device. Resultant parasitic impedance difference between the longest and shortest

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leads could upset timing signals, causing a source of system malfunction difficult to pinpoint.

Finally, the high aspect ratio (length/width) of conventional DIPs with over 40 pins makes the package susceptible to breaking during handling. These problems associated with DIPs are being solved by the refinement of previous package types as well as with the development of new packages.

To achieve the goals of higher functional density, lead count, and performance, the package sizes are being decreased. The trend in packaging is from DIPs to surface-mount packages using smaller profile plastic packages and hermetic chip carriers. Longer range, multichip modules will provide the direction for high-lead-count, high-density packaging.

The main package styles aimed at replacing the DIP are miniaturized versions of DIPs, or small-outline packages (SOICs), flat packages, pin grid arrays, and leaded and leadless chip carriers. These new packages are eliminating many of the problems associated with large conventional DIPs, but not without introducing some new problems of their own.

All of these, with the exception of the pin grid array, utilize surface-mount technology. However, it is important to note that dramatic package design changes are infrequent, and change occurs more slowly than for ICs themselves. One reason for this is the complexity of modifying interconnect standards and the substantial inertia to be overcome for redesign and tooling of boards, test equipment, and systems. Thus new packages are adopted slowly.

The Small Outline and Thin Small Outline IC Packages

The small outline package (SOP) and thin small outline package (TSOP) have become the accepted packages for low-pin-count surface-mount applications. These packages offer significant advantages over their DIP counterparts. Resembling miniature versions of molded dual-in-line packages, the SO-8, SO-14, SO-16 types in 8-, 14-, and 16-pin styles, respectively, are roughly one-eighth the size of a standard DIP equivalent. The SOP is approximately 5070 mils high and 155 mils wide. Length ranges from about 190 mils on the SO-8 and 340 mils for the SO-14 to about 390 mils on the largest SO-16. Lead spacings of 15, 20, 25, and 50 mils are available for all SOIC packages: 8 to 84 leads.

The SOP is very similar to the military flat pack, which is surface mounted. The technology is proven, reliable, and available, and the procedures for attaching and handling the packages are well established.

The SOP, constructed with an Alloy 42 lead frame, employs exactly the same die as its DIP counterpart. Encapsulated with a plastic molding compound,

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it provides an integrated circuit with a reliable barrier to hostile external environmental conditions and stresses.

The primary advantage of the SOP is its small size, which is primarily due to its 50-mil (or 20-mil) center lead spacing. The SOP occupies a board area of 3050% less than an equivalent dual-in-line package, and the typical SOP thickness is 70% less than a conventional DIP. Consequently, circuit boards that incorporate SOP devices can serve applications where space and weight are at a premium (Table 3.1). The SOPs fit nicely into those application areas where conventional DIP packaging is too large.

Considering their size, SOPs exhibit reasonable power dissipation characteristics. The parts' small thickness and short connections produce a thermal resistance between junction and solder pads or heat sinks roughly equal to that of a standard DIP mounted on a PC board. Because the thermal resistance depends on chip size, a range of actual values exists for each SO type. Nonetheless, use of the SOIC package is limited to small die size and low power dissipation applications.

A refinement of the SOP is the thin small outline package (TSOP), which was originally introduced for memory credit cards but has been rapidly adopted by IC memory and logic manufacturers for use in space-saving applications. The TSOP (Figs. 3.15 and 3.16) required wire bonding equipment refinements due to the required lower loop height and potential for die edge shorts, and molding process changes due to the thinness of the package (i.e., bowing).

Pin Grid Arrays

Pin grid array (PGA) packages are similar to ceramic chip carriers in construction except that the I/Os are accomplished through pins that populate the

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Figure 3.15
TSOP cross section diagram. (Courtesy of Amkor Electronics.)

Figure 3.16
TSOP fixed-voltage regulator. (Courtesy of Texas Instruments.)

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base or surface of the package in array fashion. The PGAs are designed to be through-hole mounted in PCBs or socketed for ease of replacement. Since this method requires little change in board technology, it is a popular way to package VLSI circuits.

Usually a square, ceramic, multilayer package, the pin grid array holds an array, or grid, of bottom pins on 100-mil centers and now on 50-mil centers. Minimum pin count is usually 64. As device performance pushes I/O count into the region of 84 pins or higher, the PGA becomes a solid choice for maximizing PC real estatewhile providing short lead lengths for optimum electrical performance. Popular pin counts are 64, 68, 72, 84, 100, 120, 124, 132, 144, 172, 184, and higher.

The pin grid array's major advantages are small size for large-lead-count packages, rugged construction, and its ability to accommodate large numbers of I/O leads. As an example, a 160-pin array would occupy less than one-half the area of a 160-pin JEDEC (Joint Engineering Device Engineering Council) chip carrier on 50-mil centers. On 25-mil centers, chip carriers would be approximately the same size as the pin grid array. Pins on both 50- and 100-mil centers allow the array package to be mated with current PCB technology.

A major disadvantage of the pin grid array is that it costs more than the other packages, and it is through-hole mounted. Also, desoldering a 160-pin package in a multilayer PCB without harm to the board takes considerable time and skill. Either the package and applicable board area must be heated to molten solder temperature, or the solder must be removed individually from each pin. Figure 3.17 is a photograph of a typical PGA package.

To address the cost issue of the PGA, the plastic PGA (PPGA) was developed. A cross section of a typical PPGA is shown in Fig. 3.18. The discussion on thermal and electrical issues presented for the flat pack is applicable to the PGA as well.

Chip Carriers

The chip carrier, in either leadless or leaded form, offers a practical replacement to the DIP, typically for low-pin-count applications. The carrier is designed to be surface mounted directly to a substrate or PCB with reflow solder techniques. The external configuration is either square or rectangular, with contact pads, or leads, around the perimeter of the package body.

The chip carrier's body is similar to that of a flat package, and bending the leads under the package separates the leaded chip carrier from a flat package. Lead counts range from 14 to 84 on 50-mil centers. Chip carriers are made of either multilayer ceramic, providing a rugged hermetic enclosure, with or without leads, or plastic in either a premolded or postmolded configuration, with leads.

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Figure 3.17
PGA package.

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Figure 3.18
PPGA cross section.

The chip carrier displays as its main advantages small size, light weight, and shorter, more closely matched trace lengths from die to terminals (of particular importance in high speed applications). Table 3.2 presents a size comparison of the leadless chip carrier (LCC) with the DIP.

For very low input/output (I/O) counts, an LCC typically occupies about one-third the board space of a DIP. At 28 pins and higher, the comparative space efficiency rating is even more impressive.

The LCCs also benefit from having shorter and more closely matched trace lengths from the die to the terminals. Short trace lengths allow the potential for operation up to 4 GHz because of lower parasitic impedances. And because LCCs have terminals on all four sides, the longest trace is only 1.5 times the length of

Table 3.2 LCC/DIP Size Comparison

Number of pins
DIP area (in.²)
LCC area (in.²)

18

0.276

0.100

28

0.854

0.160

40

1.257

0.230

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the shortest trace in 18-, 24-, 40-, and 64-lead packages. This means that the circuit performance at high frequencies is more reliable than DIPs.

JEDEC has standardized two package styles (one with 50-mil center terminal spacing and another with 40 mil) and provided interchangeability (within similar center terminal-spacing outlines) so that designers can interchange types to suit changing requirements without redesigning the interconnecting assembly.

The 50-mil center family contains seven variations (Fig. 3.19). Four leadless types, A, B, C, and D, mount in different orientations depending on the type, mounting substrate, and preferred thermal orientation. These packages are ceramic with hermetically sealed metal or ceramic lids. When the leadless types mount with substrate clips, they become the leaded Type B packages.

The Type A category comprises two standards. The first, a one-of-a-kind 24-pin-only outline, is strictly a premolded plastic (PMP) package. The second leaded Type A package (MS 007) has two versions: either a substrate clip on a leadless Type A package or a PMP package. This second leaded Type A unit comes in a wide assortment of pin counts. Figure 3.20 is a dimensional outline of a 20-lead molded PLCC.

The differences among leadless chip carriers are the internal features and mounting orientations with respect to substrate and thermal performance. Figure 3.21 summarizes the socketing and soldering requirements of each of the packages of Fig. 3.19.

Since leads are short and bent under the package, the leaded carrier appears to be easier to handle in system assembly. Leaded chip carriers and flat packages are interchangeable; deciding which to use will depend upon the final assembly technique.

Limiting factors for greater application of chip carriers to date are the relative scarcity of viable methods to surface-interconnect the package to the board and the lack of equipment for handling, processing, and testing.

Soldering chip carriers on conventional epoxy/glass boards remains the number one problem area with this packaging technology, however. The problem stems from the difference in thermal coefficient of expansion (TCE) between ceramic chip carriers and PCBs. On ceramic substrates, direct chip carrier soldering is fairly simple using reflow soldering.

Because leadless chip carriers solder directly to the substrate surface, there is a strain on the solder joints if the substrate and chip carrier do not remain in the same dimensional relationship. This suggests ceramic chip carriers on ceramic substrates. However, both the package and the board may expand or contract with changes in temperature, and the strain on solder joints will not be excessive if the temperature coefficients of expansion match reasonably well.

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Figure 3.19
The 50-mil center terminal spacing JEDEC outline for chip carriers includes four leadless types and three leaded types. The
Mini-Park has been registered but not approved.

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Figure 3.20
Typical 20-lead molded PLCC package. (Courtesy of National Semiconductor Corp.)

Matching temperature coefficients does not fully resolve the problem. Even the best choice of substrate coefficient will still produce strains during every on/off cycle. This effect limits the use of leadless chip carriers to low-wattage applications with very little temperature difference between package and substrate, so that in effect the temperature expansion is the same.

Currently, leaded carrier packages are preferred over leadless package styles. Leaded chip carriers can handle mismatched thermal expansions and variations from flatness as well. Overall, chip carriers promise to be a dominant

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Figure 3.21
Deciding which chip carrier to use, based on whether it can
be directly mounted or socketed, is another trade-off. The
leadless Type A requires socketing regardless of substrate,
for instance, while the leaded Type B must be soldered in
all cases.

packaging force for all semiconductor products in the foreseeable future. Figure 3.22 provides a pictorial comparison of several through-hole and surface-mount technology packages.

Surface-Mount Technology

All manufacturers of electronic systems have rapidly turned to surface-mount technology (SMT) as a more cost-efficient manufacturing alternative to conventional through-hole mounting. This change represents a major shift in electronic system manufacturing technology.

What is surface mounting? Surface mounting is the process in which a packaged IC or other component is physically mounted on to the surface of a PCB rather than inserting leads into plated holes through the PCB. As mentioned

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Figure 3.22
Comparison of through-hole and surface-mount
technologies.

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before, SOIC packages, flat packages, and chip carriers are all surface-mountable packages.

Surface-mount technology has advantages that make it much more cost-effective than through-hole technology. Among the more commonly cited advantages are

The ability to readily automate the SMT manufacturing process

Increased functional density, which allows smaller circuit boards or more functions within the same boundary constraints

A reduction of the number of interconnect layers necessary in multilayer boards

The use of shorter signal path lengths, which can improve high-speed circuitry performance

Despite the advantages, the adoption of SMT is not without pitfalls and problems that must be addressed before its benefits can be fully realized. Some of these are within the control of the user, while others are not. Differences in circuit constructions, manufacturing processes, components, and materials must be addressed. New circuit design rules have to be formulated and used. Different environmental constraints exist, which must be identified and addressed.

Standardization of component packaging is another significant issue. The lack of uniformity in packages can complicate both circuit design and manufacturing. Efforts, led by JEDEC, have developed standards for surface-mount component packages. One of the main advantages cited for surface-mount technology is its adaptability to automation. In the mid 1980s the lack of uniformity in component standards, coupled with the reluctance of some device suppliers to conform to those existing standards, complicated the automation process. However, this has now changed with the availability of various JEDEC package standards.

Two types of lead configurations are used for the surface-mount device (SMD) integrated circuit packages. Gull wing leads, which spread away from the device, are used on both SOIC packages and plastic-leaded chip carriers (Fig. 3.23).

Figure 3.23
Gull wing leads.

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The main advantage of the gull wing is that the solder joint can be easily inspected. The disadvantage is that the exposed leads tend to bend and break because the solder joint is in shear.

The second lead configuration is the J lead, so called because it resembles a J with the leads tucked under the device. It is used on the PLCC package (Fig. 3.24).

The advantages of the J-leaded devices are that they occupy less board space than the gull-winged devices, the leads are less subject to damage during handling because they are tucked under the device, and the leads are in tension and thus they are the stronger of the two lead-style categories. The disadvantages are that the J-leaded devices present testing, inspection, and repair problems. The hidden leads make it difficult to visually check solder joint quality, and the pad leaves no room for test probes and rework tools.

Probably the most significant consideration when adopting surface-mount technology is assuring the reliability of the interconnection between the ICs and the substrate. Surface-mount IC attachment relies exclusively on the attaching medium, be it solder (the main technique used) or conductive adhesive (currently being investigated as an alternative to solder), in order to make the connection to the surface conductor. Through-hole mounting technology, on the other hand, also makes use of the clinched lead and solder in the plated through-hole to assure a reliable connection and provide some mechanical strength. Thus, the integrity of joints between the IC, the attachment medium, and the substrate surface is extremely critical for surface-mount technology.

Because of the importance of forming a reliable solder joint, component and substrate solderability must be assured. Reliability is particularly important,

Figure 3.24
J-Lead package.

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since defective solder joints are not easily observable or repairable. The predominant causes of PCB failure, rejection at board test, and rework are user handling issues and defects relating to the solder joints and solder attachment process. Planarity of component leads and flatness of the substrate are essential.

Rapid change is occuring in improved packaging with respect to functional density, high-speed performance, and high power by means of surface mounting of packages using higher density board technology.

Two significant factors must be considered when weighing packaging and interconnection alternatives. First, in today's design environment, one must consider the packaging approach as a whole, not just the silicon and its unique function: The IC, the attachment method to the PCB, and the PCB itself all must be considered a single component, a system. Second, as integration grows at the chip level, the associated packaging system is not simplified, but must become more sophisticated to accommodate speed, transmission line effects (loss and termination), thermal, and other performance considerations.

Die Bonding

No matter what package type is used, the basic assembly operation is the same. The good circuits (dice) from the scribe and break operation are the only ones that will be assembled in packages. The first step in the assembly process is die bondingsoldering, brazing, or glassing the IC die to a package substrate in which the chip is mounted into position in the package (hermetic), on the lead frame (plastic), or directly on a PCB. The attachment material is a mechanical contact, a thermal path, and sometimes an electrical contact, all in one.

Die attachment on metal substrates is generally accomplished by a eutectic brazing alloy such as the gold-germanium alloy in the TO-5 package cross section of Fig. 3.25. Gold preforms are often used for ceramic packages and for attaching the die to the lead frame in plastic packages. Note that the silicon circuit was backed with gold to enhance the bond. As mentioned previously, a eutectic alloy is a combination of two or more metals whose melting point is significantly lower than the melting point of any of the alloy constituents. In particular, the eutectic is the alloy having the minimum melting point for a given combination of metals. Certain bimetallic systems exhibit more than one eutectic point, but these generally are not important. It should be emphasized that these bimetallic alloys are mixtures, not chemical compounds. A eutectic brazing alloy is usually preferred over soft solder for die attachment because of its higher melting point.

In some instances if an electrical connection to the substrate is not used, either a low-melting-point glass frit or an epoxy glue can be used to cement the chip down. Both methods involve heating to a temperature between 300°C and 400°C until the metal (gold), glass frit, or epoxy fuses with the silicon and forms a strong bond.

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Figure 3.25
Silicon monolithic assembly. (From Ref. 1.)

The die bonding process utilizes three categories of materials: solders, organic adhesives, and glass adhesives.

Solders

Solders are classified as either hard or soft solders. Hard solders (Au-Si, Au-Sn, Au-Ge) have rather high flow stresses (onset of plastic flow) and thereby offer excellent fatigue and creep resistance. The disadvantage of using hard solders is primarily their lack of plastic flow, which leads to high stresses in the silicon chip due to the thermal expansion mismatch between the die and the substrate.

The soft solders are low-melting-temperature binary and ternary (e.g., Pb-Ag-In and Pb-Sn) compositions that have a high degree of plastic strain capability. This allows for a reduction of the thermal stresses on the chip, but makes the solders prone to fatigue and creep-rupture failures at the device-operating temperature. However, in spite of the low die-stress advantage, the soft solders have failed to emerge as a popular group of useful die bonding materials.

Organic Adhesives

Epoxies and polyimides filled with precious metals have found widespread acceptance as die bond materials for use in plastic package assembly. They provide the lowest processing temperatures and lower cost compared to the gold-based hard solders.

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These adhesives are filled with a metal to provide the thermal and electrical conductivity required in most applications (silver being the most common filler). However, the use of organic adhesives in high-reliability packages (hermetically sealed) has been slow to gain acceptance due to the poor thermal stability of these materials, especially when filled with silver. Furthermore, due to the high amounts of solvents and binders used in these adhesive pastes for processing purposes, it is extremely difficult to obtain a die bond area free of any voids, leading to poor thermal dissipation and other reliability concerns. The poor thermal stability coupled with the outgassing of entrapped solvents and other gaseous species remains a challenge in the application of these materials to high-reliability VLSI applications.

Glass Adhesives

Silver-filled specialty glass materials have emerged in the past few years for use in VLSI die bond applications as the material of choice. These materials offer the possibility of a void-free die bond interface with excellent thermal stability. However, the currently available materials require high processing temperatures (>400°C) and oxidizing ambients for optimum adhesion, creating some special processing concerns. In addition, the glass die bond materials also need solvents and binders for processing purposes, leading to the problem of complete solvent removal, similar to the case of organic adhesives.

Wire Bonding

With the chip firmly mounted in the package, the next step in the assembly process is to make the electrical connections from the bonding pads on the chip to the package leads. The three types of wire bonding used are thermocompression, ultrasonic, and thermosonic. They vary primarily with respect to the shape of the bond, the type of wire used, and their basic operating conditions (such as temperature and pressure).

Thermocompression wire bonding is the most widely used bonding process. The principle here is to join two metals using heat and pressure, but without melting. The elevated temperature (approximately 270°C) maintains the metals in an annealing state as they join in a molecular metallurgical bond. The process is quite involved, but generally speaking, the softer the metals, the more readily they bond together. The basic method actually encompasses three different bonding processes: wedge, ball, and stitch.

The oldest form of thermocompression bonding is known as wedge bonding. This technique requires two separate alignments (X and Y) and is rather slow. However, it is very useful with small-diameter wires. It is also quite simple to produce two bonds with the same wire on the same land, thereby improving joint reliability.

A technique more suited to higher bonding rates is known as thermo-

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compression ball bonding. In this technique the gold wire is fed through a capillary needle as shown in Fig. 3.26a; then a minute hydrogen-gas flame is passed across the wire, melting it and forming the ball on the end as shown. The package with the mounted chip is heated to about 300°C, and the capillary is lowered so that the ball on the end of the wire contacts the terminal pad on the chip (Fig. 3.26b). A suitable pressure is applied to flatten the gold ball, and the combination of pressure and temperature results in the gold welding to the circuit pad (Fig. 3.26c). The capillary is then raised up the wire, moved horizontally until it is over the package terminal, and lowered to weld the wire onto the terminal (Fig. 3.26d). After this second weld, the capillary is raised again, and the wire is cut by passing the flame across the wire. This also forms a new ball on the end of the wire, ready to repeat the sequence for the next connection (Fig. 2.26e).

A disadvantage of this type of bonding is the presence of the cantilever tail formed with each bond. Under conditions of extreme vibration this tail can be broken off within the package, and is thus an incipient cause for circuit failure. A technique frequently used as a compromise between wedge and ball wire bonding and one that avoids the aforementioned problem is thermocompression stitch bonding. In this technique, a cut-off arrangement is used in place of the flame-off. This allows for the use of gold and aluminum wire and smaller

Figure 3.26
Sequence of the ball-bonding process.

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bonding areas. The cut-off process also forms the wire for the next stitch-bond operation. The steps used in the stitch bonding operation are as shown in Fig. 3.27.

The problem of purple plague (the formation of gold-aluminum intermetallic compounds that degrade the contact and cause voids, resulting in lifted bonds and opens in aluminum metallization) is avoided by a system in which aluminum leads are bonded to aluminum pads, or gold leads are bonded to gold pads. In this way the binary Au-Al system is avoided at the lead-chip interface. However, if an aluminum lead is used, it must eventually be connected to the gold-plated terminal post. This tends to alleviate the problem to some extent, since compound formation is accelerated in the presence of a third component such as silicon.

Ultrasonic bonding, which is performed at room temperature, is used primarily when bonding aluminum wire to aluminum bonding pads. In this process, the bonding tool vibrates at high frequency to provide the required bonding energy. The wiping motion of the ultrasonic lead removes any oxide films possibly present on the contact pad and strong intermolecular bonds are formed. The principal advantage is that neither the substrate nor the needle is

Figure 3.27
Sequence of the stitch-bonding process.

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heated. Thus, surface cleaning is not critical, and there is almost no contamination of the bond or the surrounding materials.

It must be noted, though, that a slightly larger area of contact is necessary to accommodate the scrubbing action. Also, extreme care must be taken not to damage the chip during the ultrasonic bonding operation.

Because ultrasonic bonding can create bonds between a wide variety of dissimilar materials, it is an extremely flexible process. Thus, both gold and aluminum wire are compatible with this technique.

Void-free junctions are produced by ultrasonic wire bonding with relatively few foreign material inclusions, making it a desirable means of creating high-quality, low-resistance, low-noise electrical junctions. Also, bonding dissimilar metals at low temperatures eliminates, or greatly decreases, the formation of intermetallic compounds and allows bonds to be made in the immediate vicinity of temperature-sensitive components without adverse effects.

Ultrasonic bonding is commonly used with VLSI circuits that have a large number of bonding pads, since this avoids subjecting the chip to elevated temperatures during this process.

Thermosonic wire bonding combines ultrasonic energy with the basic elements of thermocompression wire bonding. This technique relies on the vibrations created by the ultrasonic action to scrub the bond area to remove any oxide layers and also to create the heat for bonding. Combined with the pressure of the tool used to force the wire into the bonding land, this provides the final bond. Since bonding here can take place at temperatures between 250 and 350°C, thermosonic wire bonding can be done with low-temperature materials.

Aluminum is difficult to bond by the thermocompression method because at typical temperatures of 250350°C, a hard oxide forms that inhibits bondability. However, gold is usually bonded with a thermosonic technique. The reduced temperature of thermosonic bonding permits the use of epoxies and low-temperature solders without compromising reliability.

Today's wire bonders make all the connections to the chip in a single operation simultaneously and at a high rate of speed. So metrology considerations of the automatic wire bonders are extremely important. A wire bonder that drifts out of calibration or that is set up to make misplaced bonds, for example, will make thousands of uniform bonds with these errors.

Alternatives to Wire Bonding

The Flip-Chip Process

The advanced packages currently used and/or proposed will not adequately address the performance demands of VLSI circuits of the near future. At some point, the limits of speed will be reached and higher density technologies, such

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as tape-automated bonding (TAB), area array tape bonding, flip-chip techniques, or wafer-scale integration, will be needed.

The flip-chip interconnect technique was the first attempt to eliminate the costly and time-consuming process of wire bonding, thus simplifying the assembly operation. Flip-chip technology is based on the use of controlled collapse solder bonding. The basic procedure of making a flip chip involves replacing flat bonding-pad areas with raised bumps. These bumps can then be placed into contact with metallized pads similarly located on a substrate or package bottom and, by suitable means, all can be joined at one time. In usual assembly techniques, the chip with the bump is flipped upside down onto the pad pattern, thus the term flip chip.

The chips are then mounted to the interconnecting metallization on the substrate by pressure and heat or ultrasonic energy. The use of solder-coated copper balls sandwiched between the chip termination lands and the appropriate termination lands on the interconnecting substrate is illustrated in Fig. 3.28 for an early flip chip process applied to a hybrid circuit. In some approaches bump contacts are formed on the die; in others, bump contacts are formed on the substrate. The die bonding and wire bonding being performed in one operation for the flip chip process provides the potential to reduce costs, achieve better quality, increase the reliability, and provide easier handling.

However, for the early flip-chip process, the handling and placement of the small diameter balls was extremely difficult and the operation proved to be costly. Other problems that were encountered included:

Figure 3.28
Typical cross section of flip-chip hybrid circuit application.

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1. Bump height is critical; if equal heights are not obtained, all bonds will not uniformly contact the package bottom.

2. Electrical testing, which must be done after the bump is formed, is a critical operation because excess probe pressure can cause damage and is highly likely to deform the bump, with the attendant disastrous change in height. Too light pressure gives unreliable test results.

3. Face-down bonding of flip chips means that the completed bonds cannot be inspected.

4. During bonding of flip chips, pressure to complete the bond must be applied to the back of the chip itself, with the danger that heat, stresses, and cracks may damage the chip. The addition of a greater number of bumps means more force must be applied to achieve the minimum pressure necessary to bond.

5. Because the chip is held rigidly to the substrate by the bonds, any thermal shocks to which the die may be subjected can cause stresses to build up that may damage the die or the bonds themselves.

In a more advanced technique, a raised metallic bump or lump, usually solder, is provided on the chip termination land. This is normally done on all lands of all of the chips while they are still in wafer form. The individual chip is then aligned to the appropriate circuitry on the substrate and bonded in place using reflow-soldering techniques. In this way, the interconnection bonds between the chip and the substrate are made simultaneously, reducing fabrication costs.

The use of flip chips with controlled collapse bonding (introduced by IBM in 1964) has potential for very high assembly rates. For example, with only the use of simple optomechanical assists, manual chip placement rates as high as 200 per hour have been achieved. This results in a very high assembly/bonding rate if a chip has many input/output terminations.

To date, the use of flip-chip devices has been limited to very special packaging applications, for example, hybrid packages. The primary advantages of using flip-chip packaging processes are fast throughput times, efficient use of board area, short electrical interconnect lengths, high I/O densities, ruggedness and ease of handling, low cost, and proven reliability. Flip chips are also self-aligning between the chip and the substrate pads. Major disadvantages include an inability to visually inspect the assembled chip; limited availability of bumped chips; difficult flux removal; thermal management of high power ICs; poor infrastructure; lack of standards for known good die (KGD); and the questionable reliability of large chips in nonsilicon substrates.

Tape-Automated Bonding

Tape-automated bonding (TAB) has emerged as a viable interconnection technology for VLSI devices. (It is more of an assembly technology than a

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packaging technology.) TAB is the predecessor of the beam lead bonding technique developed by Bell Telephone Laboratories, Inc. (see Ref. 1 for a discussion on the beam lead technique).

TAB utilizes photoimaging/etching processes to produce fabricated conductors on a dielectric tape. The most striking aspect of the TAB system is the carrier tape; it looks much like movie film because of its sprocket drive holes and comes in widths from 8 to 70 mm. Windows are punched at specific locations and a thin (often only 0.0014-in. thick) conductive foil, typically copper, is bonded to the tape, which is itself usually either Mylar or polyimide. A conductive pattern is then etched in the foil to give the desired interconnection circuitry with beam-type leads that extend over the windows in the tape.

In subsequent processing, the beams are simultaneously bonded to the chip, which is precisely located under the window. The exact location of the chip with respect to the sprocket holes on the tape carrier permits the use of automated tape-handling equipment that accurately positions the individual chips for the subsequent processing operations.

Two TAB processes are involved. Dice are attached to a continuous, filmed lead frame, called a tape, by an inner-lead bonding (ILB) process. Then the attached chips are removed from the tape and connected to conventional lead frames or hermetic packages with a second TAB process called outer-lead bonding (OLB).

TAB can, however, also be used by itself as a packaging techniquefor the direct surface mount of a TAB-processed chip to a printed circuit board. A bare section of ILB tape with the attached die can act as a mini chip carrier. The section can be protected with a suitable coating or mold-on plastic.

The Basic Process. The initial stage of TAB wafer preparation is much the same as that for wire-bonded wafers. A pinhole-free silicon nitride passivation layer (or silicon dioxide or polyimide in some cases) is deposited at low temperatures. As shown in Fig. 3.29a, passivation is selectively removed to expose the aluminum bonding pad. This is the state in which a chip would be presented for wire bonding, and the exposed pad would be a problem. The gold wire ball bonding with the resulting gold-aluminum intermetallic interface could spell trouble.

At this point in the preparation of a chip slated for TAB, a barrier metal such as titanium-tungsten is deposited not only over the exposed aluminum, but up and out over the passivation on the periphery of the pad (see Fig. 3.29b). The titanium-tungsten (TiW) provides a good adhesion to the aluminum, has excellent step coverage, and adheres well to the passivation, which is typically silicon nitride. The TiW is also an excellent diffusion barrier for isolating the gold and aluminum. These steps plus the final step, the addition of 0.001-in.-high gold bumps, help ensure the reliability of the TAB connections to the tape during

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Figure 3.29
Bonding pad cross sections show (a) the unprotected aluminum pad, (b)
the barrier-metal cap, and (c) the 0.001-in. gold bump. The cap and
gold bump seal the chip.

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innerlead bonding. The gold prevents oxidation of the TiW and forms the base for electroplating the bumps. Copper/gold bumps can also be used (Fig. 3.30) and both copper and gold can be tin-plated.

The bumps on the chip are electroplated onto the barrier metal at each pad position. A photoresist-masking step combined with a flood-plating process and selective etching step builds 25-mm-high bumps at the pad locations that extend above the passivation surface. This process completely seals (through the passivation down to aluminum metallization) the chip by preventing external impurities from diffusing into the contact structure, providing essentially a hermetic chip, further enhancing TAB's reliability as a direct surface mounting technique.

A variation of this process puts the bump on the tape rather than on the chip. This approach is known as BTAB. In either case, the bumps are necessary to elevate the etched tape conductors above the chip to prevent shorting of the leads. Then the IC is electrically tested.

At this point the TAB chip can be either directly attached to a PC board (COB) or encased in a traditional package.

Lead Bonding. After the tape is fully fabricated, the next operation is to make the inner-lead bonds between the chip and the etched cantilevered conductors on the tape. The positioning for this operation is controlled by the holes on the tape. Monitoring the chip position is accomplished by using a television monitor or microscope.

The ILB process immediately follows die and tape preparation to join them together. Using a thermocompression bonding technique, all copper interconnect leads on the polyimide tape are bonded at the same time to their respective bond pads on the die. (This is an advantage over standard wire bonding where each bond is done sequentially.) Once the leads have been bonded to the die, a thin

Figure 3.30
Cross section of copper-gold (Cu-Au) TAB bump sandwich.

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Figure 3.31
Outer-lead bonding process of TAB in which the die is flipped
before bonding to pads on the substrate.

layer of epoxy resin is applied over the top surface of the die for protection. The die is now suspended within a tape frame, which provides for easy testing as well as burn-in, before mounting on the substrate.

During the OLB process, or mounting the die on the substrate (see Fig. 3.31), the die is flipped and excised from the tape, followed by thermocompression bonding the copper interconnect leads to pads on the substrate.

Figure 3.32, which shows a TAB-bonded IC, details the inner- and outer-lead bonding connections, and Fig. 3.33 provides the outline dimensions

Figure 3.32
Drawing of TAB-bonded IC chip.

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Figure 3.33
Outline dimensions of tape pack. (Courtesy of National Semiconductor Corp.)

of a typical tape pack. The thin layer of epoxy, which covers the top of the die, is now called the inner mold because it is sandwiched between the die and the substrate. The final step is to cover the exposed leads with epoxy resin around the periphery of the die (the outer mold).

TAB interconnections provide a distinct advantage over wire bonds as a means of mounting bare IC chips to printed circuit boards. TAB allows smaller pads with closer spacing and shorter lead lengths to maximize circuit density and minimize interconnect length. TAB leads have rectangular cross sections, which

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exhibit lower inductance at short lead lengths. The larger cross-sectional area of TAB interconnects and the use of copper as the lead material provide greater mechanical strength, lower electrical resistance, and lower thermal resistance. Furthermore, TAB lead shape after assembly provides shorter lead lengths and lower profile height, resulting in improved transmission-line characteristics for high-speed operation. Table 3.3 compares calculated electrical and thermal properties for a round wire bond versus a rectangular cross-section TAB lead. Because of the significant tooling required for tape development, bonding tools, test fixtures, and die bumping, TAB is reserved for high-volume applications that can justify the costs, or for applications where size constraints mandate the use of TAB.

One of the most recent interconnection technologies is known as area array TAB (ATAB). In this approach, circuit patterns are fabricated on multilayer metal beam tape, allowing the chip designer to put the I/O lands at any position on the chip as opposed to being on the periphery of the chip. This reduces the signal path lengths required and thereby reduces signal delayit provides controlled impedance interconnects.

Conventional TAB designs using pads on the perimeter of a chip with 80100 mm center spacing will accommodate I/O counts up to 250, doubling the maximum density achievable with wire bonds.

Area array TAB designs using multilayer tape construction accommodates I/O lead counts in the 300500 range, matching the density achievable with solder bump interconnections. In fact, most ATAB designs use solder-bumped devices to accomplish the mass interconnection of the chip to the tape.

Another TAB advantage is its testability. If the tape is properly designed,

Table 3.3 Comparison of Key Interconnection Performance Characteristics

Wire bonda

TAB leadb

Parameter
Aluminum
Gold
Copper

Electrical properties

Lead resistance (ohms)

0.142
0.122
0.017

Lead-to-lead capacitance (picofarads) (0.008-in. spacing)

0.025
0.025
0.006

Lead inductance (nanohenries)

2.621
2.621
2.10

Thermal resistance

Lead conduction (°C/mW)

79.6
51.6
8.3

Lead convection (free) (°C/mW)

336.5
336.5
149.5

a0.001-in. diameter × 0.10-in. long wire bond.

b0.001-in. × 0.004 in. × 0.100-in. long TAB lead.

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each device can be tested after inner lead bonding, while the device is still in reel-to-reel format. Also noteworthy is the fact that TAB has inherently high assembly speeds and production efficiency, which make it suitable for automation. Table 3.4 summarizes additional salient TAB advantages as well as disadvantages.

Sealing and Molding the Package

Once all the wire-bonding connections have been made, the package is sealed and the device is ready for final testing. In the case of ceramic or metal-to-glass packages such as the flat-pack and TO-style packages, this consists of welding on a lid to give a hermetic enclosure. With the plastic package, the lead frame assembly is placed in a mold, and the plastic body is molded around it. Figure 3.34

Table 3.4 Summary of TAB Characteristics as Compared with Wire Bonding

Advantages

Disadvantages

Rugged, flexible, high-density connection
More complex wafer processing

Built-in high package reliability
Criticality of bump metallurgy

Bonding areas on the chip can be her- metically sealed when a gold bump is constructed on the bonding land

Inner- and outer-lead bond processing criticality such as silicon cratering during inner lead bond

Backside thermal attachment to chip

TAB requires specially designed equipment to match each application, both at the chip and board interface

Easily tested

Smaller lead lengths and smaller bonding pads with closer spacing

In general, TAB chips cannot be purchased economically in small quantities

Smallest surface area and volume of any available packaging concept

Bonding lands can be as small as 0.002 in.2 on 0.004-in. spacing

Lack of commercially available ''bumped'' wafers or chips

Input/output counts can be as high as 300 or more leads

TAB bonding and bumping equipment is rather sophisticated

Very low (0.030 in.) profile chip-on-board assemblies can be made: devices can be mounted in a recessed cavity in the substrate, further reducing heigh

TAB provides a method for automated simultaneous bonding of all the leads to the chip and board

Rectangular TAB lead provides a lower inductance than does a round wire to enhance its use in high-speed applications

TAB is reworkable

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Figure 3.34
Silicone protective die coat being applied.

shows a silicone protective coating being put on each die of the finished uncut lead frame to provide stress relief during the molding operation, as a moisture barrier during use, and for alpha-particle protection (for memories). Figure 3.35 shows an example of a typical uncut lead frame after completion of the injection molding step. Figure 3.36 provides a pictorial comparison, while Table 3.5 provides a comparative summary of currently used lead bonding techniques.

Reiterating, wire bonding, flip chip, and tape automated bonding (TAB) (Fig. 3.36) are the most widely used methods for providing electrical interconnects. Wire bonding is a proven and well supported technology, but it does not allow chips to be pretested at speed and its electrical performance is limited by high inductance and heat dissipation. Rework economics for wire-bonded high-density MCMs (multichip modules) could become overwhelming.

Flip chip and TAB both require additional materials and processing. Flip chip has the highest density and the best thermal performance. The flip-chip technique involves placing solder on each bond pad, turning the chip upside

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Figure 3.35
Plastic package injection molding process.

down so that the pads touch the solder on the substrate, and heating until the solder flows. Although flip-chip solder bumps are hidden so that they cannot be tested, defective chips can still be unsoldered and replaced, a feature that could make flip chip the enabling technology for large-scale MCM production. One problem with flip-chip technology is that differences in thermal expansion become a concern when mounting silicon flip chips on low-cost PCBs.

TAB enables pretesting of chips at speed, before substrate attachment. This is a significant advantage over the wire-bonding and flip-chip approaches. TAB also offers important cost/performance advantages but faces high entry cost. Although there are problems with TAB repair, pretesting should help eliminate the need for rework.

Electrical Testing

Electrical testing of the finished product is performed to:

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Figure 3.36
Common MCM interconnect bonding methods.

1. Identify and reduce outgoing defect levels

2. Identify manufacturing process deviations

3. Verify conformance to specification limits

Categories of Electrical Test

The types of tests conducted on ICs can be divided into several categories: functional tests, parametric or DC (static) and AC (dynamic) tests, and defect-oriented tests.

These are summarized for various IC categories in Table 3.6.

Functional Testing

The intent of functional testing is to provide verification that the device under test performs its intended function. This type of testing implies logical stimuli on all input nodes simultaneously with respect to the time at which logical signals on output nodes are measured and compared with expected values. Functional testing finds failures due to shorts between pins, broken wires, improper packaging, bonding, some masking errors, and the like. Historically, functional testing came about with the development of complex devices requiring

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Table 3.5 Comparison of Lead-Bonding Techniques

Bonding Method

Lead type

Active Elements

Used in

Advantages

Thermocompression
Au wire
300°C heat, pressure
Hybrids, ICs, transistors
Speed: 8 wires/sec
Reliability

Most commonly used method, automatic and semi-automatic equipment

Ultrasonic wedge
Al wire
Ultrasound
Scrubbing
Hybrids, ICs, transistors
Energy efficient
Lowest cost

Thermosonic
Au, Al wire
Ultrasound
Heat
Hybrids, ICs, transistors

Energy efficient
Faster than ultrasound due to use of heat

Tape-automated bonding

Cu, Au ribbon lead
Heat, pressure
Polymide tape format
ICs

Ease and accuracy in multiple lead bonding

Leaded IC can be tested prior to package insertion

Flip chip
Solder bump

Additional plating step puts bumps on chips or on tape

ICs

Bumps replace leads to reduce lead inductance

Ease and accuracy of bonding for high-I/O chips

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Table 3.6 Basic Test Categories

Purpose

Test

Memory devices

Digital devices

Analog (linear) devices

DC testing

Verifies basic critical characteristics such as breakdown voltages, threshold voltages, leakage currents, Icc, min/max output states, and output sink/source currents

Verifies basic critical input characteristics such as offset voltages and currents, bias currents, gain, output leakage currents

Functional testing

Checks storage and retrieval or standard patterns at rated cycle rates or frequency

Verifies truth-table performance of device

Verifies basic operational characteristics such as gain or continuity checks

AC testing

Measures time difference such as access times, setup and hold times, strobe widths, and cycle times

Measures pulse characteristics such as propagation delays, pulse rise times, delay times, and operating frequency capabilities

Measures characteristics such as pulse response times, frequency response characteristics, slew rate, and various circuit delays

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extremely time-consuming parametric testing. Functional testing usually involves a large number of tests, but can be performed at the highest machine (ATE) speed to shorten test times.

Since functional testing is normally much faster than DC or AC parametric testing, it is put first in the test sequence to identify nonfunctional parts. The ICs that pass the functional test are then subjected to the longer DC parametric and dynamic measurements in the test sequence. A device that passes functional tests has a high probability of being logically correct and is unlikely to have any physical faults that could be detected by DC testing. However, for complex ICs such as memories and microprocessors, for example, functional testing is generally more time-consuming and thus more costly than DC testing, since it requires a pattern generator and driver at each input with a discriminator and comparator at each output pin, and is thus performed after the DC parametric tests for these device categories.

Static Tests

Static or DC tests are those in which steady-state voltages and currents are applied to certain terminals of the device, and the corresponding voltages and currents at the same or other terminals are measured. They refer primarily to tests in which the inputs are maintained until the outputs reach a stable state. These tests uncover problems in substrate resistivity that may result in gain that is not within design tolerance, major mask faults that prevent the device from meeting parameter specifications, and other manufacturing errors.

Test rates for measuring DC parameters are influenced by the implementation technique, required accuracy, settling time of measurement signals, and analog-to-digital conversion time. There are various implementation methods for performing a DC measurement; however, it should be noted that in general it is necessary to preset the internal states prior to measuring a DC parameter. Test rates can be enhanced by functional testing prior to testing DC parameters, thereby shortening the total test time required to run through the entire test program on those devices that are catastrophic failures.

When testing simple SSI and MSI devices, DC testing does a reasonable job of duplicating the actual performance. However, this is not the case for LSI and VLSI circuits. For these devices a DC test is applied only to identify gross defects before beginning more sophisticated and necessary functional and dynamic tests.

Dynamic Tests

Dynamic tests are those in which voltage pulses or sinusoidal voltages are applied to the inputs of the device, and measurements in terms of time or instantaneous voltage are made at the output. Testing occurs near the maximum frequency of the device. Alternating current testing is performed to guarantee all areas of operation specified on the data sheet. This yields measurements under

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actual operating conditions, thus allowing device performance to be determined much more realistically.

Timing is most critical in IC memories and microprocessors. Each timing parameter requires extensive testing in order to verify correct circuit operation. Dynamic testing is considerably more expensive than DC testing alone. To reduce the test cost of dynamic testing some suppliers test most device parameters on a DC basis, and employ AC testing for those parameters, such as noise immunity, that cannot be adequately checked or correlated by DC techniques.

Defect-Oriented Tests

Defect-oriented tests are tests developed to detect specific design, fabrication, or assembly imperfections. One such test for CMOS ICs is quiescent (leakage) current or IDDQ. There are various causes of leakage. Gate-oxide shorts are the most frequently referenced, but others do exist. Within this section, leakages are divided into four separate mechanism categories: testing, handling, manufacturing, and design induced.

Testing-induced leakage is any leakage that results from the test method. This form of leakage typically is corrected by altering the test conditions. Examples of testing induced leakages are ATE loading of the DUT's outputs and I/Os, faulty load board, insufficient measurement settling times, or excessive parasitic capacitance.

Manufacturing-induced leakage is defined as any defect-induced leakage occurring as a consequence of the silicon fabrication or assembly operation. Elimination of this type of leakage is a primary goal of IDDQ because of its inherent reliability implications. Examples of manufacturing-induced leakages identified by IDDQ testing are gate oxide shorts, poly bridges, low transistor thresholds, p-n junction leakage, punch through, mobile ionic contamination, stacking faults, particulates, metal bridges, inner-layer oxide shorts, and defects that cause circuit delays.

Handling-induced leakages are a result of mishandling. Examples are ESD and mechanical damage. Both mechanisms are readily detectable with IDDQ after the damage occurs.

Design-induced leakages are described as any leakage that is present on every device of a particular design. This type of leakage is caused during the design, layout, or mask generation steps and, if not identified, may prevent the implementation of IDDQ testing. Examples are repeating mask defects, floating gates, incorrect alignment, parasitic devices, internal oscillators, internal resistors, analog circuitry, sense amplifiers, or redundant memory. This form of leakage can be prevented with the use of design guidelines and design rule checks.

The theory of IDDQ testing is pretty straightforward. Ideal CMOS circuits draw significant supply current, IDDQ, only when they are switching. When the circuits are not switching, the current flowing through the device is primarily

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leakage current and is usually very small. This current is called the quiescent current, or IDDQ.

The low quiescent current of CMOS devices reduces power consumption and is one of the strong points of the technology. It also makes IDDQ testing possible. Circuits that have defects, such as gate-oxide shorts, bridging defects, and open transistors, often have a higher IDDQ than defect-free circuits. By measuring the IDDQ of a CMOS IC and comparing it to the IDDQ of a known-good device, one can detect faulty devices.

Thus, IDDQ testing is used to

1. Improve the quality of low-fault coverage tests

2. Detect defects that are hard or impossible to detect using traditional voltage testing methods

However, there are a few types of defects that IDDQ testing does not detect. Certain defects cause signal delay without elevation ofIDDQ and are not classified as opens or shorts. The electrical effects of parametric defects are often sensitive to temperature, operating frequency, and power supply voltage. Boolean test methods are difficult to implement since there are many defect sites to examine, the timing effect on voltage levels can be small, and a two-vector pair is often required for defect detection. These defects, such as a change in transistor threshold (DVT), increase in via resistance (Rvia), local change in thin oxide thickness (DTox), or nicks in the transistor geometry that alter width to length ratio [D(W/L)] remain difficult defects to detect. They are an important class of defects to pursue since test escapes and reliability failures are probable. Thinned transistor oxide regions can lead to increased local charge tunneling, buildup of fixed charge, and subsequent gate-oxide rupture. A defect that locally reduces the transistor length can increase electric field intensity and may initiate short-channel carrier injection into the thin oxide.

Additionally, some obstacles to effective IDDQ testing exist. These include

Low test speed

Fixturing (IDDQ and functional test don't use the same test fixtures)

13% Yield loss due to Type I errors

IDDQ Tests corrupt Vcc because one is trying to measure current over a wide rangemany orders of magnitude

Testing Various IC Functions

The topic of electrically testing integrated circuits is very complex and cannot be treated in a broad-brush, one size fits all manner in the limited space provided here. Conferences such as the International Test Conference provide the forum for presenting the necessary detail required to do the subject justice. There are also many excellent reference books available that deal with the issues

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involved in testing (including test generation; fault simulation, coverage, and grading; and testability analysis) of specific functional IC categories such as ASICs, FPGAs, microprocessors, digital logic, and memories. I have provided a brief bibliography at the end of this chapter should the reader desire to study and pursue the subject in greater depth. However, I use memory and operational amplifier testing as practical illustrative examples of some of the issues involved with electrical testing of these functional IC categories.

Testing Memories

IC memories present a unique testing problem, since the devices are arranged in a rectilinear pattern (structure) of data storage units called cells, each of which can be changed to and retain either of two binary states: a high-level (logic 1) or a low-level (logic O) voltage. Each cell is accessed for programming or reading by energizing the proper row and column. In practice the cells are operated in groups (words), which store information in binary-coded form. The content of cell groups can represent data such as numbers, letters, or instructions for manipulating data.

There are two basic types of semiconductor memories: those that can be both programmed (data entered) and interrogated (data read), and those that are permanently or semipermanently programmed and that, during system operation, can be interrogated or read only. The first type is called read-write or random access memory (RAM), because data can be written into or read from any location in memory without scanning. Read-only memory (ROM) can also be randomly accessed, but the acronym RAM is used to denote only read-write memory. In the following discussion the RAM is used as an illustrative example of what is involved in memory testing, since it classically typifies an IC memory.

Since RAM memory cells by virtue of computer architecture and their on-chip structure must be handled in groups that are selectively accessible for reading and writing purposes, a selection and control system is built into the same chip as the cell matrix. The on-chip control circuitry configuration depends on memory cell structures, organization of the memory matrix, and the intended application. Although the control circuits (as well as the memory array and cell structure) vary from one memory type to the next, they all have several basic features: an address decoder consisting of a row decoder and a column decoder that selectively addresses (energizes) any specified word in memory, at least one chip select (CS) or chip enable (CE) input that permits the selective addressing of a particular memory chip from among several comprising a memory system, and a read-write input that permits setting up the proper condition for either reading a particular memory address or writing into the memory (the read-write control circuit disables the read circuit during a write operation and vice versa).

The cell matrix, physically surrounded and shielded by peripheral and support circuits, is the most difficult portion of the RAM to test or analyze. Cell matrices, no matter which technology is used, all have the common problem of

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dropping bits. One reason for this is that cell currents have become so small that minute variations in word line/bit line currents can disturb the cell.

The purpose or task of testing memories is to detect as many failure modes or defects as possible and practical. Most memory defects occur in clusters of memory/cells because of their orderly rectilinear layout, increasing the possibility that a particular functional pattern will detect them. (Because of this layout, a dust particle impinging on the device surface during manufacturing results in a defect encompassing many adjacent cells.) It is the test engineers' role to understand all of the possible faults for a given device type so that he can develop an effective test strategy. The following is a partial list of the failure modes found in IC memories.

1. Functional cell failures are a class of hard failures in which one or more cells of a memory are stuck at some voltage level or are completely open. These are the easiest type of failures to find.

2. Functional address failures are hard failures in which one or more cell addresses are not unique. There are multiple addresses selected usually due to row or column decoder faults or input latch faults. A good address uniqueness test will read each cell when all the other cells are in the opposite state.

3. Address propagation faults are due to the address decoder being slow and are dependent upon the state of the address decoder before switching and the state being switched to. These faults will show up as access time failures but not necessarily with all patterns used to exercise the memory.

4. Adjacent cell-disturb failures occur when there is an interaction between two or more topographically adjacent cells.

5. Row- or column-disturb failures occur when one or more cells of a row or column change state as a result of an action on some other row or column.

6. Sense line or sense amplifier faults manifest themselves in several different ways. If the sense amplifier is slow, it will cause an access time failure. Write recovery failure is the inability of a saturated sense amplifier to recover after one or more write cycles and then execute a ready cycle at minimum cycle time.

7. Refresh problems are unique to dynamic RAMs. Dynamic RAMs store a charge on a capacitor to represent a 1 or 0. Capacitors are leaky and discharge with time, losing data. The device data sheet usually requires the capacitor to be refreshed at least every 2 or 4 ms depending on the architecture. The important point to remember is that the leakage is a strong function of temperature and any leakage testing should be done at the maximum possible temperature.

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8. Data sensitivities have been found in some RAMs. They are more often found in devices where the memory array is divided into segments and the data is stored as data or complement data depending on the segment. This type of failure is difficult to test for because of the variety of configurations available and because it is rarely mentioned in data sheets.

9. Soft errors due to alpha particles occur in both static and dynamic RAMs. When an alpha particle penetrates the silicon surface, it can generate up to 1 million electron-hole pairs. A typical dynamic RAM capacitor is 35 femtofarads (fF) at roughly 5 V. Basic physics relates capacitance and the number of electrons stored on a capacitor with the equation

Q = CV NE = CV

Solving for N we get

N = CV/E

Plugging in our values:

It can easily be seen that an alpha particle can cause a cell to change state. There are several guards against alpha particles. The first is for the supplier to use package materials that generate no or low levels of alpha particles, and second to use a die coating if the cells are sensitive to soft errors. An epitaxial layer, grown during wafer fab, also provides an effective alpha-particle barrier. An equally good solution is for the user to include error code correction (ECC) techniques at the board level to guard against any single bit error.

10. Direct current parametric failures account for a large percentage of all failures. Of these, the largest number are due to electrostatic discharge (ESD).

To find these faults, the memory is exercised with a pattern. A pattern is defined as a series of reads and writes usually done at minimum times designed to exercise the device in order to expose marginalities. The pattern(s) needed to reveal the previously discussed failure modes depends on the memory to be tested, its organization, layout, and the geometry of the memory cell.

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There are many different types of test patterns that are useful for testing memories. Each has its place or use along with certain trade-offs as to the sufficiency of the test, complexity of the test, and the test time. No one functional pattern can locate all of these faults. What is required is a characterization program to find which patterns are most effective in locating specific device sensitivities. Normally it takes a combination of several test patterns to properly test a given memory. Figure 3.37 presents some of the typically encountered RAM failure categories and the patterns used to test for each.

Testing a RAM requires that the three basic tests discussed earlier, DC, AC, and functional, be performed at temperature extremes. The DC parametric tests measure such parameters as open and short circuits, leakage currents, and breakdown voltages. It is generally preferable to perform the functional or pattern testing and the AC testing simultaneously; these are the most critical and important in assessing the conformance of the RAM to its intended operation (functionality). Dynamic tests (AC) measure access, setup, hold, and cycle times.

Access time and cycle time are the two major AC performance characteristics of the semiconductor RAM. Access time is defined as the time delay at specified thresholds, from the presentation of an enable or address input pulse until the arrival of the memory data output. Cycle time is the time required to access data (read), enter data (write), and update or modify the state of a memory location. The cycle times of dynamic MOS RAMs are longer than access times

Figure 3.37
RAM patterns versus failure modes detected: (1)
Functional cell. (2) Address uniqueness. (3) Address
decoder problems. (4) Adjacent cell disturb. (5)
Row/column disturb. (6) Sense amplifier faults. (7) Sense
amplifier recovery. (8) Data sensitivity.

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because of refresh requirements; static MOS RAM cycle times are about the same as their access times.

Functionally testing RAMs involves complex sets of information that a test system must be able to generate and compare. Different sets of addresses, data, and test patterns are used to verify the operation of individual segments of the memory under test. To ensure that a RAM is completely functional, the following performance features must be checked:

Every cell of the memory must be capable of storing a 0 and a 1.

The cell-addressing circuits or decoders must correctly address every cell.

The sense amplifiers must operate correctly.

There must be no interaction between cells.

For dynamic MOS memories, the cells must be capable of storing data for a specified time without being refreshed.

Selecting the proper test sequence and optimizing AC testing patterns, although a difficult task, is necessary to achieve efficient and thorough testing.

These patterns are applied over a number of cycles that make up a functional test. In a full functional test, there are several types: write, read, read-modify-write, page mode, refresh, and so forth. Each cycle involves many activities: sending address information, various clock and enable pulses, sending data to the device pins, and reading data out from the pins.

Functional tests must be performed over a range of timing conditions, in which the cycle duration, the voltage levels, and the time of occurrence of activities are varied. These tests reveal under what conditions the RAM will operate.

Functional testing therefore demands that the tester be able to create and handle data in a highly flexible manner. Furthermore, a high degree of accuracy and repeatability must be consistently attained.

Testing Operational Amplifiers

Analog, or linear, ICs are those devices that operate over a continuous and broad spectrum of power-supply voltages and currents and input voltages. They include such diverse IC families as operational amplifiers, voltage regulators, voltage comparators, voltage references, instrumentation amplifiers, analog switches, sample and hold circuits, D to A and A to D converters, timers, TV and audio circuits, speech synthesis circuits, and telecommunication circuits.

Linear ICs bear little or no resemblence to their digital IC counterparts in terms of functionality, complexity, and sensitivity. The simplest operational amplifier requires 2030 totally unrelated tests, and measurements of offset current in the picoampere range and of gain greater than 10⁶. An even larger problem is that the term linear IC is much less definitive than digital IC. Digital IC testing usually involves the same family of measurementhigh-state and low-state thresholds, propagation delay, and the like. But the tests necessary

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for one type of linear device (e.g., operational amplifier) may have little or no relation to the tests for another (FM stereo demodulator).

For a typical linear IC, the operational amplifier, the following DC parameters are normally measured:

Input offset voltage at zero common-mode voltage

Input offset current at zero common-mode voltage

Input bias current at zero common-mode voltage

Common-mode rejection ratio

Supply-voltage rejection ratio

Positive gain and positive-output swing

Negative gain and negative-output swing

Figures 3.38 through 3.40 show the wide range of parametric values for input offset voltage (Vos), input bias current (Ibias), and noise figure, respectively. A supplier must have the capability to test each of these parameters over the full range indicated, since all are being simultaneously manufactured. These figures also show the improvement that has occurred in the past 20 years for each of these parameters. Also, note that linear ICs such as the (LM108 operational amplifier and LM339 quad comparator have been around since 1970 and will continue to be produced through the year 2000. But die restepping and shrink and process improvements will continue to improve both yield and performance.

Even with computer-driven testers, the variations in test requirements for linear ICs are so great that much of the test programming must take the form of

Figure 3.38
Range of Vos values for available operational
amplifiers.

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Figure 3.39
Range of Ibias values for available operational
amplifiers.

performance boards, which are special-purpose plug-in fixtures incorporating the output loads and circuits needed to test a given family of devices. Very often, the performance board must be fine tuned either automatically by the computer or manually for each device to match the load and other situations found in actual use. The number and complexity of parameters that must be measured at one time or another are usually well beyond the reach of a hardware-only test system

Figure 3.40
Range of noise figure for available operational
amplifiers.

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and require more dedicated software than is normally associated with other device categories.

The dynamic parameters of a linear device define its high-frequency performance. Only recently has the need for high-speed AC testing been understood for establishing parameters such as total harmonic distortion, channel separation, cross talk, gain bandwidth product, slew rate, response time, and phase margin. At one time, the amount of distortion, for example, was estimated during manufacture of the device by comparing high and low DC parameters. The separation would then give a rough estimate of the distortion to be expected.

The problem with this technique is that if either the high or low value is a few percentage points out of tolerance, distortion in the finished device may be greatly amplified. Then, too, a great many DC tests must be made to verify the same parameters that a few AC tests measure, so test time using all DC tests is much longer than that using both DC and AC tests.

Problems often occur when testing linear ICs, for no apparent reason. In reality, the inherent nature of these devices requires that strict attention be paid to many details that are not important or significant for the digital IC. The testing of the operational amplifier will be used as a representative example of a typical linear IC in the following discussion. Similarly, there are idiosyncracies peculiar to voltage regulators, voltage comparators, digital-to-analog (D to A) and A to D converters, timers, and the like that must be addressed in testing these devices.

Many problems incurred in testing operational amplifiers are due to the test circuit or fixture that is fabricated for the testing activity and its effect on the operational amplifier it is to test. Figure 3.41 is a schematic diagram of a typical operational amplifier test circuit. To prevent test circuit-related problems the following precautions should be observed.

1. Check for oscillation of the test loop. Incorrect compensation of the buffer amplifier will cause oscillations, which show up as excessive offsets, low gain or high supply current. A capacitor Cc in Fig. 3.41 will normally stabilize the loop.

2. When checking input voltage, take care not to cause the inputs of the operational amplifier to break down, as this will degrade input characteristics. This is particularly important when testing devices that have low input breakdown voltages of 6 V.

There are two methods of measuring maximum input voltage. The first makes use of a current that is forced through the inputs. The subsequent breakdown voltage is measured. This method, however, is not recommended since it causes reverse baseemitter breakdown of the input transistors and degrades input performance.

With the second method, a voltage is applied to the inputs and the

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Figure 3.41
Complete operational amplifier testing for DC characteristics can be
achieved with this test circuit.

resultant current is measured. This method is a much safer one in that it does not degrade the operational amplifier unless breakdown occurs.

3. Check the tolerances of the circuit components. Incorrect tolerances of the circuit resistors can produce a significant measurement error. For example, if the common-mode rejection ratio (CMRR) is being tested by varying the input voltage as shown in Fig. 3.42, resistor matching must be such that the error (twice the resistor match) is small compared to the measured value. If CMRR is to be measured to 80 dB, the resistor match should be at least 100 dB or 1 part in 10⁵, a 0.001% match.

When using source resistors, Rs, they must also be matched to minimize the error due to bias current change with input voltage. This is also necessary when using the circuit in Fig. 3.41. During the era of the 709 operational amplifier, a resistor match of 0.02% was sufficient. For modern operational amplifiers, such a match of 2 parts in 10⁴ is many times the magnitude of the error that is being measured. This will either add or subtract from the CMR error of the operational amplifier.

4. Minimize thermal effects when performing DC tests. Thermal effects

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Figure 3.42
Resistor tolerances can produce significant errors in the
measurement of an operational amplifier's common-mode rejection
ratio (CMRR). The value of the source resistors (Rs) depends on
the type of amplifier under test.

are particularly noticeable when making gain measurements, especially where negative or infinite gains are often measured. Thermal effects can be minimized by pulse testing with a very short duty cycle of less than 5%. In this way the instantaneous and time-dependent effects can be observed. With these tests, and even with tests where the junction temperature of the device varies only slightly, the difference between the instantaneous and the final values is dependent on the loop response time. For relatively slow devices such as the 725, the loop response combined with thermal response may be greater than 30 sec for certain tests.

5. Input and output voltages must not exceed either of the supply voltages during usage or testing. Transients that occur when the power supply is turned on and off often result in a higher input voltage than supply voltage. This condition can cause a catastrophic operational amplifier failure. The negative supply voltage or ground should always be applied first or simultaneously with the positive supply to avoid latch-up or device destruction. Some operational amplifiers can be destroyed when an input voltage is applied to the operational amplifier and both supplies are turned off. This turns on the collector-base diode of the input transistors and grounds the positive power supply while it is off.

Device inputs can be degraded if a DC voltage is placed on the

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output of an integrator or on the input of a sample and hold circuit and the positive supply is again off. If a large capacitor is used, the inputs may be destroyed.

A high-voltage diode inserted in each power supply lead will prevent failures caused by transients and power supply reversals. Additionally, a resistor inserted in each input will limit the input current caused by high transient voltages (the zener diode protects against overvoltage). Both of these configurations are shown in Fig. 3.43.

6. Test sequence is important for measurement accuracy and reproducability: specifically, the manner and order in which input offset current, input bias current, and short-circuit current are measured and the effect of these measurements on chip temperature (heating). Several comments are now made to set the stage for the following discussion.

First, a comment on the relationship of operational amplifier currents with temperature. For a field-effect transistor (FET), the input current increases with temperature; but for a bipolar transistor, the input current decreases with increasing temperature. Second, most ATE measurements are made as fast as possible, normally on a pulse basis, to minimize test costs. As such, the chip temperature during the measurement has never stabilized, and different readings could occur if the part was tested several times due to the different test times used. In actual use the operational amplifier once turned on stays on. It is not used in a pulse mode. For precision operational amplifiers the chip temperature must stabilize before the measurements are made.

Figure 3.43
To protect an operational amplifier from power
supply transients and high input voltages, a pair of
diodes and two resistors are used.

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If short-circuit current is measured before the input offset or input bias currents, the test results will be different than if performed in the reverse order due to the longer duration of the short-circuit test and resultant higher chip temperature. The data sheet specifies that these measurements be made at an ambient temperature of 25°C, for example, but it says nothing about junction temperature.

Realistically, then, input bias current and input offset voltage and current should be measured first with the device being allowed to stabilize. The test for output short-circuit current should be performed last. However, the input offset voltage should be measured again after the short-circuit current test to ensure that the device has not failed.

Electrical testing takes place after the IC has been packaged and must be comprehensive to

Ensure that the part functions as intended

Remove manufacturing defects

Determine the operating boundaries and margins (characterization)

These items are addressed next.

The Design Verification (Characterization) Test

When an IC is designed, a great many different disciplines are involved: solid-state chemistry and physics, semiconductor materials science, circuit design (both analog and digital), on-chip interconnection techniques, and computer/process modeling, simulation, and verification techniques. Other areas of knowledge such as the selection of materials for the package, various methods used for connecting the chip to the outside world, heat transfer, and package design are also required.

During the circuit design and fabrication of an IC, design (electrical and thermal), process, reliability, and test engineers will perform a very large number of tests including circuit simulation and functional verification, fault simulation and verification, timing analysis, resistance measurements, impedance measurements, threshold voltage measurements, leakage current measurements, propagation delay, and switching measurements. The number of tests required during design verification is staggering.

After a supplier has an IC design at a predetermined level of completion, with several prototype fabrication runs completed, the supplier will perform a comprehensive design verification or characterization test [4]. The characterization test provides device process data that allows the supplier to verify process parameters; to see how well the resultant circuit implementation meets the design objectives with variations in power supply levels, test patterns, external noise sources, operating temperatures, timing conditions, and microprocessor instruction sequence and instruction speed; to establish data sheet specification limits;

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and to develop a meaningful production test program for the particular device type.

Electrical characterization testing can be defined as the thorough and exhaustive testing of a sample of a given device type through all practical combinations of supply voltages, temperatures, timing conditions, parametric variations, and the like, to find its response under these conditions and to find the limits within which the device remains functional (i.e., define the operating limits). Characterization testing includes stringent functional testing using patterns or truth tables and timing and parametric variations under temperature extremes. Worst-case patterns with supply and timing variations are applied to the device to expose it to as many failure modes as is practical, and determine its performance under the most severe conditions.

For digital circuits, extensive DC tests are performed, including logic levels, leakage and quiescent currents, threshold levels, and driving capability to test propagation delays from various inputs to outputs. These tests are conducted to verify that the internal gates switch at the proper rates, as well as to determine if any race conditions in the logic exist. Additionally, multiple output switching and ground-bounce tests are performed to verify functional application compliance.

These tests include an effort to determine if decoding and encoding networks (and other combinational logic) function as required. Since the logic design has been verified by computer simulation during the design process, this testing of timing and timing analysis switching parameters verifies the simulation results. This testing also includes extensive truth-table testing to determine if the device operates properly in all the necessary states. In cases such as microprocessors, it is very important to not only determine that all instructions operate as intended but to ensure that large numbers of various sequences of instructions operate properly. Simply stated, design verification testing makes a major effort toward determining if any patterns are sequence sensitive.

Another less obvious test requirement is the timing of the input and output functions. Timing between synchronous input functions (such as INTERRUPT, RESET, HOLD, etc.) is especially difficult. Design verification and characterization will also include tests to measure critical AC parametric characteristics.

During testing, all parameters are held constant except one (a simplified or restricted design of experiments), which is varied (or iterated) until that parameter results in a device failure (nonfunctionality). The last valid operating point is then noted and testing of another variable is begun. This process is repeated until all parameters are tested to failure for the entire sample population. The number of tests involved in such a characterization runs into the millions and results in very long test times.

Thus, characterization tests are used to define a generic device's operating

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region and boundaries. They are also used to define and prove the effectiveness of developed test patterns, worst-case test conditions, and test procedures for parametric measurements. Some characterization test programs are combined with reliability test programs to ensure that the product will have a high probability of working properly for the customer.

It should be noted that each generic part type is normally characterized by the design engineer during prototype (pilot) fabrication. From this the data sheet and test programs are written. Once the product is acceptable to the design engineer, it is then transferred to production. In the production area, wafer fabrication processes are constantly being adjusted to the product design to increase yield and thus revenue per wafer. However, this act causes a shift in the target specifications for the actual parameters and thus a shift in the distribution of these parameters as well. Thus, the original target specifications, distribution, and test programs may no longer be valid and test escapes or errors occur. As such, periodic recharacterization tests should be conducted throughout the life of a given product to verify the original characterization test results and institute whatever specification changes need to be made if the results differ.

Final Electrical Testing

The last step in the manufacture of an integrated circuit is the final electrical test, which, as was mentioned before, is performed to

1. Identify and reduce outgoing defects

2. Identify manufacturing process deviations

3. Verify conformance to specification limits

This final test includes a combination of DC and AC measurements and functional performance of the complete circuit, and its nature depends upon the type of circuit, the current prevalent market conditions (market prices), specific device peculiarities or weaknesses, and manufacturing cost. The amount of testing performed on the product also depends on the maturity of that product. A high-volume mature product has been refined (its die size optimized, its process improved, and its test vector set refined and reduced) to yield the most net dice per wafer. Throughout the life cycle of a given IC, as its manufacturing process is continuously refined and improved, so too is the test vector set simplified and focused to contain only those test vectors that identify device sensitivities. Thus, the supplier has had time to develop refined functional tests for older products, but more comprehensive tests are required

1. For a new product that has just been introduced

2. For a new product in low-volume manufacturing

3. For a product that is extremely complex, especially if it is relatively new and/or in low-volume production

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Thus, the final test program is usually a compromise optimized for that particular supplier's design and unique processing features and yet constrained by the need to compete in the marketplace at market price while manufacturing the given circuit at reasonable cost and making a profit on its sale.

However, final test is changing significantly. With the ability to perform comprehensive, highly guard-banded, and accurate parametric (both DC and AC) and functional tests at wafer probe, the purpose of final electrical test is changing to a check for assembly-related defects using low-cost testers. The real value added for electrical testing has moved forward in the manufacturing process to just prior to putting the die in an expensive package, at wafer probe.

Yield Considerations

As has been shown, there are many sequential steps in the process of fabricating an integrated circuit. In most of these steps, some imperfections are fabricated that produce loss. For example, yield loss can occur at each of the oxide-removal and diffusion steps due to a variety of causes: imperfections in the original silicon, incomplete cleaning of the wafer, uneven photoresist application and removal, the presence of dust particles and unwanted impurities contaminating the diffused areas, incomplete control over the etching processes, and mechanical breakage of the wafers, for example. Although the loss of each operation is small, only 1 or 2% or less, there are so many sequential operations that the cumulative good yield up to the end of scribing the wafer into chips and sorting can vary between 10 and 80% depending on the circuit function and complexity. After this, units may be damaged during assembly, and there will be a further loss at the final test due to units not meeting specification; the overall yield can be as low as 5% or perhaps as high as 70%, again depending on the type of circuit. In other words, about 60% of the processed ICs are defective. Figure 3.44 depicts this graphically.

Yield is a complex issue. Yield is related to the defect density (number of defects or imperfections in a given space or area) and the die size. For a constant defect density, as the die size increases, the yield decreases (see Fig. 3.45). For a constant die size, decreasing the defect density dramatically improves the yield, as shown by Murphy's model in Fig. 3.46. In today's environment the number of process steps is increasing (this increases the potential for a greater incidence of imperfections or defects) and the die size is increasing. Thus the incidence of imperfections or defects must be greatly reduced in order to increase or even maintain a given yield.

Process monitors and test structures (discussed in Chapter 4) are fabricated on chip and used to isolate defects, institute corrective action, and drive continuous improvement at each critical process step, thereby increasing yield at that step so that cumulative yield is high and first-time functional silicon as well as profitability will be assured.

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Figure 3.44
Graphical representation of yield loss. (Courtesy of ICE Corp.,
STATUS 1994.)

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Figure 3.45
Effect of die size on yield. (Courtesy of ICE Corp., STATUS 1994.)

Figure 3.46
Murphy's probe yield model (as a function of defects per square centimeter).

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References

1. E. R. Hnatek, A User's Handbook of Integrated Circuits, John Wiley & Sons, New York, 1973.

2. C. A. Nicolaou, Plastic package failure modes, Surface Mount Technol. November 1993.

3. J. L. Freeman et al., Direct electro-optic sampling of analog and digital GaAs integrated circuits, GaAs IC Symposium Proceedings, 1985.

4. E. R. Hnatek, Device characterizationA practical approach, Proceedings of the Technical Conference, 2nd Annual American Society of Test Engineers Conference, November 1315, 1984.

Selected Readings

1. M. Abramovici, et al., Digital System Testing and Testable Design, Computer Science Press, 1990.

2. H. Blecker and P. van den Eijnden, Boundary-Scan TestA Practical Approach, Kluwer Academic Press, 1992.

3. R. J. Feugate and J. M. McIntyre, Introduction to VLSI Testing, Prentice-Hall, Englewood Cliffs, NJ, 1988.

4. J. Huber and M. Rosneck, Successful ASIC Design the First Time Through, Van Nostrand Reinhold, 1991.

5. R. W. Liu, Testing and Diagnosis of Analog Circuits and Systems, Van Nostrand Reinhold, 1991.

6. A. Miczo, Digital Logic Testing and Simulation, John Wiley and Sons, New York, 1986.

7. W. Needham, Designer's Guide to Testable ASIC Devices, Van Nostrand Reinhold, 1991.

8. K. P. Parker, The Boundary-Scan Handbook, Kluwer Academic Press, 1992.

9. A. K. Stevens, Introduction to Component Testing, Addison-Wesley, Reading, MA, 1986.

10. J. Turino, Design for Test, Van Nostrand Reinhold, 1990.

11. A. Van de Goor, Testing Semiconductor Memories, Theory and Practice, John Wiley & Sons, New York, 1990.

12. F. C. Wang, Digital Circuit Testing, A Guide to DFT and Other Technologies, Academic Press, Orlando, FL, 1991.

13. E. R. Hnatek, Digital Integrated Circuit Testing from a Quality Perspective, Van Nostrand Reinhold, 1993.

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4
In-Line Process Monitors and Test Structures

Traditional reliability test programs estimate the lifetime of an IC by means of operating life tests. However, there are some inherent problems with this when dealing with technologies that are currently in production. Specifically, traditional reliability tests

Are performed at the end of the manufacturing line. Thus, a significant amount of material can be affected by a process variable drifting out of specification before it is possible to detect it.

By their nature have a lack of real-time feedback to initiate process and/or design changes.

Do not provide acceleration factors for a specific failure mechanism.

Are not run long enough to find the wear-out time of the device.

As a result of these shortcomings, testing has moved upstream in the IC manufacturing cycle from an end-of-the-line operation to an in-process monitor via test structures and process monitors. Testing, using statistical tools, is conducted during wafer fabrication so that a real-time indication of the quality of the critical process steps can be ascertained and appropriate decisions made.

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Some of the upstream wafer fabrication issues that affect finished IC quality and reliability include.

1. Manufacturing process capability. A new process must guarantee sufficient margin to both specification limits and the likelihood of any reliability excursions.

2. Manufacturing control. To achieve low failure rates, there is a need to address some of the nontechnical procedural issues. These may not be obvious from a technical perspective, but can have a significant impact on reliability.

3. Assessment of process interactions. One step in a process may be an amplifier of a previously unobserved defect from a previous process step. The end result may be a degradation in the reliability of the final product if the interactions are not well characterized.

4. Process monitoring. It is critical to drive all monitors to as close to real-time monitors as possible. Real-time monitors, such as in-line particle monitoring, are preferential to end-of-line (EOL) or unit-level evaluations. Short-loop (reduced-process) monitors examine specific areas of the process.

Semiconductor manufacturing uses well-established statistical process control (SPC) techniques to increase device fabrication yield. Conventional fabrication relies on controlling a limited set of critical equipment parameters (e.g., process pressure, gas flow rates, substrate temperature, rf power, etc.), but significant wafer and process state parameters are typically not monitored in real time or in situ. These parameters include those associated with deposited films (e.g., film thickness and composition), lithography (e.g., line-width control), etch processes (e.g., uniformity, selectivity, line-width control), as well as hardware issues (e.g., cleaning).

Significant advantages can be obtained from sensor-based IC manufacturing processes. In situ sensors enable a higher degree of hardware control, an increased level of hardware and process diagnostics, tighter control over individual process steps, and automatic run-to-run control of wafer parameters. See Ref. 1 for more details concerning in situ hardware sensors.

Furthermore, the development of VLSI circuits and commensurate VLSI processing, the use of large-size wafers (6, 8, and 12 in.), and the drive toward higher packing density, higher speed, smaller geometry ICS are (1) creating a need for semiconductor wafers with a perfect surface, (2) placing greater emphasis on in-line process monitors to measure, verify, feedback, and correct each process step in real time, and (3) driving process monitors farther up the process cycle into the raw material supply cycle.

For low operating voltages and/or even smaller submicrometer geometries, the interactions between process steps, device parameters, and the finished IC's

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behavior are magnified. Thus the need for extremely tight process control by means of process monitors is greater.

A process control monitor is defined as a monitor or test that detects when a process variable drifts out of preestablished specification limits using statistical tools. It thus provides rapid feedback to prevent manufacturing discrepant material. The purposes of process control (improvement) monitors are to guarantee the stability of every lot and to ensure that continuous improvement is occurring.

Process control monitors include both wafer fabrication and assembly-critical parameters. Typical CMOS wafer fabrication process parameters are listed in Table 4.1. A similar list of critical bipolar wafer fabrication parameters can be created. Typical assembly process parameters that must be controlled are listed in Table 4.2.

Table 4.1 Typical CMOS Wafer Fabrication Process Parameters

Process

Critical Parameters

All contacts
Step coverage

Field oxidation
Oxide thickness

Gate oxidation (see Fig. 4.14)
Oxide thickness

Poly deposition
Film thickness

Silicide deposition
Film thickness

Phosphorus diffusion
Sheet resistance

Polysilicide etch
Linewidth (CD)

Glass deposition
Dopant concentration

Metal 1 and barrier material depositiona

Film thickness

Metal 1 etcha
Linewidth (CD)

Intermetal dielectrica
Film thickness

Metal 2 and barrier material deposition

Film thickness

Metal 2 etch
Linewidth (CD)

Nitride deposition
Film thickness

Particle monitor
Density

CV plot
Graph, histogram

Electromigration (see Fig. 4.10)

Wafer level reliability test (SWEAT)

Each mask level
Defect density

Pinholes
Substrate current

aApplicable for each layer of metallization when there is more than one layer.

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Table 4.2 Assembly Process Parameters

Process

Parameters

Die attach
Die stud pull

Wire bond
Bond pull

Encapsulation
Molding temperature

Solder plating

Plating composition and thickness

Trim and form
Coplanarity

A note of caution is warranted: Test structures and process monitors must be sensitive enough to detect when a process variable drifts out of specification. Electromigration is used as an illustrative example. Electromigration time-to-fail is a composite of many process variables, as shown in Fig. 4.1. Each process variable in turn may be (is) a function of many other input variables to the process, as shown in the exploded view of metal quality in Fig. 4.2. Some of these input variables could be a function of even more input process variables.

As can be seen from Figs. 4.1 and 4.2, electromigration is a function of several hundred input variables to the manufacturing process, all of which need to be controlled. A drift in any one of these process variables will have an effect on electromigration performance.

In summation, one must ask: Can an electromigration test at the output of the fishbone process be sensitive enough to detect if any one or more of the input process variables drift out of specification? The answer is no. When there are hundreds of process variables, the only way an output electromigration test can detect drift in one variable is if it is so far out of spec that it swamps out the effect of all other input variablesa major disaster in the manufacturing line. Therefore, each process step must be controlled by itself.

Another example is presented that measures (monitors) oxide-nitride-oxide thickness, quartz tube cleanliness over time, and breakdown voltage between poly 1 and poly 2 layers (Figs. 4.3, 4.4, and 4.5, respectively) as they relate to EPROM DC erase fallout. This is important because in EPROMs, charge loss can occur in several ways, one being DC erase or word line stress. DC erase is used to maintain the health of the process and drive process variation reduction.

Next, an on-line die/wafer inspection (OLDI) example is presented, the purpose of which is to monitor process defect density level and generate an alert when necessary. An EPROM fabricated on 6-in. wafers using a double Poly 2-mm CMOS process was chosen as the test vehicle for the following reasons:

Easy, fast, and accurate defect detection

Good correlation and failure analysis using bit mapping

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Figure 4.1
Fishbone diagram showing input variables that affect electromigration time to fail.

Figure 4.2
Fishbone diagram showing input variables that affect metal quality.

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Figure 4.3
Direct current erase fallout versus O-N-O thickness.

Figure 4.4
Impact of quartz cleanliness on DC erase fallout.

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Figure 4.5
Short-loop monitor data correlating BVPPREOX (from monitor) to DC erase
(on product). BVPPREOX: breakdown voltage between poly 1 and poly 2 for
an edge-intensive capacitor formed during the etch process.

The reason that inspection was deemed important is that 41% of the yield variance is attributable to the variance of observed visual defects. It was decided to monitor the following four critical process steps: composite, Poly I, Poly II, and metal.

Each critical process step was inspected by production personnel. This was followed by on-line die inspection at 10X objective magnification using dark-field mode. The details for this methodology are

Any defects appearing in a simple microscope field of view are counted as a single defect.

All defects that affect the inspected layer are recorded and counted according to predefined categories and their locations are identified.

The smallest defect counted is about 0.5 mm.

Each process step (layer) has its own control limits, which act as the warning trigger.

Average inspection time per wafer is 6 min.

Figure 4.6 shows a control chart of the defect density occurring in the Poly II layer. Each of the four critical process steps are monitored by a specific control

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Figure 4.6
Each of the layers has its own control limit, which acts as the warning trigger. Shown is the current control limit for the
Poly II layer.

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chart. Figure 4.7 shows a distribution of the total weekly defect density. The conclusion from this example is that on-line die wafer inspection is an accurate, sensitive, and valuable tool in monitoring, detecting, and correcting out-of-control critical wafer process situations.

As a last example, Figure 4.8 shows control charts that are used to monitor tungsten film deposition uniformity as measured by sheet resistance for consecutive wafer fabrication runs as another illustration of the use of process monitors. These control charts verify the stability of the WF₆ gas delivery system.

Integrated circuit suppliers use various test structures (either dedicated drop-in or structures fabricated in the kerf) to demonstrate process control and parametric stability and ensure long-term reliability. This is accomplished by measuring initial test structure parameters to detect potential reliability defects such as

Metal stripe defects

Metal interlevel connection defects

Metal intralevel short defects

Interlevel metal short defects

Gate dielectric defects

Polysilicon short defects

Contact or interconnection step coverage defects

Contact Al/Si interdiffusion defects

These defects are introduced by random contamination, wafer handling, or excessive process or material variation. The gathered data are used to monitor and adjust each process step, as appropriate, as well as the interaction occurring between process steps, to drive continuous improvement and increase yields.

A listing of typical test structures follows:

a. n-Channel device (minimum geometry)

b. p-Channel device (minimum geometry)

c. n-Channel device (large geometry) (see Fig. 4.12)

d. p-Channel device (large geometry)

e. Sheet resistance measurement structure

f. Metal step coverage structure

g. Field device(s)

h. Intermetal oxide integrity structure (see Fig. 4.13)

i. Contact chains (must be of sufficient length to be representative of the contact resistance)

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Figure 4.7
Sensitivity of the OLDI as a monitoring tool, where an increase in the observed
defect was detected after a 2-week holiday shutdown.

Figure 4.8
Control plots of as-deposited tungsten sheet resistance uniformity for a sequence of
wafers.

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Table 4.3 Test Structures and Measured Parameters

Typical structures

Parameters measured

Gate-oxide capacitor, trench capacitors

Capactitance, oxide breakdown

Capacitor arrays
Oxide integrity

Assorted contact chains
Contact resistance

Assorted Van der Pauws
Resistance

Assorted p and n and MOS FET geometries

Transistor and diode parameters, leakage I

Assorted serpentine structures over steps

Continuity/Bridging

Metal to poly (where acceptable) (see Fig. 4.15)

Metal 1 to metal 2 (where applicable), via resistance

Gated inverter chain(s) for AC measurements

Metal to diffusion (where applicable)

Within these test structures, the interconnection structures are critical and typically consist of

Interdigitated metal serpentines (for metal opens and metal shorts)

Metal stud or via chains (for interlevel connections)

Interlevel crossover patterns (for interlevel shorts)

Table 4.3 takes some of these test structures and lists the measured parameters, and Figs. 4.9 through 4.15 provide detailed views of the physical construction of these test structures.

Other test structures check for pinholes/photolithography errors, ion implant errors, plasma etch errors, EOS/ESD events, radiation events, and particulate contamination. The number and types of test structures and process monitors used vary with the maturity of a given process. According to IBM Fishkill (author's personal communication with IBM personnel), each of their products has 10% of its wafer area dedicated to drop-in test sites when it is introduced into manufacturing. As the technology matures, the test site wafer area is reduced to 5%. Test sites on all wafers are tested during processing.

Test structures and process monitors are used to monitor assembly processes as well as wafer fabrication processes. Figure 4.16 shows a drop-in die containing numerous assembly structures used to monitor various portions of the typical assembly process. Figures 4.17 through 4.20 show typical assembly process monitors for die attach and wire bond operations. Figures 4.17 and 4.18 are control charts for two different die attach operations. Notice the notations where changes to the process occurred, such as new operator and epoxy problem.

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Figure 4.9
Typical test structures: (a) metal test structure; (b) thin-oxide test structure; (c) hot carrier test structure; (d) wafer-level
contamination test structure.

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Figure 4.10
Various metallization test structures for evaluating and checking for
electromigration. For (d), pattern is repeated for various line widths and spaces, as
required by circuit design.

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Figure 4.11
Test structure for metal shorts and voids.

Figure 4.12
MOS transistors, n channel: variable W, variable L.

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Figure 4.13
Oxide integrity/step coverage.

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Figure 4.14
Gate dielectric integrity array. The number of identical capacitor elements for each
subarray is listed at the right. Area of capacitor is scaled to circuit feature size, i.e.,
2 mm × 2 mm or 1 mm × 1 mm.

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Figure 4.15
Electrical alignment resistor (metal Poly I) contact chain.

Figure 4.16
Assembly test structures.

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Figure 4.17
and R control charts for die attach operation.

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Figure 4.18
and R control charts for another die attach operation.

Figure 4.19
Example of run chart of minimum wire bond pull strength.

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Figure 4.20
Example of run chart of average wire bond pull strength.

It is important that such notations be placed on control charts and run charts to aid in understanding all of the steps and changes that occur in a given process and the reasons for such changes. They are used to get to the true root cause of a problem, providing permanent corrective action and leading to continuous improvement. Figures 4.19 and 4.20 are run charts of minimum and average wire bond pull strength, respectively. Notice the effect of introducing a second source wire supplier in Fig. 4.20.

The data gathered from the various process monitors and test structures are analyzed and displayed using statistical tools such as histograms/bar charts, run charts, pareto charts and control charts. Examples of these are shown in Fig. 4.21 through 4.26. Figures 4.21 and 4.22 display histograms of channel length for n- and p-channel transistors, respectively. Figures 4.23 and 4.24 are control charts for the same parameters, respectively, showing good process stability. Figure 4.25 shows a monthly distribution of p-channel substrate current (used as a hot carrier indicator) indicating good process stability; Fig. 4.26 shows a monthly distribution of time-dependent dielectric breakdown (TDDB) defect density. Figure 4.26 shows a widely varying defect distribution. Typical assembly data were already presented in Fig. 4.17 through 4.20.

It is upon graphical data such as this that appropriate action is taken in as near to real time as possible to ensure stability and to drive continuous improvement.

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Figure 4.21
Process monitor for electrical channel length, n-channel transistor.

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Figure 4.22
Process monitor for electrical channel length, p-channel transistor.

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Figure 4.23
Process control chart for electrical channel length, n-channel transistor.

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Figure 4.24
Process control chart for electrical channel length, p-channel transistor.

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Figure 4.25
Hot carrier indicator: p-channel transistor subthreshold current.

Figure 4.26
TDDB defect density.

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Reference

1. G. G. Barna et al. Sensor needs for IC manufacturing. Solid State Technology. April 1994.

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PART II
IMPACT OF NEW TECHNOLOGIES

The semiconductor industry has been an explosive growth in productivity during the last decade as significant strides in productivity and performance improvements have been accomplished by shrinking the device feature sizes and through circuit innovations.

The primary technology parameters affecting productivity then and now are

1. Circuit and CAD innovations

2. Improvements and innovations in lithography

3. Chip size (packing density)

4. Process innovation and new materials

Ongoing research into new processes, materials, and circuit innovations as well as the implementation of these technological enhancements to achieve smaller geometry devices is occurring at a rapid and frenzied pace (see Fig. II. 1). All of these tend to significantly complicate the IC manufacturing process and

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Figure II.1
Dramatic reduction in design rules for ICs has taken place since 1960.

thus directly affect finished product quality. For example, in 1970 a 10-step fabrication process was considered complex. Today, typical VLSI processes have nearly 100 fabrication steps!

Leading-edge technology innovations are implemented for memories (RAM, EPROM, Flash) as process drivers to maximize asset utilization and reduce costs due to their high-volume run rates and for application-specific ICs (ASICs) as technology drivers to reduce cycle time.

Once these innovations are refined, they filter downward to all areas involving mature and more profitable products that may be restructured, redesigned, or restepped for larger wafer sizesor a combination of all of thesein order to decrease die size, obtain more dice per wafer, decrease the cost per die, and increase profits and affect inherent device quality levels.

In this section only a brief discussion will be presented of some of the more pervasive technological innovations, since such a detailed discussion could easily fill one or more volumes. Furthermore, these will become mainstream and then dated or outmoded as technological innovation continues.

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5
Circuit Design Trends

The primary design trends are concerned with packing the greatest amount of circuitry in the smallest possible area and reducing parasitic circuit effects. The dynamic RAM or DRAM will be used as an illustrative example of future technological projections. Specifically, the International Solid State Circuits Conference (ISSCC) technical papers from 1983 and 1992 will be used for comparative purposes and upon which to draw conclusions and future projections. It should be realized that there is a time lag of 3 to 6 years from the time a DRAM at a specific level of integration is formally presented at ISSCC to when products of that level of integration are available at a production rate of 10 million units per month or greater (Fig. 5.1). It is anticipated that this time delay will increase for future generations of DRAMs.

What the Dram Future Promises

Figure 5.2 is a comparison of six primary DRAM attributes for 1983, 1993, and extrapolated to 2003. Memory density has grown by 1000 times from 1983 to 1993 and is expected to grow by the same factor by 2003. A one-billion-transistor

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Figure 5.1
DRAM time to production.

Figure 5.2
Comparison of DRAM characteristics for 1983, 1993, and extrapolated for 2003.
(Courtesy of ICE Corp., STATUS 1994.)

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chip is projected to occur by the year 2000, with the possibility of a one-trillion-transistor device by the year 2020!

Cell size may be the most difficult attribute of the extrapolated 2003 DRAM to achieve. The problem with continuing to shrink the DRAM cell size rests not so much with the transistor but with the associated capacitor in the DRAM cell. Already DRAM manufacturers are struggling with the shape and type of material to use for the cell capacitor. It has proven very difficult to satisfy the need for a smaller cell size (and smaller capacitor size) while at the same time ensuring that there is enough charge in the capacitor structure to prevent a potentially disastrous increase in soft-error defects. Figure 5.3 presents several capacitor structure configurations and innovations aimed at improving DRAM density while maintaining accepted DRAM performance criteria.

Figure 5.4 compares described DRAM die sizes. The 1993 ISSCC 256M DRAM die sizes ranged from 516K sq. mils to 740K sq. mils. Because DRAMs are rectangular in shape (typically not square), the longest side of the largest DRAM chip at ISSCC 1993 was 1.3 in.!

For 2003, the 6.58M sq. mils device, if square, would be 2.6 in. on a side. Given the typical 2.1 aspect ratio of the DRAM die, the 2003 DRAM die size would be about 3.6 in. by 1.8 in. (Fig. 5.4), approaching what is called wafer-scale integration.

By 2003 the IC industry may be forced into some type of three-dimensional (stacking one or more transistors on top of each other) technology in an attempt to keep die size manageable. However, three-dimensional technology will come with its own set of constraints and problems that one cannot even fully imagine at this time. Three-dimensional technology is discussed later in this chapter in greater depth.

The rapid migration to lower supply voltage has been well documented. As was shown in Fig. 5.2, the very small feature sizes of the 256M DRAMs described at the 1993 ISSCC require even lower voltage operating levels for the internal circuitry (1.52.0 V) than for the overall operating voltage level (3.3 V).

It is fairly easy to visualize 2.0-V supply voltages being converted to 1.0 or 1.5 V internally for the 2003 DRAM. However, the industry will have a difficult time significantly advancing performance while at the same time lowering voltage levels.

Using a device voltage of 1.0 V, a feasible minimum effective channel length for a silicon-based MOSFET is between 0.10 and 0.05 mm.

This reference to silicon MOSFETs brings up the question, will silicon still be used for fabricating gigabit-scale integration (GSI > 1 billion on-chip transistors) DRAMs? If history is any indicator, the IC industry will not move to new materials or structures unless it is absolutely necessary. Thus, silicon-based MOSFET-type ICs can be expected to be the mainstream technology for at least the next 10 years.

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Figure 5.3
Stacked capacitor structures: (1) vertical fin structures; (2) complex structures;
(3) rough-stacked capacitor; (4) comparison of capacitor structures.

Although GaAs electron mobility is almost six times that of silicon at low field strengths, it is largely inconsequential at transistor feature sizes below 0.25 m because operating field strengths are well above the level needed for carrier velocity saturation (Fig. 5.5). And CMOS will still be the technology utilized to realize the GSI DRAMs of 2003.

Even with dramatically smaller feature sizes, the 1993 DRAM was only

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Figure 5.4
ISSCC-described DRAM die sizes. (Courtesy of ICE Corp., STATUS 1994.)

Figure 5.5
GaAs versus silicon carrier velocity.

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22% faster (access time) than the 1983 DRAM! Moreover, another 22% advance by 2003 will only put access times at a very mundane 55 ns. The mismatch between MPU and memory (including DRAM) performance is already causing headaches for the system manufacturer. New DRAM circuit architectures are attempting to solve this increasingly encountered problem. As previously mentioned, lower supply voltages will slow the performance improvements of advanced DRAMs. Thus, if a 2003 DRAM is to achieve even the meager 22% performance improvement over 1993 DRAMs, new circuit design techniques will be required.

In 1983 it was hard to imagine ever making ICs with feature sizes finer than 0.5 mm. However, 10 years later, the majority of 256M DRAMs described at ISSCC 1993 used 0.25-mm features!

If 0.03-mm feature sizes are able to be used for IC production in 2003 it will not be with optical lithography. In fact, between now and the end of the decade there is expected to be a discontinuity as the industry shifts from optical lithography to a different and more expensive method (most likely some type of x-ray or e-beam). Mitsubishi, for example, expects x-ray lithography to be used below 0.25 mm feature sizes [1]. According to Rensselaer Polytechnic Institute, if the industry progressed along the current trend line, the feature size fundamental limit should not be reached until at least 2030 (Fig. 5.6).

In late 1992 and early 1993 a couple of research laboratories (Bell Labs and IBM) described creation of transistors that turned on and off with the movement of one atom! Although the practicality of using such structures in an IC is at least a couple of decades away, it does illustrate how small feature sizes can ultimately be.

Another technology envisioned by Mitsubishi to be used in sub-0.25-mm ICs is silicon-on-insulator (SOI) processing. Figure 5.7 shows some of the features and advantages of SOI technology for advanced ICs. Although SOI wafers now cost quite a bit more than non-SOI wafers, * sub-0.25-mm circuitry may require the beneficial aspects of SOI regardless of the increased cost.

Then there are some issues that crop up that are beyond the realm of, but clearly intertwined with, technology per se: application and economic issues.

DRAMs will become more application specific. As shown in Fig. 5.8, DRAMs are evolving from so-called white, or generic, structures to application-specific architecture and designs.

Integrated circuit technology advances will increasingly hit against economic practicality in the mid to late 1990s. Figure 5.9 shows Mitsubishi's forecast for DRAM and gate array production equipment out through the 1G DRAM and 0.15-mm gate array device families.

As shown, extrapolating the cost of IC production equipment for the IG

*For example, a non-SOI 125-mm wafer costs about $20 whereas an SOI 125-mm wafer costs $225.

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Figure 5.6
Potential limits for lithography.

DRAM (near the year 2000) yields a required equipment investment by one company for this device of about $15 billion! Mitsubishi notes that this investment would be equal to about 70% of a manufacturer's semiconductor sales (as compared to the industry average of about 20% today)!

In summary, after examining the extrapolated 2003 DRAM characteristics, while most of the aspects of the device appear achievable, they do not appear to be economically practicalat least from a 1994 viewpoint; and at some point in the DRAM growth hierarchy physical or economic limits will present themselves.

Vertical Structures

To achieve the ever-increasing packing densities required, technologists have been developing vertical structure fabrication techniques. Two, silicon-on-insulator and 3-D ICs, are presented in this section. But first, several practical implementations using trench technology to fabricate vertical field-effect transistor structures are presented (Figs. 5.10 through 5.14).

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Figure 5.7
SOI impact on GSI (Gigabit Scale Integration).

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Figure 5.8
White DRAM to application-specific DRAM.

Figure 5.9
Mitsubishi's forecast for DRAM and gate-array production
equipment investment. (Courtesy of ICE Corp.,
STATUS 1994.)

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In Fig. 5.10 an active transistor is built on the side of an etched trench. Device fabrication begins with selective oxidation to define the transistor area. Then boron ions are implanted so that their region of maximum concentration forms the p⁺ channel at the midpoint of the depth of the 0.8-mm-deep trench in which FETs will be fabricated. Reactive ion etching is used to form the trench. Next, the 15-nm-thick gate oxide is formed in the trench, and the polysilicon is deposited on the inner walls of the trench to form the gate. The thick region on top of the wafer is etched back, and the oxide film between the gate and the drain connection is formed.

After etchback of the oxide, the n⁺ polysilicon drain connection is formed and the moat is completely filled. Gate and drain contacts are metallized, followed by n⁺ diffusion of source and drain contacts. The n⁺ region that forms the actual drain contact to the drain connection at the bottom of the moat is implemented by solid-state diffusion from the n⁺ polysilicon.

Another vertical trench approach for fabricating high-density DRAM memory cells is shown in Fig. 5.11. In this vertical cell, the capacitor and transistor are formed on the side walls of a 1.3 × 1.5 mm² trench; the trench in turn, is etched in a 4.5-mm-thick p⁻ epitaxial layer on a p⁺ substrate. The p⁺ wafer acts as a grounded capacitor plate, rendering the cell insensitive to minor carrier disturbances or substrate noise.

The n⁺-doped polysilicon charge storage node, at the bottom of the trench, is primarily oxide isolated to minimize charge loss caused by junction leakage and ionizing radiation. A vertical n-channel pass transistor is formed above the storage region. A buried lateral contact, formed by the outward migration of the

Figure 5.10
Vertical FET structure in which the transistor is
fabricated on the trench wall.

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Figure 5.11
This vertical memory cell is built inside a trench with the pass transistor
above the capacitor.

n⁺ dopant from the polysilicon, connects the storage node to the source of the pass transistor.

The pass transistor's drain consists of a buried n⁺ bit line, thus eliminating the bit line contact typically formed within the cell region. The effective gate length of the pass transistor is controlled by the dopant profile from a high-energy boron implantation. That implant also adjusts the threshold voltage.

In this memory cell, the vertical transistor is formed along all four walls of the trench opening, making the cell capacitor self-isolating and eliminating the problems that are encountered in the folded capacitor and buried cell structures.

Instead of going down into the silicon, another cell configuration (a three-dimensional stacked cell) builds on top of it, with silicon-on-insulator techniques as shown in Fig. 5.12. This dynamic RAM cell stacks the pass transistor above the capacitors in a laser-recrystallized layer of silicon. To suppress the lateral diffusion of impurities from the n⁺ region, a nondoped epitaxial silicon layer (a liquid-phase diffusion stopper) is selectively grown on the seeding area before depositing the doped polysilicon to be recrystallized.

The trench capacitors in the substrate have a value of more than 100 fF, assuring sufficient charge to avoid soft-error problems. However, to improve the cell's resistance to alpha particles, a p⁺ barrier can be used beneath the n⁺ capacitor in the trench.

A deep trench memory cell is shown in Fig. 5.13. In this design, deep

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Figure 5.12
Using silicon-on-insulator techniques, this
memory cell has the pass transistors built
above the trench capacitors on a
laser-recrystallized layer of silicon.

Figure 5.13
Deep trench structure formed with reactive ion etching (RIE).

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trenches 1 mm wide and 3 mm deep are etched with reactive ion etching. Then a shallow n⁺ layer using an arsenic dopant is formed by thermal decomposition of tetraethoxysilane (TEOS) and triethoxyarsine (TEOA) through low-pressure chemical vapor deposition. After a drive-in diffusion to the side wall, an oxidation step is performed prior to gate oxidation to round the convex and concave corners. After the gate oxide is thermally grown in water diluted by argon at high temperature, the trenches are filled with polysilicon to form the capacitor electrode.

In the one-transistor, one-capacitor buried storage-electrode cell structure shown in Fig. 5.14, which features high alpha-particle immunity as well as reduced soft errors and punchthrough, the storage capacitor is formed by digging a 5-mm-deep trench measuring 0.8 by 1.2 mm, laying down a dielectric film on the inside wall of the trench, and then refilling with polysilicon. The polysilicon is then connected directly to the transfer transistor, which is fabricated in a 1.5-mm-thick p-type epitaxial layer on a p⁺⁺ substrate. In this configuration, the charge is stored on the refilled polysilicon side, while the p⁺⁺ substrate side on the trench serves as the capacitor plate.

In contrast to standard memory cell structures, in which the charge is stored on the substrate side, the buried storage electrode cell is insensitive to minority carrier disturbance from alpha particles. Because the capacitor's storage electrode is isolated from the heavily doped p⁺⁺ substrate, the isolation region between neighboring regions can be very narrow (0.8 mm), contributing significantly to reducing the size of the cell.

The vertical cell structures just presented show some of the myriad of design and process possibilities that are being developed to fabricate state-of-the-art small-geometry DRAMs. Inherent in each approach is an exponential

Figure 5.14
One-transistor, one-capacitor buried storage electrode memory
cell structure.

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increase in processing complexity and thus the possibility for reducing device quality.

Silicon-Germanium Devices

As IC manufacturers struggle to put more transistors on a single chip and increase circuit speed, the physical and electrical limitations of silicon wafers become a major concern. As a result, alternative materials are being considered. One such material is silicon-germanium (SiGe).

The concept behind SiGe is to add (through the doping process) the benefit of germanium's high carrier mobility to a silicon wafer. High electron mobility is particularly good for both bipolar and field effect transistor devices. The electron mobility of germanium is nearly twice that of silicon.

Figure 5.15 is a cross section of IBM's high-performance FET, designed using its 0.25-mm BiCMOS SiGe process. By going to a 0.1-mm process, IBM expects the SiGe circuits to rival gallium arsenide in speed while providing a lower cost solution.

Silicon-on-Insulator (SOI) Technology

Silicon-on-insulator (SOI) technology is showing great promise for solving some of the device physics problems anticipated with producing deep-submicron ICs

Figure 5.15
IBM's high-performance SiGe FET. (Courtesy of
ICE Corp., STATUS 1994).

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in the future. But its inherent advantages are prompting serious consideration by major semiconductor firms to use SOI technology for today's chips.

SOI wafers are comprised of a layer of a high-quality insulator on a bulk silicon substrate, which is then covered by a thin silicon layer where the active circuit is built (Figure 5.16). Such a structure dielectrically isolates circuit elements, thereby reducing problems like punch through and latch-up, which can occur when silicon junctions are so close to each other that the electric fields in the junctions interfere with each other. It also provides reduced junction capacitance, resulting in 20100% faster circuit speed than bulk silicon devices with the same device dimensions. Moreover, SOI devices consume significantly less power (2575% less) than bulk silicon products. Other benefits of SOI technology include easier scaling to smaller linewidths; immunity to latch-up; improved resistance to radiation; higher operating temperatures; higher packing density; and simpler processing. One of the major advantages of SOI is its compatibility with existing silicon processing flows, while on the down side is SOI's high wafer cost.

There are a number of different silicon-on-insulator technologies including SIMOX (separation by implantation of oxygen), BESOI (bonded etched-back SOI), silicon-on-sapphire (SOS), zone-melt recrystallization, epitaxial lateral overgrowth, field isolation by porous silicon, and others. So far, only SOS, SIMOX, and BESOI are commercially available.

SIMOX involves the bombarding of a normal silicon wafer surface with oxygen ions to stimulate growth of oxide. The process is reliable and easily performed in a manufacturing environment. It allows the formation of extremely thin silicon layers (<0.2 mm) with precise thickness uniformity. Oxygen implantation does, however, introduce some material defects in the silicon and buried oxide layers. Newly developed low-dose implant processes have left nearly defect-free silicon over thin buried-oxide layers.

Bonded wafers are formed by sandwiching a piece of silicon with two pieces of silicon dioxide (glass) and fusing them together by annealing. The top

Figure 5.16
SOI structure. (Courtesy of ICE Corp., STATUS 1994.)

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layer is then ground, polished, and chemically etched until the desired silicon thickness is attained. While bonded wafers are less costly, more manufacturing steps are required and the top layer only covers the wafer to within approximately 3 mm of the substrate edge, leading to a potential loss of about 10% of the silicon area (on a 100-mm wafer).

There is some evidence that SOI may become a mainstream technology. Problems with leakage and short-channel effects could render traditional bulk silicon unsuitable for advanced CMOS circuit production, and the isolation effects provided by SOI's buried insulator layer may offer a remedy.

Several factors are driving IC manufacturers to reconsider SOI. CMOS device geometries below 0.35 mm bring attendant problems of latch-up and short-channel effects; SOI's dielectric isolation has natural immunity to latch-up, and fully depleted devices can be made by reducing the silicon film thickness to less than the channel region depletion depth. This cuts charge-sharing and drain-induced barrier lowering (DIBL), and boosts drive current by 3050%. SOI also slashes leakage from noncritical junctions, allowing devices to have a much lower standby current. Moreover, moving a CMOS design to SOI can boost device speed to ECL or bipolar levels for some designs.

There are, of course, down sides: the thickness uniformity of silicon and insulator films must be maintained to within a few tens of angstroms, the SOI oxide layer prevents metallic contaminants from being removed by the traditional back-side gettering process, and per-wafer cost is substantially higher. The cost issue is partially offset, however, by the ability to eliminate several masking and implant steps during device fabrication. Reference 3 discusses cell structures for 256-Mbit and 1-Gbit DRAMS using an SOI substrate.

Three-Dimensional ICS

Silicon-on-insulator technology forms the basis for and fabrication of dense three-dimensional ICs. In one technique (see Fig. 5.17), individual VLSI wafers are fabricated with conventional techniques and then interconnected physically and electrically. Following those steps, a 23 mm layer of polyimide is spin-coated on one side of each wafer. This insulating film serves three purposes: it flattens the wafers, bonds them together during stacking, and acts as a packing material between them.

Next the film is partially cured, maintaining a degree of stickiness, and then selectively thinned until the gold vias are exposed. The polyimide-coated surfaces of the wafers are bonded and aligned so that the vias make contact. The wafers are subsequently thermally compressed to connect the vias. The gold vias themselves are 2 and 3 mm high and form a cross section of 10 × 10 mm. They can be used for future vertical wafer connections.

The wafer-glue technique should produce a variety of benefits, ranging

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Figure 5.17
A three-dimensional integration technique fabricates two wafers separately and
then glues them together with a polyimide film.

from a complete mixing of bipolar, CMOS, and even gallium arsenide technologies to high-voltage isolation. Moreover, it can be extended to additional layers, and the production yield should be high because each wafer is tested before stacking.

Recrystallizing polysilicon film into monocrystalline form is the original three-dimensional SOI technology. In an integrated version that combines both bipolar and CMOS technologies, a layer of oxide is grown on a silicon wafer, polysilicon is deposited on top, and then the polysilicon is annealed or zone-melted. These steps convert the material into monocrystalline form.

Using this approach, two silicon-on-insulator structures were fabricated as shown in Fig. 5.18. In the first (Fig. 5.18a), the silicon-gate CMOS transistors and the n-p-n bipolar transistors are formed in film, using an extra layer of polysilicon for the gate, emitter, and contacts. Though the film is initially 1 mm thick, it is subsequently etched down to 0.3 mm.

In the second structure (Fig. 5.18b), the MOS transistors are incorporated in film, but the n-p-n transistor is formed on an n-type epitaxial layer that grows on the original p silicon substrate (a window must first be etched in the oxide). The resulting structure is extremely flat, simplifying metal inter-connection and passivation. Both n-p-n structures have betas of 100, but the collector resistance of the bipolar film units is higher than that of the epitaxial devices.

Another three-dimensional structure involves stacking three levels of silicon on a single chip. NMOS transistors are formed in the first level or

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Figure 5.18
Recrystallization of polysilicon film is used to fabricate n-p-n
transistors (a) on the film and (b) in the p substrate
through a window etched in the oxide.

substrate. A laser recrystallizes the polysilicon to create the second and third levels, in which reside NMOS transistors and photodiode sensors, respectively.

A p-type wafer is used for the first level, fabricating NMOS devices in the bulk silicon (see Fig. 5.19). Phosphorus-doped polysilicon replaces aluminum as the interconnector at that level because of its ability to survive the high temperatures of the subsequent processing stages.

Low-pressure chemical vapor deposition (LPCVD) forms the insulating base of the second level. A layer of oxide, 0.7 mm thick, is grown, then etched back to make it more planar, and then a second 0.6-mm layer of oxide is placed above it.

To form the active region of this level, 0.5 mm of polysilicon is deposited, covered with 500 Å of silicon nitride, and then patterned with stripes 5 mm wide and spaced 10 mm apart. The stripes act as antireflection coatings to help control the thermal profile, both as the laser melts the polysilicon and during resolidification.

The resulting recrystallization yields 15-mm-wide single-crystal silicon stripes sandwiched between straight silicon-grain boundaries. Thus, perfectly controlled single-crystal regions are available for the transistors. The silicon

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Figure 5.19
Three active levels of silicon are stacked on one chip.

dioxide insulating layer deposited (to form the base of the third layer) above this region is slightly thicker than the corresponding first-level layer, but it is formed in the same way.

To form the third active level, polysilicon thicker than that on the second level is deposited on top of the insulating layer. After recrystallization, shallow-junction NMOS devices are formed in the single-crystal material to create photodiode sensors and other circuitry. Layer-to-layer interconnection holes are formed in the same manner as most other NMOS circuits, with special care paid to alignment. Above the third level are layers of aluminum and nitride, and a passivation layer forms a protective cap.

One FET structure [2] solves the short channel effects that have plagued submicron MOSFETs and places one gate above and another below the channel to facilitate three-dimensional circuits.

Logic Simulation

Integrated circuit device simulator models need to be evaluated and updated to accurately represent state-of-the-art device structures and manufacturing processes. For example, model adjustments must be made in order to address very-high-speed devices: parasitics are becoming more dominant, requiring more accurate extraction; and lumped RC load models have to be changed to RC-loaded transmission line models. Accurate device models will result in proper circuit design being accomplished, which is where quality begins.

One problem that has to be addressed is that of maintaining the integrity of the representation between and within the various existing design, simulation and verification, process parameter, and test data bases, and the translation of these data bases.

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References

1. Komiya, Future Technological and Economic Prospects for VLSI, 1993 ISSCC Plenary Session.

2. C. L. Cohen, New FET Design Could Speed the Arrival of 3-D Circuits, Electronics, September 9, 1985.

3. T. Nishihana, et al., A buried capacitor cell with banded SOI for 256-Mbit and 1-Gbit DRAM, Solid State Technology, June 1994, pp. 8994.

4. A. J. Auberton-Herve and T. Nishimura, SOI-based devices: status overview, Solid State Technology, July 1994, pp. 8996.

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6
Changing Fabrication Techniques

The high levels of integration and the small feature sizes currently used in the fabrication of integrated circuits result in extremely complex processes including ion implantation, diffusion, film depositions of both dielectric and metallization, lithography, oxidation, and etching. Not only must each individual process step be optimized to its state-of-the-art limits, but each must be integrated with the others to successfully achieve an operational integrated circuit (IC). One major trend of the future that will significantly impact the fabrication process of advanced ICs (VLSI and ULSI) is single-wafer processing as opposed to batch processing due to the idiosyncracies of handling and processing 8-in. and larger wafer sizes. This chapter discusses technological changes to IC manufacturing processes being introduced that will serve to both impact and enhance the quality of semiconductor products.

Lithography

Lithography must be viewed as a total and complex system. Advances in tooling, mask technology, resist materials, and new processes have opened avenues for

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future applications. The five key elements of a lithographic system and their influence are

1. Exposure tools: affect resolution and overlay

2. Resists: affect throughput and image quality

3. Developing techniques: affect image tolerance and profile

4. Etching techniques: affect image tolerance and profile

5. Measuring techniques: affect process control

Lithography represents one of the highest cost elements in IC production, and within the total lithography system the exposure tool is the dominant cost item. Hence, the choice of lithography system and exposure tool selection is a delicate balance of cost, performance, and productivity. It is also foreseeable that mixed lithography will gain increased popularity. For example, one exposure system would be used for the critical masking level and another for noncritical levels.

One trend occurring more frequently due to the small geometry and complexity of VLSI circuits is that of photomasking individual dice rather than full wafers to increase device yield and quality. Fabrication costs, however, will increase and throughput will decrease.

Optical Lithography

While the demise of optical lithography has been forcast for some time, most IC suppliers see optical step-and-repeat systems as the best way to put VLSI circuit patterns on wafers because these systems are cheaper and faster than their electron-beam counterparts. The continued widespread use of optical lithography is due to the improvements in the chip-making process with only small increases to manufacturing costs, eliminating any incentive to change to another technique. Optical lithography is still the most cost-efficient way to get the job done.

Two factors have enabled optical lithography to retain its dominant position. The first is continued improvement in the technology. Optical steppers and 1:1 scanning optic systems have performed successfully at the 1-mm level for many years. Steppers work by shining a light from an ultraviolet source through an enlarged portion of an IC wafer pattern, known as a reticule. The pattern is projected onto the wafer's resist-covered surface through a reduction lens. After exposure, the machine's table is mechanically stepped to a new site for the next exposure. This procedure is repeated until the entire wafer is exposed. More recently, the reduction stepper has allowed 0.5-mm devices to be fabricated.

The scanner, on the other hand, has a complex reflective lens system that uses a mask to project an image the same size as the mask on to a wafer.

The second factor is the failure of the electron-beam technique to carve a position for itself on the IC production floor. The electron beam's fine-line capability has never been questioned. However, the equipment is difficult to

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interface with IC production lines because it needs special resists and takes up a lot of floor space. In addition, electron-beam systems are more expensive than optical systems and they suffer from low throughput.

Optical technology has improved in a variety of ways, and it should continue to do so. The major improvementsand the most dramatichave been in better resolution lenses and higher numerical apertures, as well as in new and improved photoresist techniques. Also contributing is the increased use of pellicles to lessen particle contamination and improve the alignment circuitry. A pellicle is a thin transparent membrane stretched across and just above the reticle or a mask. The pellicle allows light to pass through. However, dust and other yield-killing particles are kept far enough off the reticle that their image remains out of focus. Consequently, rather than dust particles being eliminated, they are rendered harmless. Pellicles are said to improve yield by about 70%.

There is a problem with optical lithography, however. Generating the necessary reticles to expose the pattern onto the wafer is a slow and expensive step, particularly with the accuracy, throughput, and low defect level needed for ICs designed with 0.5-mm or smaller features. A newly developed laser-scanned reticle printer could greatly improve reticle performance, which will aid the optical steppers. Its advantages include

Throughput 510 times faster than electron-beam methods

Higher yield of reticles than is possible with electron-beam technology

Process compatibility with optical photoresists and electron-beam tape formats

Equipment costs that are less than one-half those for electron-beam lithography equipment

The key technical problems in reticle generation are the demands for extremely high precision and information density. Circuit geometries must be written with a position accuracy on the order of one part per milliona proportion comparable to the width of a human hair against that of a football field. Nonetheless, the scanned-laser reticle writer has the capability of generating the required precise reticles for smaller geometry devices.

These improvements led to several changes beginning in 1978 and 1979, when optical lithography was based on 10× steppers and 1:1 scanning projection machines producing 3-mm IC features. Today, optical lithography has crossed the 1-mm level with achievable resolution in the 0.50.65-mm range and overlay accuracy to better than 0.1 mm. In fact, optical lithography is being used to fabricate 0.5-mm circuits, ensuring its viability for some time to come. Table 6.1 summarizes the key features of the various optical lithographic techniques currently available.

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Table 6.1 Summary of Key Optical Imaging Features

Contact proximity mask aligners

Used for mature large-geometry devices

Lowest cost, no frills (auto cassette loaders and mask changers)

Can provide very high resolution with excimer source

Close alignment difficult in contact mode

Full-field scanning projection

Nearly twice the throughput of steppers

Most useful between 1.2 and 1.5 mm feature size

Control of mask defects feasible, but expensive

Mix/match with steppers well accepted

Full field only to 6-in. wafers

Step/scan future possibility

Optical steppers1:1 projection

Larger field (thus scans wafer more rapidly), depth of focus, lower aberrations than reduction stepper

Lower capital cost per equipment, per wafer than reduction stepper

Resolution below 1mm (0.80.9) now achievable

Reticle defects under control (they do not limit its use)

Optical wafer steppersreduction

Reduction (5×, 10×) reduces influence of reticle defects and mask errors, allowing use of coarser reticle

Throughput: approximately 3040 6-in. wafers per hour

Resolution to 0.80.9 mm with 0.35 numerical aperture (NA) lens

0.43 NA reduction lenses for 0.7-mm resolution

Overlay accuracy better than 0.1 mm

Mask changer to run all critical layers on one unit so as not to have problems with mirror lens aberration and distortions

Wafer leveling introduced: because depth of focus is miniscule, the curvature of wafer is taken into account, thus there is calibration across the entire wafer

Advances have also been made in illumination sources. For example, current steppers have improved dramatically using a deep-ultraviolet lens. Further reductions in wavelength have been achieved using a deep-UV excimer laser source and special fused-quartz lenses, resulting in minimum feature sizes of less than 0.5 mm.

Besides shorter wavelength optical systems, IC suppliers have explored multilayer resist systems to get the even finer lines required by very-large-scale and ultra-large-scale integration applications. Finer lines require thinner and more fragile resist coatings. If a thin resist is spun over a nonplanar surface, the resist will be distributed unevenly over the wafer, resulting in a distorted exposure image. Because of this, two- and three-layer resist approaches have been

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developed to planarize a wafer's surface and efficiently handle a thin photoresist layer.

However, as multilevel resist techniques are incorporated into the production process, they add many steps to the IC processing flow, increasing cost.

Though optical lithography will survive well into the 1990s and perhaps to the end of the century, one still asks the question, what technology will replace optical lithography? X-ray or electron-beam direct writing (which are the most likely candidates), or some current research technique such as ion-beam lithography or holography?

X-ray technology has advantages over electron-beam direct writing. These include simplicity, absence of proximity effects, large depth of focus, and, most important, an immunity to dust. But electron-beam technology has built up a tremendous backlog of design and operational experience, while many design problems remain for X-ray methods. Until now, most commercial electron-beam efforts have gone for mask making. Only now are the few existing electron-beam equipment companies beginning to concentrate on direct writing.

The IC industry's increased production of application-specific ICs could generate much interest in the direct-write electron-beam system. That is because those semicustom chips do not require large production volumes; it is cost-effective to fabricate them with a direct-writing electron-beam machine rather than producing an expensive and time-intensive reticle for an optical stepper. Let's look at both of these techniques in greater detail.

E-Beam Systems

As the dimensions in VLSI and ULSI circuit patterns approach the resolution limits of light optics, the use of an electron beam to write directly on resistcoated wafers has attracted considerable attention. Electron-beam lithography avoids the limitation of resolution and depth of focus imposed by the wavelength of light, has an excellent capability for overlay, offers a high degree of pattern flexibility, and makes it possible to control microscopic pattern distortion in real time. However, in spite of these attractive features, the ultimate viability of e-beam lithography is still questionable. The economic concerns of high equipment cost, low throughput, and high unit cost are the major obstacles for wide application in high-volume integrated circuit production. Then there is the issue of high defect levels inherent in e-beam resists, which require lengthy inspection and repair times, unsuitable for quick turnaround and rapid throughput.

In addition, a multilevel resist process is essential for submicrometer device fabrication. The process complexity, plus the high tooling cost, raises a real economic concern. The use of multilevel resists is further discussed in the section on Material Technology Trends. Furthermore, e-beam lithography is incompati-

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ble with most existing semiconductor process technologies, requiring suppliers to replace capital equipment. All of these raise the question as to e-beam's practicality in a normal wafer production environment.

E-beam lithography has a dual identity represented by mask making and direct write. The e-beam for mask making is a well established technology used by most IC suppliers and mask houses. The e-beam for direct write is predominantly a research and development technique, although several IC suppliers are using direct-write e-beam in a production environment.

Over the past two decades, significant effort has been directed toward improving throughput by reducing the time-contributing factors required to write a wafer: namely, mechanical handling time, registration time, writing time, and X-Y stage movements between fields. Let's look at some of these key issues.

Registration accuracy is important in both applications. The difference lies in the level of complexity required to achieve good registration. The major difference is that wafers have registration marks while masks do not. Therefore, achieving good registration in mask making requires the system to have more intrinsic accuracy than that required for direct write. Direct-write registration is achieved by referencing to the registration marks already on the wafer. In large measure, the accuracy of the system is dependent upon the ability of the system to detect these registration marks on the wafer. Furthermore, long-term stability is not critical because the beam can be reregistered after writing each die. Of course, this reregistering process must be quick and efficient.

The mask maker must be able to reproduce the same plate and produce a set of masks that overlay with a high degree of accuracy (on the order of 0.1 mm). Since there are no landmarks on the mask, the referencing must be within the system itself.

Mechanically, this is a very demanding and expensive process. Some e-beam systems have a grid located on the stage or table portion of the system which serves as a reference point. However, in writing a pattern on a mask, a single layer is written across a 6- to 8-in. substrate without realignment. Therefore, stability is a critical factor in maintaining a high degree of accuracy in registration. Temperature control is important in maintaining good stability as well as precise table positioning.

However, some IC suppliers believe that placement accuracy is more demanding in direct write than mask making because in mask making most people are generating 10× reticles, while in direct write linewidths are in the submicrometer range. Furthermore, even for 1× masks the linewidths being used are in the 1.52.0-mm range and the grid spacing on a direct-write system is smaller than that of one for mask making.

Like registration, throughput is important in both applications but for direct write, throughput is probably the major issue. Two of the advantages of generating e-beam masks are the speed and the accuracy with which a mask can

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be produced. Older optical techniques for generating masks require many hours, whereas an e-beam system can write a mask in a half hour to an hour. Thus, throughput is not a key issue in mask making with e-beam because it is already offering a substantial time savings.

Defect control and line edge roughness are the two most often mentioned problems with e-beam-generated masks. The first of these problems, defects, is not really a function of the e-beam system but rather a problem with the resists and processing associated with e-beam mask making. Generally speaking, the e-beam resists are of poorer quality than those for optical lithography. Photoresists are much farther along on the learning curve than e-beam resists; thus, optical pattern-generated masks have the advantage of good-quality photoresists. This situation should be changing in the very near future because of the effort being devoted to improving e-beam resists and improving e-beam systems to expose photoresist.

Roughness of line edges has been a problem with e-beam-generated masks, but improvements over the last few years have reduced the problem significantly. One of the solutions to the problem is to make 10× or 5× reticles and step to 1×. Improvements in the electronics have also reduced the roughness of line edges for 1× masks.

Throughput has been the limiting factor in the use of direct write for production of devices. Optical techniques are significantly faster than writing with an e-beam system. Many factors contribute to the throughput of an e-beam direct-write system. However, there is an inherent difference that reduces the throughput of direct writing. In exposing a wafer using optical techniques, millions of circuit elements are exposed in parallel, while in e-beam one element at a time is written in a serial fashion. This inherent difference makes throughput a key issue in direct write viability as a production tool. An offsetting factor is the shift to small-quantity (essentially prototype quantities), application-specific ICs in which throughput is not a primary consideration. Other factors are wafer handling (moving the wafer in and out of the vacuum); placement of the wafer on the stage; movement of the wafer stage; checking for registration; and movement of the beam. Another factor, though not part of the system itself but very important, is the sensitivity of the resist. This factor is also tied to the current density of the electron beam.

E-beam lithography offers better resolution over optical techniques because of its shorter wavelength. In fact, the wavelength is four to five orders of magnitude shorter than optical techniquesthis was the original interest in e-beam for direct write. Ultimately, though, e-beam became attractive for mask making because of its flexibility; it is easier to move a beam of electrons across a mask than it is to move a beam of photons (light). Charged particle beams can be moved around by electrostatic and magnetic forces, while photons need to be mechanically moved by mirrors or by moving the stage or station. This greater

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flexibility translates into greater speed, as well as the ability to write different patterns on a single mask substrate.

Thus e-beam masks offer better overlay accuracy and better critical dimension (CD) control and have better registration over optical stepping for 1× masks.

Another factor that has limited the use of e-beam systems for direct write has been the high capital investment required. Most optical equipment is substantially less expensive than e-beam systems. Thus there is considerable interest in stretching the limits of optical tools. Additionally, optical techniques have advanced considerably over the last few years, reducing the need to convert to e-beam technology. Linewidths have not shrunk as fast as originally predicted, and this further reduces the need for e-beam direct write.

It appears that optical techniques are as good as the marketplace requires and they have the throughput advantage. At present no one has demonstrated the cost-effectiveness of direct write versus optical. E-beam direct write is not competitive in terms of cost per chip; it is still predominantly a research and development tool. Whether e-beam direct write ever assumes a major role in the production of devices is still open to question. Certainly it will have its niche. Factors that will contribute to limiting the use of e-beam direct write are the advances made with optical methods and X-ray lithography. Resists for e-beam also will be a contributing factor because the resists in use today lack sufficient sensitivity, resulting in lower throughput. Work is being done in this area, and any improvements in resist sensitivity will go a long way in increasing the throughput.

X-Ray Lithography*

X-ray lithography has long been touted as the technology needed to overcome the limitations of optical and electron-beam lithography in the move to submicrometer features. X-ray lithography provides several potential technological and economic advantages. The primary advantage of X-ray lithography is its high-image resolution, due to the short wavelength of the X-rays. It is not affected by either depth-of-focus problems or by the reflection and scattering effects that plague optical and electron-beam lithographic techniques. X-ray lithography achieves high aspect ratios in resist patterns for submicrometer device fabrication. This allows the use of a single-level thick resist process, which is not feasible for optical lithography due to diffraction effects and/or electron-beam lithography due to proximity effects for dense circuits with linewidths less than 1 mm at the current state of the art. Also, X-rays are transparent to particulates that produce mask and wafer defects with other approaches.

*Portions of this section used with permission from Ref. 1.

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Of all the problems that confront X-ray lithography, mask making has been the hardest to solve. A mask must be distortion free and capable of being patterned to submicrometer dimensions. Glass substrates provide high transparency to ultraviolet light, but only thin membranes (thinner than 10 mm) of materials having low atomic number are transparent to X-rays with wavelengths smaller than 10 Å.

Most X-ray mask blanks are made of a thin-film membrane structure supported around its periphery by a ring. The membrane, which is held in tension to keep it flat, is transparent to X-rays and acts as a substrate for the X-ray absorber pattern that blocks the X-rays. It can be either a single- or multilayer structure, and it must have a high tensile strength to keep it from fracturing under the tension.

The most useful X-ray mask blanks have been made by depositing the membrane material by vapor deposition on a host substrate, which is then back etched. The most common membrane material is boron nitride, whose membrane thickness is typically 36 mm. This material is deposited by low-pressure or plasma-enhanced chemical vapor deposition on silicon substrates. The resulting film is a hydrogenated, amorphous form of boron nitride. Other materials that have successfully formed membranes include silicon nitride and silicon carbide. The membrane is usually coated with a polymide layer, which strengthens the structure as well as planarizes the surface. However, a potential problem exists. Thermal stresses occur in thin X-ray masks, which can lead to distortion, thus imparing chip quality.

Absorber patterns on an X-ray mask can be gold, tantalum, or tungsten. Gold absorbers can be patterned by either subtractive or additive techniques.

The theoretical limit of X-ray resolution expressed as minimum feature size lies in the range of 0.10.2 mm. Resolution is limited only by such factors as penumbra blur (due to finite spot source), contrast (mask-to-absorber pattern thickness), and secondary photoemission in the resist. Edge definition of a printed X-ray pattern in resist is not degraded by standing waves, as is the case in optical systems, or by proximity effects associated with e-beam lithography.

Also, while direct-write e-beam equipment is expected to be an essential tool for submicrometer IC development, the economics of e-beam versus X-ray lithography for high volumes strongly favor X-ray, with e-beam performing more sophisticated submicrometer imaging of X-ray masks. X-ray offers higher throughput at lower cost for the same resolution.

Throughput projections for full-field research equipment range from 12 to 20 wafers per hour as listed in Table 6.2, based on currently available X-ray resists. However, anticipated advances in resists, sources, and alignment times should increase throughput to in excess of 24 wafers per hour.

As shown in Table 6.2, both full-field and step-and-repeat systems show the inherently high resolution of X-ray lithography. Level-to-level overlayanother user parameteris composed of mask, wafer, and alignment errors.

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Table 6.2 X-ray Lithography Performance Parameters [1]

Parameter

Full wafer exposure system

Step and repeat system

Exposure field

Full wafer(100 mm diameter)

2 cm × 2 cm (typical)

Minimum feature size

0.51.0 mm

<0.5 mm

Overlay (2s)

0.250.50 mm

0.10.2 mm

Throughput

1220 W/h

>24 W/h

Step-and-repeat systems will use smaller exposure sights (subfields) together with physical optics alignment to minimize wafer-to-wafer overlay error.

Another advantage of X-ray technology concerns defects like dust particles that are, to a large extent, transparent to X-rays and therefore do not print during an exposure. Inorganic materials such as silicon, SiO₂ and Si₃N₄, and organic ones transmit X-rays. So silicon or organic particles can occur 30 times the thickness of the gold absorbing pattern before they absorb an equivalent amount of 7-Å X-ray energy. Lower defect printing, higher circuit yields, and lower costs per die result.

Due to smaller field sizes, step-and-repeat systems minimize the effect of nonlinear distortion associated with mask patterning, wafer processing, and electron-beam lithography. Smaller exposure sites permit closer mask-to-wafer spacing, thereby reducing penumbral blur. Nonlinear distortion is reduced to small values when field size is reduced. In addition, smaller sites allow higher and more uniform flux distribution across the exposed field, providing tighter linewidth control. Small step-and-repeat reticles are easier and cheaper to produce than full-size masks. Step-and-repeat systems are versatile, because they can handle any size wafer without having to develop larger area masks.

With the development of high-resolution, high-speed resists and the use of high-power X-ray sources, the slow throughput associated with step-and-repeat systems is avoided.

The four most critical issues associated with X-ray lithography are summarized in Table 6.3. They represent technical problems that need to be addressed before X-ray equipment can confidently be used for the high-volume manufacture of submicrometer ICs. X-ray mask technology, considered to be the most difficult barrier, must achieve membrane mechanical stability and nonlinear patterning distortions of less than 0.01 mm and 0.03 mm, respectively, to meet the level-to-level overlay of 0.1 mm necessary for 0.5-mm circuit production. Mask defect density must be less than 0.5 defects/cm² to gain adequate yields for economical device fabrication.

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Table 6.3 X-ray Lithography Technology Issues and Solutions [1]

Issues

Solutions

Mask Technology

Membrane stability (0.01 mm)
Defect density (<0.5/cm²)
Patterning distortion (0.03 mm)

Titanium (opaque and transparent viewing) mask

Silicon carbide (transparent) mask

Boron nitride (transparent)

Overlay Error

Overlay requirement (0.1-0.2 mm)
Geometrical optical approach

Alignment requirement (0.02 mm)
Physical optics alignment technology

X-ray Resist

Sensitivity (2-4 mJ/cm²)
Dry etch compatibility

Commercial developments (EK88 and COP)

Advanced resist developments

X-ray Source

High brightness (10 and 20 kW)
Small spot size (1.5-3.0 mm)

Conventional X-ray source (tungsten rotating anode)

Plasma source

Subsystems must perform wafer-to-mask alignment to accuracies of 0.02 mm and operate independent of mask errors to comply with the 0.1-mm overlay error. Similarly, resists with sensitivities in the range of 2 to 4 mJ/cm² and high-intensity sources (10 to 20 W) will ultimately be required to realize throughput goals.

Several solutions are being pursued in each major technology area. Titanium, silicon carbide, and boron nitride masks are under development at a number of companies. Geometric optical alignment techniques have demonstrated accuracies of 0.3 mm (rms). Advanced alignment subsystems using physical optics are also under development at several firms. These techniques utilize zone-plate and grating marks on masks and wafers and coherent illumination to derive misalignment signals. Zone-plate/grating-alignment approaches have demonstrated sensitivities below 0.2 mm with acceptable signal-to-noise ratios.

X-ray lithography may first be used in a mixed or hybrid mode. For example, critical levels of submicrometer circuits would utilize X-ray lithographic techniques, while levels having larger geometries will continue to be patterned with existing optical equipment. This situation can give rise to a unique source of overlay error. The optical image is printed with ultraviolet light at normal incidence to the wafer, so wafer height variations do not affect the lateral position of the image. Since X-ray exposures utilize a point source, image

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location is a function of proximity gap and is affected by variations in wafer height. Thus, overlay error depends on wafer flatness and the size of the exposure site. Wafer flatness variations of 2 mm can create overlay errors for hybrid imaging, but the source of error becomes very small for step-and-repeat systems having 2 cm × 2 cm fields.

Ion-Beam Lithography

Two techniques have been reported for the exposure of resist by ion beam. One is projecting a collimated ion beam, which irradiates a mask onto the resist-coated wafers. The other uses a scanning, focused ion beam, which is deflected across a resist-coated wafer to write the pattern serially. The former is analogous to X-ray lithography, and the latter is similar to a direct-write electron beam. In other words, ion-beam lithography has the potential of producing high-resolution, high-aspect ratio resist images and also offers the potential of direct writing free of proximity effects. However, the technology of both schemes is at the exploratory stage, and the mask technology, alignment system, and overlay capability remain to be evaluated. Table 6.4 lists the primary characteristics of e-beam exposure, X-ray proximity exposure, focused ion-beam, and scanned laser exposure lithography techniques.

Overlay Accuracy*

Increased packing density of semiconductor devices requires not only fine pattern delineation, but also improved registration accuracy. With 4 megabit dynamic random access memories (4-Mbit DRAMs), for example, the required minimum pattern size approaches 0.6 mm and the required registration accuracy is about 0.12 mm or less.

Recently, fully automatic die-by-die alignment technology used for wafer steppers has gained attention as one of the most useful approaches to achieving high registration accuracy.

Various techniques have been developed for die-by-die alignment: edge detection, reflected light contrast, and diffraction. For any of these methods, the optimization of an alignment mark pattern is important to achieve high alignment accuracy, and thus finished device quality. The two factors (both lithographic) that effect alignment accuracy are the line width of the alignment mark and the resist thickness. For the above 4-Mbit DRAM, the required line-width precision of the alignment mark pattern is ±0.3 mm. This value is larger compared with the critical dimension precision required for 4-Mbit DRAMs.

Variation of resist thickness has a large effect on alignment accuracy. The

*See Ref. 2 for greater detail.

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Table 6.4 New Lithographic TechniquesKey Feature Summaries

Electron-beam exposure

Widely used for many critical masks

Standard systems slow for wafer writing, but used for fast turnaround R&D

High overlay accuracy, <0.1 mm

Improved resists being developed

Shaped beam wafer writer undergoing evaluation

X-ray proximity exposure

Commercial units undergoing evaluation

Several mask process now developed and offered

Only a few mask defects print (most are transparent)

Resolution down to 0.10.2 mm

Masks are tricky, fragile, unrepairable, and expensive

Photoresists need higher sensitivity and better resolution

Focused ion beams for mask repair and direct-implant writing

Small area writing

Image repair

Equipment now undergoing evaluation

Can repair clear and opaque optical defects

Used for both wafer patterns and masks

Direct-implant writing

Used for implanting small regions in R&D facilities

Full wafer writing requires new equipment designs

Scanned laser exposure reticle/wafer writing

Use focused laser for mask generation or direct wafer write

Introduced in 1985 for reticle writing

Now capable of 2 mm resolution for reticles, useful for reduction steppers

Lower capital cost, smaller than e-beam equipment

Writing speed enhanced by multiple beams

deviation of alignment error changes periodically as the coated resist thickness changes. Therefore, it is important to optimize the resist thickness for each level of device structure and alignment method.

Alignment accuracy of ±0.3 mm (95% confidence, including mean offset) in actual device structures was achieved by optimization of the linewidth of alignment marks and the resist thickness.

Resists

The second key ingredient of any lithography system is resist. Resists are combinations of polymer and sensitizer. Resist materials are sensitive to light, X-ray, high-energy electron-beam, or ion-beam irradiation. It is not neces-

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sary to go deeply into resist theory except to say that the selection of a suitable resist for a specific application requires a comprehensive examination of resist sensitivity, resolution, and compatibility with companion processes and tools.

Resist performance for VLSI applications should exhibit the following desirable characteristics: high sensitivity (for the particular exposure tools chosen), dry developing, dry etch compatibility, and vertical profile control.

Development Techniques

Development of resist coatings requires fine tuning of resist materials to the product and process needs such as sensitivity (minimize exposure time for higher speeds), resolution capability (high aspect ratio for minimum linewidth), and compatibility with companion processes (wet and dry etching, application, temperature stability, and ion-implant stability).

Etching Techniques

The etching processes for VLSI and ULSI devices have to etch anisotropic features onto highly complex structures, such as refractory metals, silicides, and multilevel aluminum alloys. To achieve this capability, the semiconductor industry has been passing through a major transition, from wet to dry etching. For fabricating VLSI circuits, extensive use of plasma (as opposed to wet) etching of oxides, polysilicon, aluminum, and silicides is required in order to precisely define horizontal geometries in the desired IC layer without the lateral encroachment of the etched channel caused by liquid etchants. The unique feature of dry etching is that it promises the potential of zero bias and image profile tailoring capability. Directional control with minimum undercutting is the key benefit over the isotropic characteristics of wet chemical etching (see Fig. 6.1). Isotropic wet chemical etching results in feature sizes that differ from those in the original mask by an amount that is at least two times the

Figure 6.1
Comparison of wet versus dry etching for low-and high-density circuits [2].

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thickness of the film being etched. In practice, because of film and/or etching nonuniformity, it is necessary to overetch by varying amounts, resulting in a still further change of the feature size. For features <3 mm this change is intolerable.

Anisotropic etching occurs in polycrystalline or amorphous materials only when the substrate is subjected to ion bombardment as in parallel-plate plasma etching, reactive sputter (ion) etching, or reactive ion-beam etching.

Figure 6.2 shows cross-sectional representations of reactive ion etching, plasma etching, and triode etching. Plasma etching produces an isotropic etching profile similar to wet etching, since plasma chemistry is the dominant etching mechanism.

The plasma processes used for pattern delineation and metal deposition are known to induce various sorts of damage at the SiO₂-Si interface, some of which cannot be annealed out at temperatures compatible with aluminum metallization. The source of the unannealable damage is energetic photons (soft X-rays and vacuum UV) produced in the glow discharges and/or generated by ion bombardment.

The photons are effectively shielded by an absorbing material (e.g., polycrystalline silicon) that covers the gate oxide, except near the edge of the absorbing materials. As device dimensions shrink, eventually the region of the edge becomes a significant fraction of the total gate area (see Fig. 6.3).

Figure 6.2
Schematic representation of the three different types of reactors and
their etching characteristics [2].

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Figure 6.3
Photon (X-ray and vacuum UV) damage around the edges of
polycrystal line silicon gates [9].

So long as there is no metal on the wafers, any incurred damage can be annealed out. Some of the damage caused by these photons can be annealed out at 450°C, but to anneal out all of this damage, the metallization materials will have to be changed to a system that does not permit aluminum to contact silicon at temperatures up to 600°C.

Reactive ion etching produces a straight vertical etching profile, since the dominant etching mechanism is ion bombardment. The need for a controlled profile provided the impetus to develop triode-type reactors, which can produce isotropic and/or directional etching profiles as required. The distinguishing feature of a triode reactor is its ability to control dark-space voltage and hence ion energy relatively independent of plasma chemistry. In a plasma or diode reactor, the energy of the ions is fixed once the power and pressure are defined. Ion bombardment energy in a triode reactor is varied by means of power ratio and phase difference between the two electrodes.

Etch rate ratio or etch selectivity is another major parameter in dry-etching processes. The relative etch rates of the resist and the underlying film must be sufficiently different to accomplish desired etching. Appropriate choice of gas composition, pressure, and flow is as important as reactor chamber configuration.

Reactive ion etching is a means for achieving high-quality etching of advanced devices. The process consists of a chemical reaction this is enhanced by charged particles, mainly ions, bombarding the wafer. The ions also remove nonvolatile etching inhibitors from the wafer's surface and thus permit etching to continue. Since the ions have an inherent directionality normal to the surface of the wafer, under proper conditions the chemical reaction can proceed in only one direction and thus creates an anisotropic profile. By selecting gases properly, the process engineer can establish the different rates of chemical reactions for different materials and can thereby obtain highly selective etch processes.

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Doping TrendsChanges in Diffusion Furnace Usage*

For Diffusion

Horizontal hot-wall diffusion furnaces have been one of the major workhorses of the semiconductor industry for the past four decades, due to their high throughput, low cost, and high reliability, and have provided adequate doping for SSI and MSI circuits. Table 6.5 summarizes the salient features of horizontal hotwall furnaces. Diffusion furnaces were originally used to perform diffusion and oxidation, but with the advent of improved process control systems in the late 1970s, low-pressure chemical vapor deposition (LPCVD) was also possible. Presently, only about 20% of all diffusion tubes sold are still used for the traditional diffusion, predeposition, and drive-in, whereas 5060% are used for oxidation. The remaining 20% are dedicated to the fast-growing LPCVD technologies. For the majority of doping applications, diffusion has largely been replaced by ion implantation. Ion implantation, although more costly, provides much better control over doping parameters, such as junction depth and dopant concentration. In addition, recent improvements in the thoughput of ion-implantation systems make them even more compatible with diffusion furnaces.

There are, however, still several doping processes that are typically done in diffusion tubes. One example is doping steps that require very deep junctions, such as p-wells in CMOS devices. Although high-current ion implanters are being developed to meet this need, diffusion furnaces continue to be used. Other applications, such as driving impurities from doped oxides or nitrides into the silicon, also require the use of diffusion furnace systems.

For VLSI devices, the hot-wall furnace presents problems. These devices need to see a uniform low-temperature, surface-controlled environment. How one obtains this environment is now discussed.

For Oxidation

The major trend in the area of oxidation is the use of thinner oxides, grown at lower temperatures. Gate oxides will decrease in thickness from about 500 Å, currently, to around the 50 Å level in the future. There has also been an increased use of growing oxides at higher pressures, because for every increase above one atmosphere of pressure, the temperature can be decreased by 30°C or the growth rate increased by 100%, as a rule of thumb. Because the temperature can be reduced, a higher quality oxide is formed.

In a diffusion furnace, thermal oxidation of silicon is normally performed in the temperature range 6001200°C, utilizing a dry oxygen, wet oxygen, or

*Portions of this section used with permission from Ref. 3.

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Table 6.5 Horizontal Tube Hot-Wall Furnace Features

Advantages

Disadvantages

Simple equipment
Nonuniform temperature/doping

Longest experience
Doping inaccuracies

Low capital cost
High temperatures required

Large batch/throughput
Defect generation

Low cost per wafer
Prior layers diffuse still further

Oxide formed for next step
Oxide may have to be removed

Long equipment up-time
Large wafer distort or break

pyrogenic steam reaction. High-quality oxide layers can also be deposited by LPCVD, usually by reacting oxygen with silane.

For LPCVD

The deposition of films such as polysilicon, oxides, nitrides, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and tetroethoxysilane (TEOS) by low-pressure chemical vapor deposition (LPCVD) is becoming an increasingly important application of diffusion furnaces. These are also the most complex of all processes performed in diffusion tubes.

Diffusion Furnace Variables

Process Considerations

The uniformity and quality of any process performed in a diffusion tube, whether it is diffusion, oxidation, or chemical vapor deposition (CVD), is affected by a number of variables. These include time, temperature, gas concentration, gas flow dynamics, temperature gradients across and down the tube, ramp-up and cool-down rates, load density, wafer size, and particulate contamination. It is essential to know what aspects of the diffusion furnace can affect these variables, and then precisely control them to obtain maximum uniformity and quality.

Temperature Control

Obviously, the most important variable to control in a furnace system is temperature. A temperature controller must not only be able to provide stable control under steady-state conditions, but it must also be able to provide a flat temperature profile during recovery and thermal overshoot after wafer loading, during gas flow and ramping conditions, and during exothermic reactions.

Precise temperature control involves not only the processing cycles, but also the ramping, heat-up, and cool-down cycles.

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Another factor that affects a diffusion furnace's temperature control capabilities is the type of heating element used. The controller is really the key to the system, but probably the second most important element is the heater element itself. The things that the controller can't make up for almost all reside in the element itselfthe way it's built; the kind of insulation; the length of the element; and the kind, spacing, and mass of the windings used. These things affect how stable and how long the flat zone is going to be, how fast the element can recover, and how much cross-talk there will be between elements.

Gas Control

Next to temperature control, precise control over the reactant and carrier gas flows is of paramount importance. Some equipment manufacturers design and build their own mass-flow controllers, but in most cases use one of the many flow controllers currently offered by a variety of manufacturers. In general, few problems are encountered with-mass-flow controllers in diffusion furnaces, but care must be taken to eliminate overshoot, where a burst of gas is experienced at the beginning of the cycle. This high concentration of gas may cause uniformity problems, and the puff of gas tends to stir up contamination.

IC suppliers would like more process monitoring capabilities than are currently available.

Contamination and Automation

Diffusion furnaces have often been criticized as being one of the dirtiest pieces of processing equipment. Due to fairly recent advances in automated loading and other improvements, this is no longer true. Contamination comes from several areas: the equipment, the people, the process materials, and even the process itself. In the past, a great deal of contamination was generated by the wafer loading system that rolled the quartz boats down the quartz tube. In addition, at high temperatures or during CVD operations, the boats tended to adhere to the process tube, so the boats were oscillated back and forth, producing even more particulates. This problem has been almost totally eliminated with the advent of cantilever and soft-contact loading systems, offered by most manufacturers.

Currently, many manufacturers offer automated wafer handling.

Vertical Furnaces

As wafer sizes get larger and chip geometries continue to shrink, it will be difficult to maintain the necessary temperature uniformity across the furnace diameter. One furnace design alternative that addresses this problem is the vertical furnace. Although vertical furnaces are not new, they have several advantages when applied to semiconductor processing, especially in the area of automation. Vertical furnaces are designed to operate in the semiconductor production environment, such as between the front-end wafer fabrication and etch operations. Normally, those operations are wafer by wafer and the wafer is in the

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horizontal plane. By putting the furnace in the vertical plane, the wafer can be left in the same orientation and the wafers can be automatically loaded into the vertical processing. Table 6.6 compares the horizontal hot-wall furnace with several other furnaces currently being considered for semiconductor doping.

Ion Implantation

Ion implantation will take on a greater roll in the fabrication of VLSI and ULSI circuits in the future. The increased usage of ion implantation is best illustrated by referring to the cross-sectional diagram of a typical CMOS transistor pair shown in Fig. 6.4. This diagram shows device regions currently fabricated with ion implantation as well as those with future potential of being fabricated with ion implantation. Clearly, ion implantation has the potential for being one of the workhorses of the fabrication process. However, some of the historic issues relative to this process step still need to be resolved:

A working charge neutralization method needs to be developed that eliminates wafer charging and oxide breakdown.

The structural integrity of the photoresist must be ensured.

Contamination (sputtered beam-line fragments, prior implants, and the like) must be eliminated.

Residual damage must be eliminated (rapid thermal processing is one method of doing this).

Channeling and shadowing, which are generated with smaller geometry devices, must be controlled.

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Figure 6.4
Application of ion implantation/doping in typical CMOS structure [3].

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Material Technology Trends*

Silicon will remain the primary material for VLSI circuits, except for special niche applications where gallium arsenide will be used, for at least the next decade. This is partly because silicon has a stable oxide that is unique as a diffusion barrier and as a dielectric for MOS gates. It is also because silicon material and wafer processing technologies are so advanced that no other material technology can compete with it in terms of quality and cost of manufacture. It is well known that for a given defect density, the die yield decreases exponentially with the number of components integrated into a single chip. To keep the same yield in VLSI as that in LSI, the defect density in the material has to be decreased. The detrimental crystal defects are oxidation-induced stacking faults and excess oxygen precipitates. A high density of oxidation-induced stacking faults results in the formation of emitter-collector pipes in bipolar transistors and a high rate of leakage current failures in MOS transistors. Excess oxygen precipitates can induce wafer warpage and consequently reduce photolithography yields. Impurity concentration and uniformity affect the performance characteristics of devices. Other material parameters such as surface damage and wafer flatness are also critical to device yield. Thus, silicon material quality must be improved for VLSI circuit developments to continue.

Silicon material quality must be improved at the time that silicon crystals are grown. Currently, the majority of integrated circuits use crystals grown by the Czochralski (Cz) method as starting material and will continue to do so in the foreseeable future. The crystals contain two unintentionally doped impurities, carbon and oxygen. Recently developed techniques eliminate carbon from silicon ingots, leaving oxygen as the major impurity of concern. Typical oxygen concentration in silicon crystals is in the range from 5 × 10¹⁷ to 2 × 10¹⁸ atoms/cm³. The presence of oxygen in silicon contributes both beneficial and harmful effects. The former include hardening of the silicon crystal lattice and prevention of dislocation multiplication during thermal cycling. The latter include the formation of stacking faults and SiO₂ precipitates, which in turn lead to wafer warpage. Since the majority of IC suppliers purchase their starting wafers from outside sources, all that will be said is that two approaches are being taken to solve the problems associated with oxygen impurity. One is to reduce oxygen concentration to less than 7 × 10¹⁷ atoms/cm³; the other is to make beneficial use of the oxygen. Both approaches require controlling oxygen concentration to certain specific ranges.

The crystal growth of quality material is of utmost importance for use in fabricating VLSI circuits. However, it is not the only criterion for producing good devices. Efforts have been and continue to be made to reduce crystallographic defects in materials. The trend will be to control defect distribution. The

*Used with permission from Ref. 4.

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Figure 6.5
Trends in MOS materials technology for VLSI circuits [4].

surface region tolerates no defects, while the bulk region utilizes defects for the purpose of intrinsic gettering.

New material processing technologies such as silicon-on-insulator substrates and silicides require further exploitation. These technologies include laser or strip-heater recrystallization of thin silicon films, epitaxial growth of implanted surfaces, GaAs crystal growth, and thin-film growth by MBE (molecular beam epitaxy). Figures 6.5 and 6.6 summarize some of the key process technologies needed to fabricate MOS and bipolar VLSI circuits, respectively, which will now be discussed.

Insulating Substrates

Parasitic capacitance and carrier mobility are the two most important material properties that affect the speed of devices. The capacitance of a material is

Figure 6.6
Trends in bipolar materials technology for VLSI circuits [4].

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proportional to the square root of dielectric constant and carrier concentration. The intrinsic carrier concentration for gallium arsenide is four orders of magnitude lower than for silicon, suggesting that the capacitance of silicon devices is higher than that of silicon-on-insulating substrates, which is in turn higher than that of gallium arsenide.

The electron mobility in gallium arsenide is considerably higher than that in silicon. Furthermore, enhancement of electron mobility can be achieved in gallium arsenide devices using technologies such as modulation doping and velocity overshoot with a submicrometer gate length.

Parasitic capacitance associated with junction areas and bit lines in bulk silicon can be virtually eliminated if the device is fabricated in a thin silicon film deposited on an insulating substrate (SOI). Sapphire (A1₂O₃), silicon dioxide (including quartz), and silicon nitride have been found to be good candidates as insulating substrates for growing single-crystal silicon films.

Several ways of creating silicon-on-insulator structures were presented in Chapter 5. Other means of fabricating the SOI devices are now presented. Silicon dioxide substrates made of quartz or silicon dioxide thermally grown from single-crystal silicon have been used. The graphoepitaxy process uses fused silica substrates in which grooves are formed on the surface as a surface-relief grating. The squared groove patterns are typically 3.8 mm apart and 0.1 mm deep. A 500-nm layer of amorphous silicon is deposited on the silicon surface using a CVD process. The silicon is then crystallized by heating to its melting point with a laser scan. Recrystallized silicon exhibits polycrystals with a typical grain size of 1 × 10 mm inside the grooves.

Laser heating has also been applied to recrystallization of CVD silicon films on an Si₃N₄ substrate, which is typically 1000 Å thick, deposited on a silicon wafer. Islands of various sizes (2 × 20 mm up to 20 × 60 mm) of Si/Si₃N₄ are created by photolithographic techniques. The thickness of the silicon film is typically 0.5 mm. By laser annealing, the grain size of polycrystalline film is increased from a diameter of approximately 500 Å to a nominal dimension of 2 × 2.5 mm. Large-grain polycrystalline silicon films recrystallized by continuous-wave (cw) laser scanning have been processed to yield MOS devices of acceptable quality.

The use of a scanning graphite strip heater has been a successful alternative to heating by laser scanning. Best results are obtained when the polysilicon film is encapsulated with a composite layer of silicon dioxide and silicon nitride. Crystal growth under this condition produces silicon films with large-grained, preferred (100) orientation. Similar results have been found by using a stationary graphite susceptor heated by a radiofrequency (rf) coil. The trace lines on the surface are subgrain boundaries. The misorientation across each line is very small (<1°C). In essence the film can be regarded as a single-crystal structure.

Another approach to form silicon-on-insulator structures is to deposit a

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silicon epitaxial layer on a silicon substrate that contains a buried oxide layer. The buried oxide is produced by implantation of oxygen ions to a density greater than 1.4 × 10¹⁸ cm⁻². The top surface of the implanted silicon remains relatively free from oxygen. After thermal anneal of ion-implanted damage, a single-crystal epitaxial layer can be grown. The p-n junction diodes built on these materials exhibit low leakage and high breakdown voltage. The drawback of this technique is that obtaining an ion-implanted dose of 10¹⁸ cm⁻² is a time-consuming and expensive process.

The low parasitic capacitance and the high electron mobility of gallium arsenide result in substantially higher operating speeds for gallium arsenide ICs. In addition, gallium arsenide consumes 2540 times less power than silicon for comparable speeds, and the intrinsic defect levels of gallium arsenide wafers have been dramatically reduced. These characteristics make gallium arsenide technology useful in very critical high-performance applications. Additionally, gallium arsenide chips can contain both optical and electronic devices. The integrated optoelectronic chips are not possible with elemental semiconductor materials.

Epitaxial Layer Requirements

Historically, an epitaxial layer has been used in the fabrication of bipolar logic and linear ICs. The problem of alpha particles in 16K DRAMs resulted in the consideration (and use by one IC supplier) of an epitaxial layer in fabricating NMOS ICs to prevent this failure mechanism. Since then it has been applied for many MOS processes (NMOS and CMOS). Furthermore, all ULSI designs, because of their inherent nature, will require the use of an epi layer.

Bipolar VLSI devices use epitaxial silicon deposited on substrates with heavily doped buried layers. The buried layer in the substrate contributes a significant portion of autodoping. One of the trends in bipolar VLSI technology is to shrink the thickness of the epitaxial layer and the base thickness of transistors. Thinner epitaxial layers require reduced autodoping, at least to an extent proportional to the reduction of epitaxial thickness. The pattern shift in the epitaxial layer is also becoming more critical with the shrinkage of lateral device dimensions. The slip induced during the epitaxial growth should be totally eliminated.

Haze or shallow etch pits in the epitaxial layer are thought to be associated with metal impurities in the wafer. Reduction of these epitaxial defects has been achieved by using substrates with high oxygen concentration. Furthermore, silicon grown on denuded substrates exhibits a lower defect density than that grown on a nondenuded substrate.

Advances in epitaxial growth technology have considerably reduced the problems associated with autodoping, slip, pattern shift, and thickness control of thin epitaxial layers. Recent evolution of silicon epitaxy technology includes

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changing from (1) 1-atm CVD to low-pressure CVD, (2) rf heating to infrared radiant heating, and (3) horizontal reactors to vertical or barrel-type reactors.

Currently, a majority of epitaxial silicon is grown by the reaction of SiCl₄ with H₂ at a temperature between 1150 and 1200°C. This is probably the highest temperature step in the overall wafer processing with the exception of buried layer diffusion. The recent introduction of ion implantation and high-pressure oxidation has considerably lowered wafer processing temperature. It is important, therefore, that epitaxial growth be carried out at a lower temperature as well.

The development of low-temperature processes for fabricating integrated circuits has become essential to the continuing development of smaller and faster devices. In particular, a low-temperature process for depositing epitaxial silicon is necessary for future bipolar and CMOS technologies to minimize autodoping and solid-state diffusion effects. When lightly doped epitaxial films are deposited on heavily doped substrates at the high temperatures used by conventional processes, a considerable transfer of dopants from the substrate to the growing films takes place. This transfer results in a transition region extending 1.52.5 mm into the epitaxial layer within which the dopant concentration changes only gradually with position. The existence of this transition region prevents the fabrication of extremely thin, lightly doped epitaxial films.

The transfer of dopants is caused by two mechanisms: solid-state diffusion, which is caused by the random thermal motion of atoms, and autodoping, which is caused by the redeposition of dopants that have evaporated from surfaces in the reactor. By growing epitaxial films at reduced pressure (40100 torr), the arsenic autodoping problem is arrested. However, the most important deposition parameter controlling dopant redistribution is temperature. Therefore, by lowering the deposition temperature, thermal diffusion and impurity evaporation are reduced and thus more abrupt transitions can be obtained. Furthermore, lower pressure and lower temperature reduce pattern shift and distortion and wafer warpage, respectively, both of which create alignment problems for small feature size lithography.

A lower deposition temperature for epitaxial films is mandatory for future processes. There are several ways to perform low-temperature epitaxial silicon growth. These are the replacement of SiCl₄ with HSiCl₃, H₂SiCl₂, or even SiH₄; the replacement of one chlorine atom in SiCl₄ by hydrogen, which will decrease the epitaxial growth temperature by approximately 50°C; and the use of SiH₄ in a helium ambient or at reduced pressure, which can grow epitaxial silicon at a temperature as low as 900°C. However, the lower temperature creates two new problems. In the conventional process, silicon's native oxide is removed in situ at high temperatures to expose the silicon lattice. Next, dopant gases are transported to the wafer surface where they undergo thermally driven chemical reactions. The resulting adatoms, atoms that have been adsorbed on the surface, must then migrate to energetically favorable surface sites to be incorporated into

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the crystalline lattice. Thus, lowering the process temperature complicates the removal of the native oxide and reduces the surface mobility of the adatoms, both of which make epitaxial growth more difficult if not impossible. Then, too, the wafer surface cleanliness is critical to any low temperature epitaxial process. Ion bombardmant has been used to solve these problems.

There are three major effects of ion bombardment on film growth. First, it can be used to sputter contaminants, including the native oxide, from the wafer surface. Second, ion bombardment enhances adatom surface mobility. Finally, ion bombardment can create adsorption sites, thereby reducing the distance the average adatom must travel. These effects are clearly beneficial to a low-temperature process for depositing epitaxial silicon.

Low-temperature epitaxial films have also been grown using silicon molecular beams. Molecular beam epitaxy (MBE) is a deposition process utilizing a molecular or atomic beam in an ultrahigh vacuum. The high vacuum offers the advantage of keeping substrate surfaces free from impurities. This allows MBE to grow high-quality films at a relatively low temperature, typically in the range of 600800°C for single-crystal growth of silicon films. The higher the degree of ionization of these beams, the lower the temperature at which epitaxial films can be grown. Using a completely ionized beam, silicon epitaxial films have been deposited at 125°C. The use of low growth temperature greatly reduces thermal stress due to the difference in thermal expansion that is produced on cooling and can thus reduce resultant dislocations at the interface. Diffusion of dopants and interdiffusion at the interfaces are also reduced by using a low growth temperature. Another advantage of molecular beam epitaxy is the capability to control epitaxial thickness to as thin as several tens of angstroms. This technique has great potential for fabrication of thin bipolar transistors with noncompensated emitters. Also, the concentration profiles of the films grown by MBE are the most abrupt. However, molecular beam deposition technology has yet to demonstrate its utility in a high-volume manufacturing environment.

Plasma-enhanced chemical vapor deposition (PECVD) provides the ability to deposit a thin epitaxial film that is compatible with manufacturing requirements such as high throughput, conformal coverage, and low cost. The plasma, which is generated by a high-frequency discharge at low pressures, can be used to remove silicon's native oxide and to supply ions for enhancing surface mobility and for creating adsorption sites. Furthermore, the plasma contains highly reactive neutral radicals, the presence of which enhances the growth rate and makes the in situ incorporation of dopants into the lattice feasible at low temperatures. Therefore, PECVD, which is performed at low temperatures and pressures, addresses the problems of conventional CVD, while retaining the aforementioned advantages of CVD (i.e., high throughput, conformal coverage, and relatively low cost). However, the PECVD process results in oxygen and carbon contamination of the epitaxial layer, which must be eliminated before the

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PECVD process can be commercially viable for obtaining low temperature epitaxial films. Again, PECVD is a new process technology that must be validated in the manufacturing environment.

Some of these problems will disappear for the IC supplier because many different types of wafers (bipolar, CMOS, etc.) are available with an epitaxial layer of the desired resistivity already grown on the substrate. In this case the problem of obtaining a low-defect epitaxial layer is transferred to the wafer supplier.

Gettering

The role of defects in reducing the circuit yield becomes more important with increasing device density. Thus, successful VLSI fabrication requires the use of starting wafers of optimum quality. Nevertheless, even if fabrication is carried out under completely contamination-free conditions, a number of process-induced defects will eventually limit the circuit yield.

Metallic impurities are often electronically active in both silicon and gallium arsenide. As a result, they reduce device lifetime and increase the leakage current of reverse-biased junctions. Often they degrade the reverse breakdown characteristic, resulting in soft junctions with excess reverse currents at low voltages below their avalanche voltage. Elimination or reduction of impurities is thus important in VLSI applications.

Oxygen and carbon are present as impurities in both starting silicon and gallium arsenide. These impurities usually form complexes in the lattice with the host atoms (silicon, gallium, and arsenic) as well as with impurities in the semiconductor. This, in turn, increases the possibility of forming other crystal defects by creating dislocations at these sites.

Dislocations and stacking faults are also present in the semiconductor. Dislocations are primarily caused by the effect of mechanical stress which is induced during high concentration diffusions, and by rapid cool-down of wafers after high-temperature processing. Stacking faults, on the other hand, come about because of imperfections during epitaxial layer growth, especially at the epitaxial layer-substrate interface. In silicon, these stacking faults can also be created during oxidation (i.e., the oxidation-induced stacking fault). The primary effect of stacking faults is that they act as precipitation sites for metallic impurities, which cluster around them in order to relieve the stress in the lattice. This, in turn, results in degraded junction characteristics, as well as in reduced lifetime.

The purpose of gettering techniques is to remove or reduce these defects (as well as any defects caused by contamination), especially those that are formed in the vicinity of the active devices. Some of these processes remove defects completely; yet others move the defects away from the active region to other areas (the substrate backside, for example) where they have no effect.

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A number of different gettering techniques are used for the removal or reduction of these defects. Some of these are now presented.

Intrinsic Gettering

Silicon wafers, especially those grown by the Czochralski process, contain large amounts of dissolved oxygen. During device processing, this oxygen tends to precipitate in regions of stress, in the form of large clumps 0.11 mm in diameter and about 1 mm apart. The intrinsic gettering process consists of heat treatments to silicon wafers prior to processing. Its function is to precipitate out the dissolved oxygen in a region that is several micrometers below the silicon surface. Heat treatment in the 9001100°C range for 24 h is commonly used for this purpose, and results in removing the dissolved oxygen in a 510 mm layer from the surface.

Halogenic Dopant Sources

Use of these sources during diffusion serves to convert metallic impurities (which are usually fast diffusers) into their volatile halides, which then leave the system by incorporation into the gas stream. These dopants must be used with care, however, since excessive halogen usage can result in pitting of the semiconductor surface.

Chlorine Oxidation

This process is highly effective in preventing the formation of oxygen-induced stacking faults in silicon. It is also effective in removing metallic impurities form the bulk crystal in much the same way as halogenic dopant sources do during diffusion.

Mechanical Damage

Both sandblasting and physical abrasion can be used to create a layer of damage on the back surface of the wafer. During subsequent high-temperature processing, this damage region acts as a sink for the removal of metallic impurities as well as stacking faults.

Controlled amounts of damage can also be introduced by depositing a layer of silicon nitride on the back surface of the wafer. Here the high interfacial stress created by the deposition process results in the formation of a dislocation network, which acts as a getter during subsequent processing. Recently, considerable success has been obtained by the use of ion implantation as well as laser irradiation for this purpose.

Glassy Layers

Both BSG and PSG in contact with silicon at elevated temperatures have been found to be extremely effective in reducing metallic impurities, stacking

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faults, and dislocations in silicon wafers. The effectiveness of these layers is the result of the diffusion-induced stress, which is created well ahead of the impurity diffusion front during heat treatment. In addition, they provide a viscous layer in which it is possible for some of the metallic impurities to become entrapped. Often these glass layers are deposited from a halogenic source, and so have some chlorine or bromine incorporated in them. This further provides a gettering role by chemical conversion of the impurity to its halide.

All of the above methods can be used singly during VLSI circuit fabrication. Often, however, combinations of these techniques are found to give improved results. Moreover, many of these techniques are used at different points in the process cycle.

Multilevel Resists*

With device design rules below 1 mm it is difficult to get high resolution, good linewidth control, and good step coverage simultaneously. Good step coverage can be obtained with a thick resistat the expense of resolution and linewidth control. Higher resolution and good linewidth can be achieved with a thin resist layer but at the expense of good step coverage.

Some multilevel resist schemes demonstrate good resolution, linewidth control, and step coverage, all at the same time. For a two-level structure, a thick photoresist layer is applied to the substrate and coated with a thin layer of organic or inorganic resist. In the three-level technique an additional sacrificial layer, such as silicon dioxide or silicon nitride, is deposited atop the thick organic layer before the working resist is applied. First the top resist is patterned, and then reactive ion etching delineates that pattern into subsequent layers. To get a vertical wall profile, to maintain very good linewidth control, and to avoid side-wall redeposition from substrate sputtering during overetch, care must be taken to choose the right gases and to optimize etch conditions.

Planarization*

Integrated circuit metallization failures occur mainly when the metal does not completely cover the dielectric insulating material, a problem that is caused by attempts to replicate topography from one device layer to another and by the very high aspect ratio of contact windows. It is a serious problem that has become more pronounced as device dimensions have continued to shrink. The surface areas of present-day (1994) state-of-the-art ICs are extremely nonplanar. Consequently, poor metal step coverage, contact misalignment, metal thinning, and metal notching issues must be addressed and resolved to produce high-quality, high-yield products. Complete step coverage of metal over insulating materials will certainly be very difficult to achieve.

*Portions of these sections used with permission from Ref. 5.

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Device suppliers have tried to obtain better metal step coverage with high-temperature (1100°C) phosphor-doped glass reflow, which smoothes the surface topography and contact window steps. But process temperatures in VLSI circuits with shallow junctions or with multilevel metallization structures should be considerably lower. A new planarization technique can, however, replace the standard reflow of phosphor-doped glass.

In this new technique, a thick organic layer is spun atop dielectric materials such as nitride or oxide. Since the organic material has rather low viscosity, flow occurs in the course of the application or during a low-temperature bake. The result is a smooth surface either with gentle steps or with a completely flat surface, depending upon the thickness of the organic material that is applied.

Reactive ion etching techniques then etch the organic and the dielectric layers at about the same rate, so that the profile of the coating organic materials is replicated into the final dielectric layer. The result is a smooth surface. A nitride layer covering an oxide step is made planar by spinning a thick layer of resist.

During planarization, the endpoint between the photoresist and the nitride is readily detected by a laser interferometer. Controlling the relative etch rates of the dielectric materials and the photoresist mask also facilitates anisotropic taper contact window etching, which is just as important as planarization for good metallization. Oxygen plasma is the main source of the photoresist etch, and mixing and controlling the amount of O₂ in the Freon gases that etch dielectric materials is capable of producing the desired results.

For certain kinds of device structures, the taper window etch actually requires a somewhat more sophisticated process. One such structure is a contact window that is opened through a double layer of plasma chemical vapor-deposited nitride and a thick polyimide, with a photoresist used as a mask. The etch rate of each layer must be properly adjusted in order to achieve a slope that is smooth overall, without changing the dimensions of the contact.

Isolation Technology*

Local silicon oxidationwhich uses silicon as an oxidation mask, with a thin oxide buffer layer (for stress relief) between the silicon and nitridehas been the dominant isolation technology for LSI circuits. As device dimensions are scaled down without a proportionate decrease in the thickness of the field oxide, this conventional process will face the difficulties inherent in the silicon's different oxidation rates in the masked and the unmasked regions. Uneven rates of local oxidation produce the well-known bird's beak structure around the perimeter of the nitride mask. Depending on the thickness of the buffer oxide layer, the encroachments formed can be 6090% of the field oxide thickness.

*Portions of this section used with permission from Ref. 5.

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This undesired topography not only deprives the device of space but also creates another problem in the anisotropic etching of the interconnection materials deposited later. Films over steep steps require a significant overetch to clean the inside corners, which are much thicker than the planar area. As VLSI continues to reduce the thickness of the gate oxide, any dry-etching process should minimize overetch of gate oxide, thereby eliminating steep steps.

Recent developments in isolation technology suggest several replacements for the conventional local oxidation process, most important among them a fully recessed process (see Fig. 6.7) and a refilled trench isolation process (see Fig. 6.8). Both require a single-crystal silicon etch. In the fully recessed local oxidation process, the silicon's etch depth is normally below 1 mm. In the refilled trench isolation process, however, the depth is 210 mm, depending on the application. Here, too, the planarization and taper contact window etch processes can be applied after the trench has been refilled with polysilicon or with oxide.

After single-crystal silicon has been etched, subsequent processing and performance will not be satisfactory if the process has not yielded a vertical wall profile, a rounded bottom profile, and a clean, smooth substrate, free of residue and irregularities. All these requirements have been achieved with reactive ion etching techniques and fluorinated or chlorinated etch gases.

Fluorinated plasma can etch nitride and oxide layers in addition to silicon, thus permitting in situ, multistep etching of all three layers in one pump-down operation. This greatly reduces the possibility of defects, since it eliminates additional etching process steps and wafer transfer. The process uses the photoresist as a masking material, since an oxide mask would be etched away. This fact and the selectivityabout 3:1between the silicon and the resist mean that the depth of etching becomes the limitation of the process applications.

For an etch depth of more than 5 mm, photoresist masks are no longer practical. The chlorinated etch-gas process should be used with oxide as a masking material.

VLSI Metallization

Polysilicon has been employed successfully in the manufacture of LSI devices, both as a gate electrode and as an interconnection material. Nonetheless, its resistivity makes it incompatible with the more stringent requirements of advanced VLSI devices. In VLSI technology, device scaling is used to improve chip density and device performance. This results in new and stringent requirements on materials used for gate interconnects, contacts, and metal interconnects.

Device scaling rules, as shown in Table 6.7, can be used for preliminary investigations of reduced dimensions with new gate or interconnect materials.

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Figure 6.7
A recessed local oxidation process using reactive ion
etching [5].

These rules dictate that as geometries are scaled by a factor of 1/k, gate-delay times are reduced by k³. Scaling, while maintaining the conventional operating voltage of 5 V (for example), leads to a k³ increase in power dissipation per unit of chip area. Contact resistance increases by k². Consequently, the intrinsic performance enhancements of scaling cannot be realized without a reduction in parasitic resistance. Or worse, device performance may actually deteriorate since parasitic contact resistance increases so rapidly. For example, polysilicon contact

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Figure 6.8
In the oxide-filled groove-isolation method, reactive ion etching first
etches deep grooves in silicon (a), which is then entirely coated with
oxide (b). Next, a resist is spun on (c), followed by planarization (d)
and tapered contact window etching (e) [5].

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Table 6.7 Device Scaling Rules

Parameter

Scaling factor (k)

Device dimensions

1/k

Gate delay

1/k

Power dissipation

1/k²

Delay power product

1/k³

Line resistance

k

Contact resistance

k²

windows of 0.25 mm² would have a series resistance of at least 160 W. A device can hardly operate under these conditions.

Increased alpha-particle sensitivity is another problem caused by increased parasitic resistance. In order to connect the individual elements of a VLSI chip together, a large portion of the chip area itself has to be used for the wiring (interconnect) structures. Unacceptable time delays result from parasitic resistances that increase with increasing circuit complexity where a large area of the die is covered by interconnect lines. For example, a three-level CMOS gate array with 6000 gates has 40% of its chip area covered by interconnects, while a 20,000-gate device has 80% of its chip area covered with interconnects.

Two methods are being used either singly or in conjunction to reduce the resistance of the gate-level interconnects and provide reasonable access times. The first, a multilevel metallization scheme, permits physically wider and shorter interconnects to be used, a more complex process. The second uses silicides on gates to provide improved interconnect delay-time, contact-resistance, and electromigration characteristics by forming a composite layer of polysilicon on the gate oxide and silicide above the polysilicon. This structure preserves the almost ideal MOS characteristics of the silicon-substrate gate-oxide-polysilicon structure yet at the same time provides interconnection resistance an order of magnitude lower than that of the polysilicon gate.

Thus, metallization is important not only in determining device density, but also in determining device performance. Since the general goal of VLSI is to improve device density and performance, the optimization of the metallization structure becomes an important part of VLSI technology. This includes the interconnect layer, material characteristics, processing, reliability, and manufacturing costs.

And as device miniaturization trends continue, metallization will become even more important. As such, let us now look at some of the key technical issues in greater detail.

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Wiring Complexity*

Wiring complexity originates from the combinational nature of interconnecting two elements. This can be recognized by estimating that for N elements there are N(N1)/2 possible binary connections. When the number of circuit elements on a chip increases beyond about 10,000, wiring can become very complicated.

The previous example does overestimate the number of interconnects, since in practice devices are not wired randomly; instead, circuits on a chip are grouped according to their functions and the placement of various types of circuits is engineered to reduce interconnections.

As device scaling continues to be used, the requirement for interconnects will become increasingly dominant in the design of the circuit layout and the metallization structure. At present, it is already impossible to use all the circuits on some high-density logic chips (gate arrays) simply because some of them cannot be wired properly.

In the design of the interconnect structure, several factors must be considered in order to optimize the device performance.

First, the length of connection should be minimized. This is equivalent to minimizing the RC response time for optimum circuit performance.

Second, the layout should minimize cross-talk to reduce the level of the inductance noise coming from the random switching of individual circuits.

Third, it is desirable to keep all the connections as close to the average length as possible. This reduces random fluctuations of the switching voltage at the contact.

Fourth, the placement of circuits should distribute the power dissipation evenly. This is to minimize the local heating, a problem particularly important for driver circuits.

Finally, the layout should facilitate detection and correction of errors and defects.

An effective approach in meeting these requirements is to use multilevel interconnects such as shown for the bipolar circuit in Fig. 6.9. In this three-level design, all wire tracks in one level run in one direction while those in the adjacent level are perpendicular. Such a structure provides a simple means to minimize cross-talk and the average length of the interconnects.

Even with a multilevel structure, however, the problem is complicated since there are many material and processing requirements that have to be considered or compromised in the final structure. For example, the number of levels can be reduced by packing as many lines as possible on one level. This

*Portions of this section excerpted with permission from Ref. 6.

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Figure 6.9
Multilevel bipolar VLSI circuit cross section [6].

demands high precision and good control of the patterning processes (i.e., lithography and metal etching). The alternative of using more levels can relax the wiring density, but causes problems in other processing areas, such as planarization and topography of interlayer contacts. Such problems will have to be considered in addition to wiring placements.

As narrower multilevel interconnections are used, electromigration causes a problem called hillocks. Small hills of metal are formed, usually on the narrower, lower level, because of the electrical pressure. These hills puncture the oxide between the first and second levels, causing a short circuit. In examining layering techniques, it was found that a composite film of aluminum, silicon, and titanium offered a substantial reduction in hillock density and permitted smooth films with no more variation than 20 Å.

Arsenic ion implants can also be used to suppress hillock formation in multiple-level metallization systems. The method developed not only solves the hillock problem and the shorts it causes, but also the opens caused by electromigration on the upper metal layers.

The majority of gate arrays require two or more levels of metallization to enable the efficient routing of circuit interconnections. This is particularly true of circuits for which the routing is aided by computer. Development of high-density, multilevel aluminum is more difficult for MOS than for bipolar technology because of the more severe topology presented by the gate electrodes of MOS.

An important question regarding multilevel metallization is whether or not to dope the first level of aluminum metallization with copper in order to suppress

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hillock spike formation (see Fig. 6.9). Mixing in copper has presented some problems in achieving fine lines with dry etching; however, if copper is not used, difficult processing techniques are otherwise needed to suppress hillock formation.

As the feature sizes of memory arrays (such as DRAMs, SRAMs, or EPROMs) get smaller it becomes harder to make contact with the self-isolated cells. One approach aims at eliminating the metal contacts, thereby overcoming manufacturing difficulties, lowering defects, and increasing quality. Memories made using the contactless structure are planar and increased in density due to the lack of metal contact.*

Impact of Device Scaling

An interconnect structure provides for four main functions: contact to junctions and gates; interconnection between device cells; interlevel insulation; and connection to input and output signal pads.

As device dimensions are reduced, the enhancements in device density and performance impose certain demands on these functional requirements. In the design of the interconnect structure, these factors have to be considered and optimized. The impact can be assessed from scaling rules. Scaling rules differ for FET and bipolar devices due to different operating principles.

Based on a constant field approximation, the scaling rules for MOSFETs assume that all device dimensions can be scaled linearly. These rules account for the fact that as the device dimension is reduced by a factor of k, its performance as measured by the delay per circuit can be enhanced by the same factor if the dopant level increases by k while the voltage and current decreases by k. On this basis, one can deduce the scaling factor (as listed in Table 6.8) for other parameters pertinent to interconnect metallization, such as resistance, capacitance, current density, and power dissipation.

Scaling bipolar devices is more complicated because their vertical structure and operational principles do not allow scaling similar to that used for FET devices. In addition, the wider spectrum of bipolar circuit design adds further complications in deducing a general set of scaling rules.

Applied voltage is particularly relevant to interconnection scaling. Since the switching voltage cannot be less than the voltage drop across a p-n junction, which is usually about half of the bandgap of the semiconductor (e.g., about 0.6 eV for silicon), scaling of the voltage is restricted. The voltage level used in devices is usually set to be a constant, chosen as a standard by the electronics industry. However, due to VLSI and ULSI geometry requirements and the portable PC industry, a change from the 5-V standard power supply level to 3.3 V is taking

*See Contactless arrays for EPROMs arrive just in time, Electronics, November 27, 1986, for more details.

Portions of this section excerpted with permission from Ref. 6.

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Table 6.8 Scaling Results for Selected Device Parameters

Scaling factor

Device parameter
FET
Bipolar

Device dimension tOX, L, W
1/k
1/k

Doping concentration
k
k

Voltage
1/k
~1

Current
1/k
1/k~1

Delay time/circuit
1/k
1/k

Power density
1
~k-k²

Capacitance
1/k
1/k

Line resistance
k
k

Line response time
1
~1

Line current density
k
~k²

place (1994), and this will again drop to 2.0 or 1.5 V (see Chapter 15). All IC families will be designed to operate from these new reduced voltage levels as each, in turn, becomes the accepted industry standard operating voltage.*

Figure 6.10 shows the effect of voltage scaling by a factor of two (current scaling goes to the industry accepted operating voltage of 3.3 V, not 2.5 V, thus not realizing all of the benefits of this chart) and resolution scaling (1.0- to 0.5-mm feature sizes) on key parameters. As shown, in spite of slightly slower operation (gate delay), the scaled voltage greatly improves the power delay product. Other improvements with a scaled voltage are a reduction of current density and a reduction in oxide field voltage.

The result is lower operating temperatures for a given complexity, which is a major factor for some long-term failure mechanisms. The reduction of current density will minimize the effects of metal migration, while the lower voltages will reduce the chance of hot electron effects and oxide wearout.

It is important that one consider how far scaling rules can be extrapolated without encountering difficulty in device processing or basic physics (see Chapter 15, Fig. 15.50). For example, the minimum switching voltage in FET devices is limited by the noise level and voltage fluctuations generated by random switching and variations in line dimensions. This restricts the lower limit that the voltage level in a FET can be reduced; usually, the gate voltage cannot be substantially below 0.5 V. This causes the scaling of the voltage in FET devices

*For further information see J. W. Mathews and C. K. Erdelyi, Power Supply Voltages for Future VLSI, IEEE Custom Integrated Circuits Conference Proceedings, 1986.

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Figure 6.10
Impact of scaling (scaling from 1 to 0.5 mm).

to stop at a certain level similar to that of the bipolar devices. Also, it is important to note that the epitaxial layer used for all bipolar processes and now beginning to emerge for MOS processes does not scale.

Line thickness is another parameter that cannot be reduced infinitely. Practical thickness is usually not less than about 5000 Å.

Other limitations come from basic device physics that are specifically related to metallization: junction depths, oxide thickness, and current density. In Table 6.9, the probable values of these parameters are summarized for three stages of device scaling.

Table 6.9 Scaling Trends in Device Dimensions

Current density (10⁵ A/cm²)

Period

Line width (mm)

Junction depth (mm)

Oxide thickness (Å)

FET

Bipolar

1970s
36
~1
~1000
0.20.5
0.51

19801985
1.53
~0.250.5
250500
0.51

24

Late 1980s
0.51.5

~0.10.25

100250

12

815

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From Table 6.9, the effect of scaling on device parameters often exceeds that of the scaling factor. This imposes demands on the metallurgical properties in several key areas, such as conductivity, electromigration resistance, power dissipation, and junction stability. Thus, it becomes clear that scaling brings forth a set of requirements for the design of VLSI interconnects, in addition to those from wiring placement.

In general, it is difficult to design a structure optimizing all the necessary factors. A practical approach is to choose a certain combination of metallization and structure to optimize some designed functions of the chip. For example, for bipolar logic circuits, where speed and power dissipation are important, the metallization should be of low resistance and with reasonable cross-sectional area to reduce the current density and joule heating. In contrast, for FET memory chips, where density and reliability are important, the line dimensions should be minimized with the possibility of using thermally stable but resistive refractory metals.

When processing devices with submicron dimensions, new techniques must be used to ensure the quality and integrity of the devices. Some of the pertinent issues are

1. Postdiffusion temperatures must be reduced to 800°C or lower. The use of rapid thermal annealing techniques may be appropriate as an alternate technique.

2. Step coverage will be very important; LPCVD or new techniques will be required for laying doen the metal.

3. Thinner gate oxides (<100 Å) may rule out the possible use of metal directly on SiO₂. Polysilicon alone or with metal or sillicides will be useful.

4. Metals or silicides will not be used at the gate level. They will only be used as interconnections.

5. Multilevel metallization will be widely used.

6. There is an increased trend toward the use of shallow and narrow junctions and contacts to such junctions.

7. New processing concepts and devices will be required.

Reference 12 describes a framework for understanding MOSFET scaling to the 0.09-mm generation technology.

Shrinking Junction Depths

The metallization employed in the fabrication of complex circuits is as profoundly influenced by device geometry down-scaling as any of the other process steps. With increased integration, not only are the lateral dimensions of the metallic circuit elements reduced, but so also are the vertical dimensions of the electrically active regions of the device components. This dimensional shrinkage has two important implications:

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1. Smaller design rules result in reduced line width without a concomitant reduction in interconnect length. For a constant interconnect length, reduction in the RC time constant is most readily achieved by a reduction in the sheet resistivity of the metal interconnect; thus, the choice of interconnect material can have a dramatic effect. For a given acceptable delay, the interconnect may be an order of magnitude longer if a silicide (TaSi₂) rather than polysilicon is employed, simply because of the difference in sheet resistivities between the two compounds.

2. The reduction in vertical dimension imposes severe constraints on the extent of permissible interaction between metal and semiconductor.. At the extreme, this interaction may locally penetrate throughout the electrically active junction region; junction shorting in aluminum contacts to silicon is the classic example. Thus, very shallow junctions can lead to spiking shorts. The traditional aluminum plus 1% silicon remedy for spiking shorts cannot be used because of radiation damage involved during plasma etch and high contact resistance. Furthermore, as junction depths approach 1000 Å, aluminum with 1% silicon, as conventionally deposited, would not prevent shorts in any case, due to silicon-segregation effects. For a variety of reasons, the solution to this problem is the use of a refractory metal alloy as the material in direct contact with silicon.

In the formation of an ohmic contact at elevated temperature, silicon from the substrate must be consumed to form a silicide with a deposited metal. The amount of silicon consumed is related to the sintering temperature, sintering time, and thickness of the metal film. As junction depths decrease, even refractory metals would consume the entire thickness of the contact pocket. This requires one to reduce the amount of metal reactant available. At first glance, this would appear easy to do simply by decreasing the metal thickness. However, for junction depths of 0.1 mm or less this would necessitate reducing the metal thickness to about 100 Å or less. Such thin films are very difficult to control and are usually discontinuous. The discontinuities reduce the contact area, and thus increase the contact resistance.

There are two possible solutions to this problem. First, one could use an alloy of two refractory metals, one constituent of which can form an ohmic contact at the anticipated annealing temperature while the other component cannot. The latter acts as a diluent and may also act as a diffusion barrier. This allows thicker films to be deposited, which can be better controlled and which are continuous.

A second approach is to codeposit a refractory metal and silicon in the form of a metal-rich silicide. Shallow contacts can thus be formed by providing some of the silicon for the reaction in the deposited film. The resultant structure is shown in Fig. 6.11. Note that in this figure, the diffused layer is depicted as

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Figure 6.11
Shallow junction contact metallization [9].

perfectly parallel to the device surface. In actuality, this is difficult to achieve due to enhanced dissolution effects near the edges of contact holes. If, in the formation of a silicide contact, the diffusing species is silicon, then it is usually observed that more silicon is dissolved near the contact edge. This excess silicon diffuses up onto the metal over the surrounding oxide in order to fulfill the solid-solubility requirements of silicon in the metal there. The void left by dissolved silicon is filled with metal, which can lead to spiking shorts in shallow junctions as shown in Fig. 6.12.

Table 6.10 lists the materials commonly used for making gate interconnections and contacts for VLSI devices.

Figure 6.12
Spiking shorts in shallow junctions due to excess silicon dissolution near
contact edges [9].

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Table 6.10 Typically Used Interconnection Materials

For gate

For contacts

Tungsten
TiSi₂
Selective metal (e.g., tungsten)

TaSi₂
Nitride/carbide

Molybdenum
WSi₂
Alloys, TiW

MoSi₂
Silicide

Aluminum
CoSi₂
Silicide diffusion barrier

PtSi

Table 6.11 lists the conductors and diffusion barriers most widely used in multilevel interconnection technology. The materials can be divided into groups based on their electrical resistivity (metals, silicides, silicon) or on their thermal stability (high to low temperatures). The table also lists the more common deposition schemes used. The delineation of the conductors can be done by additive (lift-off), subtractive (wet or dry etch), or selective or self-aligned

Table 6.11 Materials for Contact and Conductor Metallization

Material

Deposition

Electrical resistivity (W/cm)

Delineation

Comments

Al alloys (Si and Cu 5% total)

Evaporation Sputtering

36

Dry etch
Wet etch
Lift-off
Low stress, good adhesion

Cu
Evaporation

23

Lift-off
Wet etch
Low stress, poor adhesion

W, Mo
Evaporation Sputtering, CVD

515

Dry etch
High stress
Refractory

PtSi, PdSi2
TiSi2
TaSi₂

Sputtered and metal + silicon +

2835 25

Selective
Selective and dry etch

High stress
Refractory

WSi₂
CVD

5055 30100

Poly Si
CVD

500

Dry or wet etch

TiW
Sputter Reactively

100

Dry or wet
Diffusion

TiN
Sputter Reactively

40

Dry or wet
Barriers

Cr-CrOx
Evaporate

Lift-off

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techniques. The definitions are self-explanatory. The lift-off and reactive ion etch of conductors are most widely practiced with Al-based conductors. An example of a self-aligned process is PtSi formation at the contacts. The selective process is one in which the material is deposited or grown selectively in a desired area because of the difference in surfaces: An example of this is selective CVD of tungsten. The structure of the films (e.g., grain size and orientation) is determined by deposition conditions and can impact electromigration and etchability. The selection of the process for delineation restricts the choice of the material/deposition process. For example, lift-off techniques allow only evaporation methods but do not limit one to any metallurgy so long as the thermal conditions experienced by the wafer are below the lift-off stencil capabilities. On the other hand, subtractive processes allow the freedom of deposition, sputtering, evaporation, or CVD, but restrict the choice to those that can be wet or dry etched. The section on Silicide Interconnect Materials, discusses the variously used deposition techniques in greater depth.

Note that if a refractory metal alloy or silicide contains a material that cannot be plasma etched (e.g., Pt), this layer will have to be patterned by lift-off techniques.

Tungsten films possess several desirable properties for use as interconnect layers. Among these are a high melting point, high reaction temperature with silicon, low electrical resistivity, low reactivity with aluminum, and high resistance to electromigration. These properties, coupled with the ability to be selectively deposited using CVD, provide for a number of self-aligned structure usages. Additionally, selective deposition of tungsten onto aluminum and metal silicides is widely used.

Four basic areas of application exist for self-aligned tungsten (W) films as shown graphically in Fig. 6.13.

1. Contact material (lower sheet and/or contact resistivity, plasma etch barrier)

2. Diffusion barrier (Al/W/Si, Al/W/MeSix/Si)

3. MOS gate/interconnect (lower resistivity, polysilicon shunt)

4. Multilevel metal connections (contact or via filling)

Tungsten is gaining increased use as a first-layer metal because of the following advantages:

Electromigration and hillock elimination

Greater than 95% conformality

Low contact resistance to n⁺ silicon

High-temperature processing

Planarizes contacts

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Figure 6.13
Schematic illustrations of application areas for selective
tungsten (W) films.

Page 273

Figure 6.14 shows the process steps for accomplishing a selective tungsten (via) contact fill, and Fig. 6.15 is an actual cross section of a dual-metal, dual-passivated structure employing a tungsten barrier layer with tungsten vias.

Silicide Interconnect Materials

Scaling increases contact resistance while reducing junction depth (Tables 6.7 and 6.8). This affects both Schottky diodes and ohmic contacts, although each has a different reliability requirement because of its specific circuit function. For a typical 3 mm × 3 mm contact with a dopant concentration of 10¹⁹ atoms/cm², contact resistance is about 10 W. Contact resistance increases to 100 W when contact size is reduced to 1 mm × 1 mm.

Resistance increases of this magnitude can degrade switching time and reduce voltage swing, thus affecting normal device operation. Since the increase is nonlinear with scaling, the problem becomes very important for submicron junctions.

The usual remedy for high-contact resistance problems is to increase dopant concentration. This has led to extensive study of shallow contacts with high dopant concentration. Of particular interest are reliability concernsthe thermal stability of the contact and the change in the dopant during processing.

It has been recognized that the usual method of using aluminum to form junction contacts has severe limitations for contacts as shallow as 0.25 mm (Table 6.9). The difficulty comes from aluminum penetration of the junction due to the formation of aluminum spikes caused by silicon dissolution to aluminum. This has led to the use of silicides to prevent aluminum penetration of junction contacts.

Silicides are compound phases usually formed by reacting a deposited layer of transition metal with silicon. A silicide has two important advantages for forming junction contacts: the formation of a silicide establishes a silicide-silicon interface below the original metal-silicon interface that is free of processing defects and contaminates, and the amount of silicon consumption can be limited by restricting the annealing, so silicides can be used to form contacts to shallow implanted junctions.

In addition, silicides have several other characteristics that make them useful:

Some have electrical conductivities exceeding heavily doped polysilicon by orders of magnitude.

They can be oxidized.

Different metals can be used to form silicide Schottky diodes with barrier height varying from 0.5 to 0.9 eV.

The combination of these material characteristics extends the use of silicides beyond contact metallurgy into other VLSI applications. Notable are

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Figure 6.14
Selective tungsten via fill.

Page 275

Figure 6.15
Tungsten via technology.

the uses of silicide for interconnecting lines, the incorporation of low- and high-barrier diodes in Schottky transistor logic circuits, and the combination of silicide with polysilicon for self-aligned bipolar contacts and MOS gates.

The use of silicides is not without metallurgical problems, however. Particularly relevant are problems associated with thermal degradation of a sillicide contact and reliability problems associated with stress generated due to silicide formation.

Thermal degradation is a particular concern for an aluminum-silicide-silicon (Al/silicide/Si) structure when subject to postmetallization annealing. The

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Figure 6.16
Cross section of silicide contacts to a bipolar IC.

mechanism was found to be caused by the phase instability of silicide in contact with aluminum, which leads to precipitation of silicon (p-doped by aluminum) on the silicon substrate, causing changes in the junction characteristics. This necessitates the use of another barrier to protect the silicide layer from reacting with aluminum. An effective approach is to incorporate a thermally stable intermediate layer, such as titanium nitride (TiN) or titanium-tungsten (TiW). An example of the use of TiW in a bipolar device with PtSi (platinum silicide) contacts is shown in Fig. 6.16.

The problems of gate metallization differ from those of contact metallization because the gate metal is not in contact with silicon. Since circuit density is important for FET devices, the problem of patterning a dense interconnect structure with planarized morphology is of concern. There is also a need to reduce the resistance of the polysilicon gate line to improve switching time.

Gate-Level Interconnection*

Refractory metal silicides of tungsten, titanium, molybdenum, and tantalum (Table 6.12) are the prominent materials being used for gate interconnect applications.

The annealed resistivity of refractory metal films is in the range of 3060 mW-cm (compared to >500 for polysilicon). The possible methods of depositing silicides include both physical vapor (i.e., evaporation and sputtering) and chemical vapor deposition.

The properties of the various silicide films vary with the deposition technique (Table 6.13). Currently one of the only reliable CVD processes available is for tungsten silicide. Using a cold-wall low-temperature type reactor, the tungsten silicide is deposited between 360 and 400°C.

*Portions of this section are used with permission from Refs. 7 and 8.

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Table 6.12 Comparing Silicide Resistivities

Silicide

Formed by starting from

Sintering temperature (°C)

Resultant resistivity (mW-cm)

TiSi₂
Metal on polysilicon
900
1316

Cosputtered alloy

25

ZrSi₂
Metal on polysilicon

3540

HfSi₂
Metal on polysilicon

4550

VSi₂
Metal on polysilicon

5055

NbSi₂
Metal on polysilicon

50

TaSi₂
Metal on polysilicon
900, 1000
6070

3545

Cosputtered alloy
900 or 1000
5055

CrSi₂
Metal on polysilicon
700
600

MoSi₂
Cosputtered alloy
1000
100

WSi₂
Cosputtered alloy
1000
70

FeSi
Metal on polysilicon
500
150200

FeSi₂
Metal on polysilicon
700
>1000

CoSi₂
Metal on polysilicon
900
1820

Cosputtered alloy

25

NiSi₂
Metal on polysilicon
900
50

Cosputtered alloy

5060

PtSi
Metal on polysilicon
600800
2835

Pd₂Si
Metal on polysilicon
400
3035

One of the advantages of CVD deposition of tungsten silicide is the ability to tailor film resistivity. In addition, the associated anneal cycles required to sinter deposited films affect film properties and composition (e.g., sheet resistance, and water vapor and oxygen content). Accordingly, the choice of a silicide becomes a factor in the thermal processing budget for a given VLSI process.

Most MOS processes now use a polycide structurea refractory metal silicide and polysilicon sandwich layer as shown in Fig. 6.17to retain many of the attractive interface qualities of polysilicon. There include good adhesion, high interface stability, and good ohmic contactswhile reducing sheet resistance as much as 10-fold. The fabrication process is essentially identical to the polysilicon gate process, except polysilicon and silicide (or the metal element of the silicide) layers are deposited sequentially. A high-temperature cycle is added for annealing.

Metal shunts (predominantly tungsten and tungsten silicide) retain more of the advantages of polysilicon than do polycide shunts and have a lower sheet resistance. Polycide shunts, however, require minimum process changes from

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Table 6.13 Refractory Metal Silicides and Selected Characteristics

Resistivity (mW-cm)

Silicide

Minimum annealing temperature (°C)

Co evaporation

Co sputtering

CVD

Process compatibility

MoSi₂

1000

40

100

120

Resistant to acids and alkalis Dissolves slowly in HF Dissolves in HF + HNO₃ Selective etchant NH₄OH:H₂O₂

WSi₂

1000

30

70

40

Resistant to acids and alkalis Dissolves slowly in HF Dissolves in HF + HNO₃

TaSi₂

900

80

50

38

Resistant to acids and alkalis Dissolves slowly in HF Dissolves in HF + HNO₃

TiSi₂

800

21

25

18

Soluble in HF Selective etchant NH₄OH:H₂O₂

silicon-gate technology. The use of pure refractory metal for gates has been complicated by poor adhesion to gate oxides, the integrity of the thin gate oxides, the need for formation of an oxide layer on the pure refractory gate, low-temperature processing, and the troublesome etching required after deposition on the metal-polysilicon sandwich. A highly selective tungsten CVD process is one means of eliminating the etching step.

Figure 6.17
Polycide structures enhance gate interconnection capability by reducing resistance [7].

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A refinement to the application of silicides as an interconnect material involves the formation of silicides on polysilicon gate interconnects and all diffusion contact areas, simultaneously. This is the self-aligned salicide structure (Fig. 6.18). Salicide processing reduces device series resistance or the combination of contact and diffusion sheet resistance, and enhances interconnect.

Salicide processing does involve a few extra steps, including the formation of sidewall oxide spacers; it is not as straightforward as polycide processing. Metal is deposited, at the right temperature and in the right atmosphere, followed by a suitable anneal cycle to form a silicide on the polysilicon and diffusion areas. Selective etching removes residual metal, but not the silicide. The process involves no additional masking.

The advantage of salicide technology is that it takes full advantage of submicrometer device performance by reducing both contact resistance and diffusion sheet resistance.

Device-Level Interconnection

Interconnection at the device level poses its own set of requirements, notably resistance to electromigration at high current densities, uniform step coverage, minimal hillock formation, resistance to corrosion, good ohmic contact, and good bondability. For the immediate future, aluminum alloys have the edge.

As line widths shrink below 1 mm, several shortcomings appear: aluminum's limited current-carrying capability, its less than completely stable

Figure 6.18
Salicide structures are fabricated by simultaneously depositing a metal silicide over gate
interconnects and diffusion contact areas [7].

Page 280

contact with silicon, and its tendency to corrode. Some improvement of contact and electromigration problems has been achieved through the use of better cleaning techniques before metal deposition and the use of barrier layers deposited between metal and silicon layers, but still limits are reached. High contact resistance can degrade a VLSI design by resulting in cross-talk, infrared voltage drops, and increased RC time delays and power consumption.

Each of the alternatives to aluminum has its own drawbacks, but, as at the gate level, refractory metals, especially tungsten, appear to have the most advantageous properties. Although the resistivity of tungsten is higher than that of aluminum, its advantages are enhanced step coverage, lower contact resistance to n⁺ silicon, higher electromigration resistance, and low susceptibility to hillock formation.

Integrated circuit suppliers have chosen to use those silicides most appropriate for their particular needs. One IC supplier has chosen platinum silicide as an interconnection metal because it permits the formation of Schottky contacts and it forms a metal-rich silicide instead of a disilicide. Another supplier has used a silicon-rich phosphorus-doped molybdenum silicide film for LSI circuit structures because this combination helps reduce the problems at the interface where two dissimilar materials touch.

In addition, phosphorus doping permits the deposited silicide to dope the contact region on the substrate during the annealing stage, thus eliminating the need to predope the contact area. Phosphorus atoms can move from the silicide to the silicon. Also, the silicide offers better resistance to the oxidizing ambient and chemical reagents and thus overcomes the problems that pure molybdenum or tungsten would face. The silicide also forms a good ohmic contact to the silicon, since the phosphorus prevents the formation of a highly resistive layer at the silicide-silicon interface during high temperature annealing. However, phosphorus can be a source of contamination and corrosion if not carefully controlled.

Dielectric Interconnections

Just as important as the interconnections are the insulators used to separate the conducting layers from the substrate and from each other. They should be crack resistant and low in stress with minimum defects to provide smooth, conformal films. Low deposition and annealing temperatures are preferred, and the film should act as a barrier to impurity transfer and should have a low dielectric constant to minimize line capacitance effects. SiO₂ is the most common insulating material, because it is very easy to work with and easy to control. Many suppliers are trying to reduce the oxide thickness to decrease the time it takes to create the oxide. This produces a more planar structure for the second or even third level of interconnection, reducing the step coverage problem of the interconnection material.

Table 6.14 lists some of the more commonly used insulators, some

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Table 6.14 Materials for Interlayer Insulation

Insulator

Deposition process

Dielectric constant

Thermal expansivity × 10⁶

Stress (dyn/cm²)

Comments

SiO₂
Sputtered rf
4
0.3-0.5
1-2 × 10⁹ compressive
Excellent ionic, H₂O barrier

PECVD
(200-400°C)

SiNx

SiOx

Oxynitrides

Popular gases are
SiH₄, CO₂,
SiH₂Cl₂, NH₃, N₂O, N₂
6-9
4-5
6-9
2.5
0.5

Tensile to compressive depends on deposition conditions

All PECVD films are conformal oxynitride with improved thermal characteristics

BPSG

Above and PH₃, B₂H₆

4-5

Tensile
Reflow for planarity

LPCVD

Si₃N₄

Silane, NH₃
6-7
4
Tensile 10⁹ to 10¹⁰
Fair step coverage

SiO₂

Silane, N₂O
4
0.4

Zero permeability

Polyimide
Spin and cure
3.5
20-70
Low tensile
Hygroscopic; fast Na mobility

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properties, and their deposition conditions. The principal candidates for interlevel dielectrics are various doped oxide films prepared by the low-temperature CVD oxidation of silane (silicon dioxide) and oxide, nitride films prepared by plasma-enhanced CVD, and polyimide because of its ability to improve planarity. Companies are placing nitride films over silicon dioxide films to form a dual-layer thin insulator in 256-kbit dynamic RAMs. Nitride offers a higher dielectric constant than SiO₂, which means that a layer of the same thickness will provide a higher capacitance for storing the electrons in the cell. Thus even if the cell size is reduced, capacitance can remain about the same if nitride oxide or pure nitride is used as the insulator between capacitor plates. Plasma films have shown reduced defect densities (both pinhole and particulate), conformal step coverage, and improved resistance to cracking due to their compressive stress as opposed to the tensile stress displayed by CVD SiO₂ films, and represent a possible alternate dielectric material.

Thin dielectric layers are used as the charge storage mechanism for UVEPROMs, EEPROMs, and FLASH. In operation the insulators of these devices are subjected to high electric field stress due to the high voltages used for programming and erasure. Thus, the quality of these insulating layers is critical for device reliability. Insulator defect density (both pinhole and particulate) is the primary source of endurance-related failures of these devices. Suppliers of these devices use overvoltage stress of the insulators, an erase/program stress sequence, and a sensitive degradation detection test to prevent parts with insulator defects from being shipped to the user.

The organic insulators have been grouped under one generic name, polyimide, even though a wide variety of polyimides are available with a range of (desirable) properties with regard to planarization, gap filling, adhesion, and glass transition temperatures. The attractiveness of polyimides is their low-cost and low-temperature processing, in addition to their natural planarizing abilities. The major concerns with the use of polyimides are that they are hygroscopic, rapidly permeable to ions, and have low thermal conductivities. The film stresses are low, normally 10⁸ to 10⁹ dyn/cm² (tensile). Polyimides are used in several interconnect strategies for interlevel passivation either at all levels or at the top levels.

The major processes used for deposition of inorganic insulators are sputtering (biasSiO₂) and low-pressure CVD (high temperatureSiOx, SiNx, BPSG, etc.). The properties of all CVD films are influenced by the choice of the reactant species, gas composition, pressure, flow temperature, and, in the case of PECVD films, by RF power and frequency.

Barriers and Contacts

The evolution of an extremely diverse assortment of metallization systems and structures for Schottky and ohmic contacts, and for interconnection metallurgy,

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has essentially been driven in response to the added constraints placed on the metallization by this geometry down-scaling. Implicit in these sometimes complex multilevel metallization structures is the need for creation, through metal deposition, of barrier layers that will permit each individual metal film to perform its intended function while maintaining its integrity during subsequent device processing steps, or at elevated temperatures during device operation. An example of a barrier layer is the copper-nickel-gold contact structure in which nickel is used as a barrier to prevent gold-copper diffusion as well as to strengthen (mechanically; see Chapter 14) the structure. As another example, silicide-gate and interconnect metallization finds current widespread use in VLSI technology. Since the metal silicide compounds may react with second-level aluminum metallization at relatively low temperatures (PtSi and Pd₂Si react with aluminum at temperatures of 250300 and 300°C, respectively), diffusion barrier layers are frequently required to prevent this reaction. The most widely used barrier material for this application has been the alloy titanium-tungsten (TiW).

Specifically, tungsten has been demonstrated to be an effective diffusion barrier because of its low reactivity with aluminum and its ability to limit silicon diffusion, preventing problems associated with shallower junctions and smaller contacts. Selective low-pressure CVD deposition of tungsten is typically performed on exposed silicon areas using a tubular CVD reactor operating at 300400°C with tungsten hexafluoride and hydrogen. Deposition of 1500 Å of selective CVD tungsten has been shown to completely eliminate silicon migration at the contact interface under stress conditions of 10 mA at 250°C.

A large number of other compounds have also been investigated for diffusion barrier applications; among them, the transition metal nitrides, carbides, and borides are some of the most promising.

A diffusion barrier is defined as a thin-film metallization layer inserted between either two other metals or between an overlying metal and an underlying semiconductor substrate material. The barrier extends the lifetime of the resultant contact structure by retarding interdiffusion or by resisting the tendency for chemical reaction to form a new phase between the adjoining materials which the barrier separates. Either mechanism, if unimpeded, has the potential for modification or even destruction of the contact structure as well as the electrical characteristics and performance of the associated device structure. Diffusion barriers have been categorized according to the mechanism by which they prevent or retard the diffusion process: passive barriers, sacrificial barriers, and stuffed barriers. They are illustrated in Fig. 6.19.

The passive barrier, probably considered to be the ideal diffusion barrier, operates because it has a tendency to be chemically inert or nonreactive with the two materials that it separates. The sacrificial or reaction barrier operates by the principle that it may react with the materials that it separates but at a predictable rate, which is sufficiently slow that the barrier's expected lifetime exceeds the

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Figure 6.19
Schematic drawings of three major diffusion barrier types.

calculated performance lifetime of the device in which it is incorporated. The stuffed barrier succeeds because the fast diffusion path (i.e., the grain boundaries) is filled with some other material and is rendered inoperational.

Selective tungsten complete contact filling has been demonstrated for silicon contacts on aluminum vias for multilevel structures. This filling technique results in partial planarization and tighter critical dimension control for VLSI processes. The aspect ratio and slope of the contact play a major role in contact filling. Because of the 1:1 step coverage achieved by CVD techniques, contact width must be equal to or less than twice the film thickness for complete contact filling.

Electromigration

As the metal lines get thinner, the migration of metal under voltage stress gets to be a problem because shorts and opens are possible. Electromigration is the movement of atoms, induced by the passage of a direct current, in a metallic conductor. Its magnitude is determined by atomic diffusivity and current density. Current density is related to the driving force. The formation of electromigration damage (i.e., opens or shorts in a metal line) requires local divergence of the mass flux. This can be generated by various types of inhomogeneity, such as those from grain size, local heating, and stress gradient.

With regard to electromigration, the main impact of scaling is to increase the current capability requirements of interconnecting lines. This problem has two basic aspects that arise from the increase in the current density and the reduction in device dimensions.

Current density (J) increases linearly with FET size reduction and increases even more so for bipolar devices (Table 6.8). For example, FET design current densities have climbed from 12 × 10⁵ A/cm² (Table 6.9) to the present 46 × 10⁵ A/cm² (for 0.5-mm geometries with 0.5-mm interconnects and 46 layers

Page 285

of metal) and are expected to climb to 1 × 10⁶ A/cm² by the year 2000 for 0.25-mm interconnects.

With the increase in the current density, there are effects due to joule heating, which increases by J² dependence. The amount of heating can increase by 100 to 1000 times according to the projected current densities. Since an isolated metal line can carry only about 10⁴ A/cm² before melting, the joule heating generated in a line carrying 10⁵ A/cm² must be almost completely removed through the substrate and the passivating overlayer.

The requirement for cooling will lead to a situation that at ~10⁶ A/cm² any imperfection in the substrate (e.g., processing defects or poor adhesion) can cause a thermal runaway to destroy the line. Even without such a catastrophe, the heating effect due to such high current densities will increase the rate of electromigration, resulting in a significant reduction in lifetime.

The other electromigration problem that results from size reduction is geometry related and caused by scaling into the submicrometer range. For metal films, it is generally observed that the grain size is about the same as the line thickness. For a 1-mm-thick film (the common thickness of interconnecting lines), only a few grains span across a 13 mm wide line.

At the device operating temperature, the electromigration flux is confined to grain boundaries. With a small number of grains across the line, each individual divergent site in the grain structure becomes potentially more damaging, since a line can fail without requiring a statistical linkage of several divergent sites, as would be the case of a line many grains across. This shortens the conductor lifetime while increasing the randomness of the failure statistics (i.e., increasing the statistical deviation sigma in the lifetime). This effect adds considerable uncertainty in predicting the lifetime under operating conditions from accelerated life tests.

Another effect due to the increase in the grain size to line width ratio is a decrease in the role of grain boundary in mass transport. Particularly for multilayer structures, scaling in the line width causes a reduction in the grain boundary area per unit line length. This increases the relative contributions to mass transport through surfaces and interfaces. Since these structures have diffusivities generally exceeding those of grain boundaries, the total electromigration rate will be increased accordingly.

Two aluminum-based metallurgies have been developed for fine lines below 2 mm. One is based on a grain structure of AlCu (aluminum-copper) metallurgy. Using a low copper concentration (12%) and suitable annealing conditions, aluminum lines with bamboo-like grain structure can be formed. (The addition of copper allows a current density increase by a factor of two.) With the grain boundary placed normal to the current flow, grain boundary electromigration is greatly reduced. Also, 1% silicon is normally added (as well as Cu) to the aluminum to prevent junction spiking. A higher concentration of

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silicon (46%) causes silicon nodules* to develop at oxide steps, resulting (eventually) in an open circuit. The solution is to use a barrier metal system.

The other approach incorporates an aluminum transition metal intermetallic sandwich layer in the AlCu structure. This intermetallic compound, which is formed by reacting aluminum with a thin layer of transition metal (e.g., chromium and titanium), improves the AlCu grain texture and also serves as a barrier for void linkage of the top and bottom AlCu layers.

A passivation coating of glass or nitride will slow the electromigration. In fact, it has been found that nitride, because of the stress it places on the substrate, is more effective as a die coating than are glass coverings.

Silicide Processing

Evaporation

At one time the coevaporation of tungsten silicide was considered as a standard of performance. However, future use of evaporation for the deposition of silicide material seems limited. The precise control required to physically deposit both materials during coevaporation is difficult, when compared to recent advances in sputtering and chemical vapor deposition. Furthermore, the large evaporation chamber and source-to-substrate distances of evaporation mean more inclusion of background gas (which cannot be kept low in an evaporator) in the film, and the inherent planetary motions of evaporation produce too many particles. It is also impractical to completely automate evaporation, which is an increasing requirement in VLSI.

Sputtering

Sputtering in silicide applications can be done by cosputtering from two sources (one the metal and the other silicon), sputtering from a single composite source (the metal plus silicon), or sputtering from a single compound source (the metal silicide).

Cosputtering options include depositing the two materials simultaneously (i.e., mixing them in the deposition chamber) or depositing alternate, repeated fine layers (in the 120 nm range) of each material (closely spaced cosputtering). In either case, the actual silicide is formed in a subsequent high-temperature (8001200°C) sintering step.

The advantages of cosputtering include control of film composition independent of the source, and the capability to deposit an initial or final thin silicon layer if desired. In addition, codeposited silicide layers can be formed

*See T. Tatsvzama et al., SI Nodule Formation in Al-SI Metallization, 23rd Annual Proceeding, 1985 Reliability Physics Symposium, for more detail.

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over silicon dioxide or silicon and will not consume any substrate silicon when the deposition ratio is correct.

One of the biggest concerns with sputtering is the inclusion of oxygen and other impurities from the source and from the background gases of the sputter chamber. This means that background residual gas levels in sputtering systems are extremely important.

Except where coevaporation was used, early development of silicide application was performed using cosputtering due to the ease with which the process and film properties could be controlled. Cosputtering, however, has become somewhat difficult to develop into a high-volume production technique. This has led to emphasis on single sources (targets) for silicide deposition with sputtering. Composite pressed targets are composed of precise mixtures of a refractory metal and silicon (unalloyed fine particles of metal and silicon) mixed uniformly and sintered at high temperature under high pressure to a density of approximately 7080%.

When first developed, these composite targets had a reputation of being a source of contamination that was detrimental to silicide film properties. For example, their large surface area was thought to adsorb contaminants, and voids in the pressed target were believed to contain gases that produced local arcing and the ejection of fine droplets of target material.

Composite targets also have the potential of becoming either silicon or metal rich if the sputter yield of either of these constituents is not properly controlled (a function of equipment design).

Now the use of composite targets has met with some success, which enhances the capability of single-wafer sputtering systems.

Compound targets are made of a single silicide material. An initial problem in the development of compound targets was the control of impurities from silicides. However, by careful control of the synthesis of a silicide, impurities have now been reduced to satisfactory levels. This has led to film resistivities equal to those obtained with cosputtering. These targets also enable the blending in of excess silicon during the target manufacturing process. Excess silicon is often desired to prevent stoichiometry changes during deposition and to aid in subsequent oxidation of the silicide.

Chemical Vapor Deposition

For many years in semiconductor processing, chemical vapor deposition (CVD) has been the source of high purity films of silicon nitride and silicon dioxide with excellent control of film conformality. Thus, it is a natural processing technique to consider for the deposition of conductive films. CVD holds the most promise of becoming the standard method of depositing TiSi₂ and WSi₂ films because of the purity of the films it provides, the conformality of the

Page 288

Figure 6.20
Schematic cross section of the final metallized structure [9].

step coverage, the ability to achieve spatially selective deposition, and the low resistivity of the materials.

Typical VLSI Metallization Systems*

This subsection describes a typical VLSI metallization system made up of the constituent elements discussed previously: gate metallization, interlevel dielectric, interconnect metallization, and multilevel metallization. The complete structure is shown in Fig. 6.20.

Gate Metallization

First, a doped polycrystalline silicon layer (30005000 Å) is deposited by LPCVD. Over this, approximately 2000 Å of a refractory metal silicide is deposited by cosputtering of silicon and the refractory metal. In cases where the polysilicon lines must go over steep steps, the refractory metal silicide will need to be bias sputtered. The structure is then annealed at a temperature appropriate to the formation of the silicide employed (typically 8001000°C). Both the silicide and the underlying polysilicon are then plasma etched.

Interlevel Dielectric

The refractory metal silicide is then thermally oxidized in such a way that a surface layer of thermal SiO₂ is formed. Interlevel vias are opened by plasma etching of the SiO₂.

Interconnect Metallization

The interconnect metallization consists of either a two- or three-layer structure. The first layer is a refractory metal alloy or a metal-rich metal silicide. If this layer contains a metal that is difficult to plasma etch (e.g., platinum),

*Used with permission from Ref. 9.

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deposition becomes a two-step process because the first layer must be patterned by the lift-off technique. To prevent damage to the mask layer and to achieve control of film composition, magnetron cosputtering is the preferred deposition technique. A light sputter etch of the substrate will be required prior to deposition to remove surface oxides and contaminants. After lift-off, the balance of the metallization is deposited in a separate step. If the uppermost metal or silicide is one on which deleterious interactions with aluminum might be expected at temperatures up to 600°C, a barrier layer must be deposited prior to final aluminum deposition. The aluminum may be oxygen doped as noted above. Both the barrier layer and the aluminum are deposited by a bias sputtering technique to ensure step coverage and with sputter-etching prior to deposition to remove native oxides and contaminants.

Multilevel Metallization

Assuming that another level of metallization is required, polyimide is spun on, appropriately cured, and patterned by oxide plasma etching. The second metal level is deposited by bias sputtering for good step coverage with a light sputter-etch prior to deposition to ensure adequately low interlevel contact resistance. Finally, a secondary passivation layer is deposited (typically by LPCVD) and bond pads are etched open to complete the device structure.

The trend is toward even more metal layers, greater than three, as shown in Table 15.4 and 15.6. Figures 1.2, 2.21, and 2.22 showed the details of four-and five-layer metal structures. In addition to developing more vertical metal layers, research is being conducted in the use of both gold and copper interconnects, such as reported in Session 11: Device TechnologyAdvanced Interconnection Techniques, 1993 International Electron Devices Meeting (IEDM). In that session, Cu/TiW metal lines showed two orders of magnitude better time to failure than Al/1% silicon at 200°C.

VLSI Metallization Reliability Concerns

The reliability of ICs in the field is of great importance. The evolution of new materials can be traced to a need to minimize electromigration, junction penetration, line corrosion, and interlevel breakdowns (Table 6.15). Some of these failure mechanisms were discussed in previous sections of this chapter, and all are discussed in Chapter 15. How do we eliminate or minimize these failure mechanisms? The addition of silicon to aluminum has been used to avoid junction spiking, copper added to aluminum has been used to improve electromigration resistance, and diffusion barriers have been used to eliminate the contact-resistance variability associated with the silicon precipitates.

Users of reactive ion etching (RIE) processes with chlorine-bearing gases avoided copper additions because of the increased corrosion susceptibility, whereas the lift-off process allowed the use of aluminum-copper metallurgy.

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Table 6.15 Reliability Effect on Process/Materials

Phenomenon

Reason

Solution

Aluminum and junction spiking

Unsatisfied silicon solubility in aluminum

Add 12% silicon to aluminum

High RC of small contacts

Precipitation of excess silicon
Diffusion barriers TiW

Electromigration of aluminum

High grain-boundary diffusivity
Add 0.51.0% copper

Hillocks
High diffusivity and film stress

Add 0.51.0% copper. Sandwich with silicide, tungsten, etc.

Interlevel defects
Pinholes, mask defects
Use dual insulator

Interlevel shorts result in yield losses. More important are the insulator defects (such as pinholes); extrusions or whiskers can grow at these sites in the presence of temperature and power bias and short adjacent metal lines, thus causing a field failure. Composite insulators have been shown to be effective (sputtered SiO₂ with PECVD nitride or polyimide with SiNx) to control the shorts. All these examples show how the choice of the elements was influenced by reliability considerations.

Short Channel Effect

The short channel effect (SCE) is a major issue with submicrometer CMOS. Simply stated, the short channel effect is the lowering of threshold voltage (VT) at shorter channel length (Leff). A high SCE results in increased leakage current (but high threshold voltage is required for low leakage) and poor performance. SCE can be reduced by thinner gate oxide (dielectric), optimized channel and source/drain junction profiles, and proper work function between poly gate and silicon:

1. Gate dielectric: Thinner dielectric improves SCE and current drive, but the high electric field introduces defect density, higher tunneling current, and integrity/reliability problems. Driven by defect density, the aggressive gate oxide thicknesses being reported are: 130 Å for Vcc = 5.0 V, 70 Å for Vcc = 3.3 V, and 45 Å for Vcc = 2.5 V. Nitrided oxide can reduce channel hot carrier degradation but it has higher fixed charge and initial interface state density.

2. Source/drain (S/D) junction dielectric: Shallow junctions with abrupt profiles reduce SCE and parasitic resistance. S/D extension is required to provide shallow junction portion for SCE improvement and deep

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Table 6.16 Typical Deposition Applications

Number of steps

Material
HCMOS
HMOS
CMOS/NMOS
Schottky
ECL

Polysilicon
2
13
1

1

Epitaxial silicon
1

0
1
1

Thick oxide
4
24
3
12
3

PSG/nitride
23
12
1
2
23

Aluminium alloys
1
12
1
0

Gold
02
02
01
0

Other metals
12
01

1

Silicides
12
02

Other

12

junction portion for silicidation (very low sheet resistance, <100 W/square, TiSi₂: most widely used) and contact (to prevent contact overetch and junction spiking).

3. Channel doping: Very nonuniform channel. The use of In (indium) and Sb (antimony) can improve SCE and reduce junction capacitance.

4. Source/drain junction profile: Shallow extension is used for SCE improvement and lower S/D sheet rho for higher circuit density. The profile is optimized for performance and reliability trade-off such as using a reverse pre-amorphization source/drain (i.e., implanting heavy ions of opposite conductivity). For example, Sb (antimony) implantation prior to BF₂ low-energy S/D for p-MOS, and In (indium) implantation prior to As S/D implant for n-MOS can reduce the ion implantation channeling effect and allow formation of an abrupt junction, thus reducing parasitic capacitance.

5. Isolation:

Modified LOCOS isolation is a trade-off between process complexity and bird's beak length, producing higher capacitance and narrow channel effect (VT increases as channel width decreases).

Shallow trench isolation has no extended two-dimensional thermal oxidation; dimensions are limited by lithography (in sub-0.5-mm regime); there is a negligible bird's beak and narrow channel effect and lower capacitance result. A planarization process, such as RIE (reactive ion etching) plus CMP (chemical mechanical polish), is required for a better control of the poly profile and resistance.

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The development of contact barriers was similarly influenced by the delineation process. The more popular diffusion barriers, sputtered TiW or CVD W films, lend themselves to subtractive processes.

Summary

The changing fabrication techniques pointedly reveal the increased use of deposited layers for VLSI and ULSI circuits. Table 6.16 shows the large number of deposited layers and new types of films used for VLSI and ULSI technology (HCMOS and HMOS) in comparison with other techniques.

References

1. C. R. Fencil and G. P. Hughes, X-Ray printing for the 80's, Circuits Manufacturing, December 1982.

2. W. Wakamiya and M. Nakajima, Overlay accuracy for VLSI devices, Semiconductor International, May 1985.

3. P. H. Singer, Advances in diffusion furnace technology, Semiconductor International, May 1985.

4. H. M. Liaw, Trends in semiconductor technologies for VLSI and VHSIC applications, Solid State Technology, July 1982. Reprinted with permission of Solid State Technology, published by Technical Publishing.

5. D. N. K. Wang and D. Maydan, Reactive-ion etching eases restriction on materials and feature sizes, ELECTRONICS, November 3, 1983. Copyright ©1983, McGraw-Hill, Inc.

6. P. S. Ho, Part 3 VLSI interconnect metallization, Semiconductor International, August 1985.

7. P. Burgraaf, Silicide technology spotlight, Semiconductor Int., May 1985.

8. S. Sachdev and R. Castellano, CVD tungsten and tungsten silicide for VLSI applications, Semiconductor International, May 1985.

9. J. L. Vossen, VLSI metallization problems and trends, Semiconductor International, September 1981.

Selected Readings

1. S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era. Vol. 1 Process Technology, Lattice Press. 1986.

2. S. Wolf, Silicon Processing for the VLSI Era. Vol. 2. Process Implementation, Lattice Press, 1990.

3. C. Hu, MOSFET scaling in the next decade and beyond, Semiconductor International, June 1994, pp. 105114.

4. G. Grivna and K. Kyler, Dielectric planarization for VLSI and ULSI applications, Semiconductor International, July 1994, pp. 134138.

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7
Packaging Technology Trends

Packaging technology trends are important because they significantly impact the quality and reliability of systems in which they are used. New package types may exhibit new failure modes, which may be screened out in the short term and designed out in the long term.

To increase the performance and reliability of a system while reducing its size and cost, systems designers use more complex and dense chips, resulting in the following device packaging trends, primarily for digital logic devices:

Greater number of I/O pins required.

Higher power dissipation.

Electrical contact on all four sides of the package (chip carrier, or quad flat package).

More stringent electrical requirements for the package (decreased resistance, capacitance, and inductance).

Tightened mechanical tolerance of the package and interconnect system.

Increased use of multichip module (MCM) packages.

Printed circuit boards with higher layer counts will be used.

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Blind vias will be used to increase routing density on printed circuit boards (PCBs).

The number of packages per system and the cost per interconnect level will decrease, while the cost of each package will increase.

Semiconductor packages protect devices from the environment, provide communication links, remove heat, and provide a means for handling and testing. With larger, higher density integrated circuits, these functions will not only continue to be important, but will be more challenging to meet. At the same time, there will be emphasis on maintaining or decreasing costs of these more complex packages. This will require increases in functional density (area ratio of chip to PCB or ceramic board on which the package is mounted; the board area referred to here is that of the package footprint or that area of the board required by the package plus any additional area required for package-to-board electrical interconnect) and higher performance design.

Since packages serve as the medium for providing an electrical connection from the IC chip to the outside world, the effects of the package on device performance require some discussion. Packaging high-speed, state-of-the-art devices requires strict control of noise, impedance matching, electrical resistivity, and temperature rise [1].

To meet the demands of increasing operating speed, problems with signal distortion and propagation delay must be overcome. This will require shorter chip-to-chip interconnect lengths, lower interconnect inductance, capacitance, and resistance, and lower thermal resistance.

Propagation delays in a package can be minimized by reducing the dielectric constant of insulators and reducing the length of conductors. The reduction of dielectric constant follows the reduction of capacitance, which solves noise problems. When propagation delays are important, the wire that carries a signal cannot be treated as a simple conductor, but must be treated as a transmission line. In a transmission line, electrical resistance is not the only property affecting signal propagation. Inductance and capacitance are also important; together they define the impedance of the line. High-speed devices will experience undesirable inductance levels due to the skin effect of round wire geometries for conventional wire bonds. An additional problem encountered at high frequency is capacitance, both lead to lead and lead to ground.

With the proliferation of more complex and functionally flexible integrated circuits (VLSICs and ASICs), new and innovative packages are being developed. We are moving to application-specific packaging where the application must first be adequately characterized before design choices can be made. The result will be an innovative product matched to a specific application. Some of the system requirements for IC packages include:

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Provide improved performance for fewer dollars.

Work faster and take advantage of the subnanosecond rise times and high speed of high-performance ICs.

Provide the thermal and mechanical efficiencies required by the shrink to submicrometer geometries at the chip level (higher grid densities are now required at the board).

Accomodate I/O and PCB interconnections into the high hundreds.

These package requirements tend to escalate package costs dramaticallyso much so that wafer fabrication, package, and test costs account for equal portions of the total cost of manufacturing a complex integrated circuit. As such, a package cost versus performance versus application balance must be continually evaluated and maintained.

New Package Solutions

Several examples are presented that illustrate the evolution of packages to application-specific products. The first is a new package that has been developed primarily for memories (DRAMs). It is a 24/28-pin lead-on-chip (LOC) package that can house large dice (up to 330 mils by 660 mils), has dual power and ground pins, and conforms to JEDEC standards. The LOC package provides a very area-efficient chip design by reducing the on-chip power buses; the package leadframe routes power above the chip surface.

The leadframe design of the package features leads that are of equal distance from one another and of equal length, thus reducing lead-to-lead capacitance variations. Wire bond pads are located in the center of the DRAM die rather than on its peripheryreducing thermal and mechanical stress on the die and voltage drops associated with long traces on the die itself. Another benefit for systems designers is reduced noise from voltage spikes on the chip.

Figure 7.1 shows an exploded view of the die bond and wire bond frames using a Mitsubishi design as an example. Figures 7.2 and 7.3 show cutaway and cross-sectional views of the LOC package structures for a small-outline J-lead (SOJ) package and a thin small-outline package (TSOP), respectively, made by Texas Instruments, Hitachi, and Mitsubishi.

Another new package is a plastic package that allows high thermal dissipation so that the use of ceramic packages, in some cases, can be avoided. This package, shown in Fig. 7.4, allows power dissipation of up to 4 W without the use of an external heat sink and more than 10 W with the use of an external heat sink and airflow.

A stress-free die-attach process was also developed for the package, so

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Figure 7.1
Welding of D/B and W/B frame.

that large silicon chips can be attached directly to the solid-copper heat sink with only a few percent of the usual stresses.

In addition, the leadframe itself provides spring tension to the heat sink during the molding operation to prevent flash. The stress relief ensures that the built-up spring forces are properly released. A molding compound with specially shaped fillers further reduces stress on the package. A high-conductivity copper-alloy leadframe is used in the package, and a fine-pitch internal lead structure allows shorter bond wires.

A frequent cause of IC package failure is moisture permeability. To address the problem of moisture ingress along the heat-sink-to-plastic interface, the package designers incorporated a locking ring and sidewall treatment, which provides a barrier to moisture penetration. The package, called the Power Quad

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Figure 7.2
LOC package structure (SOJ).

2, is available with 160 and 208 leads in a 28 by 28 mm plastic EIAJ (Electronic Industry Association of Japan) quad-flat-pack outline.

Figure 7.5 shows a plastic package (developed to house GaAs gate arrays) that is able to dissipate up to 44 W when using a heat sink. The die is mounted on a copper-tungsten base. The package metallization itself is copper, which offers much less resistance than the tungsten metallization of a cofired ceramic package. This new package also offers a consistent 50-W transmission-line impedance from the die to the pins, which is achieved by using a nine-layer PCB technology.

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Figure 7.3
LOC package structure (TSOP).

Figure 7.6 shows other versions of custom packages. The TSOP (Fig. 7.6a) package was designed by Fujitsu to hold two 16M DRAMs, and the SOJ package (Fig. 7.6b) can hold four 16M DRAMs.

Multichip Module Packages

Rapidly increasing gate and pin counts (Figs. 1.9 to 1.11) and increased package-related timing delays (board plus package in Fig. 7.7) are driving the demand for new and innovative package solutions such as the multichip module

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PowerQuad Specifications

Bonding wire
1.0 or 1.3mil Au

Dielectric constant
4.2 to 4.4

Leadframe material
High conductivity Cu

Length
30100mil typical

Power/and lead inductance
34nH

Signal lead capacitance
0.51pF typical

Signal lead impedance
Optional

Signal lead inductance
78nH

Substrate conductor
100% copper

Substrate material
proprietary epoxy

Theta JC
0.250.75°C/W

Figure 7.4
High-performance plastic package.

(MCM) package. An MCM is an assembly of ASICs and VLSICs (as opposed to a traditional hybrid circuit, which is an assembly of discrete semiconductors, passive components, and SSI and MSI circuits) mounted on a miniature PC-board-like package with the attendant ground, power supply and signal planes and termination means. Because packaging-related delays are such a big portion of the total cycle time delay, MCMs are receiving a great deal of attention

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Figure 7.5
Vitesse's high-performance plastic package. (Courtesy of ICE Corp., STATUS 1994.)

Figure 7.6
Surface-mount TSOP and SOJ packages of the future. (Courtesy
of ICE Corp., STATUS 1994.)

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as a method to minimize these delays. There are three general MCM categories, designated by the materials used for the conductor and dielectric:

The simplestand generally the lowest in cost and performance levelis MCM-L. The L is for laminate, such as FR-4, but polyimide-based laminations are used more frequently. COB is usually the interconnection of choice, but SMT/FPT packages (or TAB) may be used for applications with more demanding temperature cycles. Flip-chip or BGA packages also can be used whenever there is an appropriate application.

MCM-C (for ceramic) appears to be the next most popular choice due to the experience and infrastructure developed over the years with green tape ceramic hybrid circuit processing. In fact, the biggest difference between MCM-C and traditional hybrid circuits is that the former uses more than one active component. The lower dielectric constant of ceramic or similar material (usually between 6 and 10) and smaller geometries compared to those of typical FR-4 PCBs allow the design and manufacture of smaller and higher data rate systems. Flip-chip IC connections are very popular, but COB and TAB are also used in many applications.

MCM-Ds are similar in that a ceramic material is used for the substrate. A low TCE is important, but the density and power dissipation requirements of a high level of performance are major concerns. Aluminum nitride, with its high thermal conduction properties, is a popular choice for some applications. The conductors and dielectric are deposited as thin films (hence the D) using IC-type technologies to

Figure 7.7
System performance considerations.

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achieve thin layers and small geometries, resulting in a tight packaging density that minimizes parasitics and facilitates a high data rate performance.

Flip-chip and TAB technologies are generally used for the IC interconnections. However, if cavities are formed in the substrate before the interconnection films are applied, a chips first process can be used. This requires placing the chips so that their active surfaces are planar, followed by application of the first film in a dry form. Vias are etched with a laser, after which succeeding interconnecting and dielectric layers are applied.

MCMs provide increased operating speed (data rate) by reducing parasitic capacitance, inductance, and resistance, and by a decreased physical size. Several problems, however, confront the use of MCMs. These include

High cost

Availability of known good (i.e., completely testeddc, ac, and functional) bare dice

The testing or testability of the MCM itself

Die Interconnection Techniques

For higher pin counts, an SMT package becomes excessively large because of the lead pitch required. Nonetheless, SMT continues to be the dominant high-density assembly technology.

For many future products, however, designers will need to utilize technologies that go beyond SMT in terms of minimizing board volume and weight, such as COB, TAB, and flip-chip. Each of these has its own set of trade-offs, which the designer must consider when deciding on the best solution for a given application. In many cases, the best solution is a mix of several of these technologies on the same substrate. However, it is important to understand how each technology affects cost, lead times, production yields, rework, reliability, etc.

Chip-on-Board

Chip-on-board (COB) has become one of the most widely used high-density assembly technologies.

In the COB process, a bare die (Fig. 7.8) is bonded directly to the substrate with epoxy. The substrate material is usually glass-epoxy, but other materials can be used as well. This is followed by wire bonding each die bonding pad to an associated pad on the substrate, thereby providing a connection to the remaining circuitry. The entire die and all wire bonds are then covered with a layer of epoxy resin, which is later cured into a hard protective coating. The board area used for COB is little more than the die area itself. Compared to

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Figure 7.8
Cross section of chip-on-board structure. Board area used is
little more than that for the die itself.

standard surface-mount packages, COB in some applications can reduce board area more than 50% and yield height and weight savings by over 50% and 80%, respectively, making COB an excellent technology for end-product shrinking. An advantage of COB is that it is relatively inexpensive in that the package for the die is eliminated.

Several variations of COB that enhance the flexibility of the technology are possible. One is an effective way of reducing the overall height of the assembly by recessing the die in a cavity routed out of the substrate. The die can be partially recessed or fully recessed where height is limited. The trade-off in these variations is the loss of area underneath the die for routing inner connection layers. Also, the substrate cost can increase as much as 30% because of the secondary routing required to provide the recessed area.

Another variation involves mounting COB devices on both sides of the substrate to further increase module density. Currently, dual-sided COB devices must be offset to accommodate fixturing for the mounting process. However, mounting dual-sided COB devices back-to-back is being developed, but the trade-off is higher manufacturing cost.

Originally, COB was not considered sufficiently reliable for use in high-end systems because of poor assembly yields and an inherent problem with moisture contamination under the epoxy resin. However, improved epoxy encapsulants now provide an effective protective barrier.

The primary drawbacks of COB are that it cannot be reworked after the encapsulant has been applied and, because COB uses a bare die, the only testing available is that performed on the die via wafer probe by the semiconductor manufacturer (thus necessitating a known good die).

The chip-on-flex, or COF, solves both of these drawbacks while maintain-

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ing reduced size. Instead of bonding the bare die directly to the substrate, with COF the die is bonded to a piece of 0.15-mm-thick polyimide film having a top layer of gold-plated copper. The layer is etched to provide pads for each wire bond plus escape traces from each pad out to a convenient lead pitch acceptable to quad flat pack (QFP) IC testers (Fig. 7.9). As with standard COB, the entire die and wire bonds are covered with encapsulant for protection. The polyimide subassembly is attached to the FR4 substrate with a hot-bar reflow process and is as reworkable as a standard SMT package.

Thus COF has the advantages of facilitating complete testing of the device prior to mounting and allowing removal of a failed device from the substrate. Its primary shortcoming is that it uses about the same board space as a standard QFP package.

Wire bonding, as shown in Fig. 7.8, has typically been the most common IC attachment technique, but it is now a limiting factor as IC manufacturers try to reduce die-package sizes. Consequently, flip-chip techniques such as the ball grid array (BGA) are gaining increased interest and support.

Flip Chip

The flip-chip die attachment method (as presented in Chapter 3) requires special metallization on the IC chip that terminates with solderable bumps on the bonding pads. The chip is then mounted face down, usually on a ceramic or other low temperature coefficient of expansion (TCE) substrate, and interconnected with a reflow solder operation. This process, also referred to as C4 (for controlled collapse chip connection), was initially used in the 1960s by

Figure 7.9
Chip-on-flex offers downsizing plus
testability. Subassembly is soldered to
FR4 substrate, which may be reworked.

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IBM for the 360 computer series and is still in use for today's systems. Motorola is currently using the basic solder bump process for its OMPAC (overmolded pad array carrier) ball grid array (BGA) package shown in Fig. 7.10. The solderable bump makes a short, sturdy connection that features minimal parasitic electrical properties, making it desirable for higher frequency systems.

The BGA package, rather than using pins for leads, mounts to a board using solder balls located on the underside of the package (Fig. 7.11). The BGA offers features that systems designers require (Table 7.1): small size, low profiles, excellent electrical characteristics, high yield (because BGAs are self-aligning), a robust package, and elimination of short/open problems. By spreading the contacts over the bottom of the packaged device, the size of the package is reduced compared to quad flat packs. No longer are there many small leads jutting out from all edges of the package that can result in handling damage.

However, as might be expected, there are some concerns with this package. Specifically,

The solder joints are hidden beneath the package, making visual inspection impossible.

The high cost. Even with increased volumes, BGAs will more than likely command a greater price than QFPs since BGAs have a circuit board that holds the chip and fans out the leads. And, though the printed circuit board area may be small, circuit boards that can handle BGAs may well require more layers. From an area standpoint, BGAs take less space,

Figure 7.10
OMPAC ball grid array from Motorola. (Courtesy of ICE Corp., STATUS
1994.)

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Figure 7.11
Motorola's 169-pin overmolded pad array carrier (OMPAC).

Table 7.1 BGA Benefits Summary

Manufacturers enjoy

· Improved yields.

· Absence of leads and lead-related defects.

· Easier to mount a 50- or 60-mil BGA than a 16- or 20-mil QFP.

· Wetting action during solder reflow tends to pull packages into alignment.

Designers enjoy

· Smaller footprint (169-I/O BGA takes up 51% less space than a 160-pin QFP).

· Bumps under the chip can be used as thermal vias.

· BGA can have a resonant frequency higher than that of a QFP.

· BGA can be optimized for most wire bond lengths, reducing average inductance per lead.

Source: ICE Corp., STATUS 1994.

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but routing traces to them uses more PCB layers. This can serve to increase the cost of the subsystem.

BGAs are susceptible to moisture, which can reduce yield and cause long-term reliability problems.

Reference

1. E. R. Hnatek and B. R. Livesay, Quality issues of high pin count, fine pitch VLSI packages, International Test Conference Proceedings, 1989, pp. 393421.

Selected Readings

1. M. L. Barton, Ball grid array technology: Is it the answer to defect-free assembly?, SMT, August (1994).

2. J. S. Hwang, BGA: Soldering concerns and defects, SMT, August (1994).

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8
Electrical Testing of VLSICs and ASICs

Introduction

The proliferation of VLSI circuits has dramatically changed the way electrical test programs are generated. Generating application-specific VLSI circuit test programs has become unmanageably complex. The proliferation of a large number of different configurations requires that an equally enormous number of test routines be generated, and generated in a short time, rapidly creating a bottleneck. The increased circuit complexity inherent in VLSI devices in terms of both transistor count and circuit function requires an exponential increase in design timeman-years for VLSI circuits versus man-months for SSI/MSI circuits (see Table 8.1). The test program generation of these devices presents as complex and time-consuming a problem as that of circuit design; it must be given equal importance with the design function, and it must be addressed early in the design cycle. Thus, technology is driving test time: the number of devices per chip, the number of external pins, and the cost of the testers themselves. These escalating complexities of chip development have created a number of sophisticated engineering workstations that automate test program generation and tie it to the chip design process via the CAD system. Manual test program generation is no longer viable.

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Table 8.1 Test Program Development Time (Manual Generation)

Function

Number of on-chip transistors

Test program development (hours)

SSI/MSI

200

120

Peripheral chips

2,000

320

Microprocessors

20,000

1,000

VLSI microprocessors

200,000

3,300

Source: Courtesy of Digital Equipment Corporation.

The Purpose of Testing

The two major weaknesses that cause failed ICs in customer use are (1) incomplete test coverage, and (2) incomplete knowledge, or attention to reliability design rules.

The purpose of testing is to verify conformance to product definition which should verify conformance to customer requirements. Testing is an inspection process that exists because the root cause of defects and failure mechanisms has not been eliminated. Testing does not add value to the product.

Electrical testing consists of three steps: (1) continuity test, (2) functional and dynamic test (AC), and (3) test of DC parameters.

Electrical testing is used for the following.

1. For verifying IC performance and conformance to published data sheet specifications so that bad parts are not shipped to the customer. [The unit of measurement for this is typically a parts per million (ppm) value for the defective parts that leave the factory.] The electrical specification limits and conditions must be related to the wafer fabrication process parameters and thus to the potential physical defects that can occur.

2. To detect the following typical wafer fabrication problems to enable permanent corrective action and thus continuous improvement to take place.

a. Poor/marginal quality oxide and gate oxide shorts (IDDQ measurements).

b. Metallization (shorts/opens).

c. Sodium contamination (junction leakage in linear ICs, for example).

d. Surface instabilities in CMOS and bipolar ICs, resulting in increased leakage current and low breakdown voltage.

e. Hot carriers.

f. Oxide wear-out (multiple read stress on nonvolatile memory oxide).

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Integrated circuit manufacturing processes undergo constant change (process improvements, die shrinks, mask changes, new equipment is brought on line, etc.), and therefore are never under complete control. Thus, some form of testing is required. Furthermore, as device geometries scale down, small particles that may not have had much impact on the reliability of earlier ICs can now cause interlayer shorts, metal line opens, etc. This effect will become more significant in the future. Particle density is typically higher for small particles compared to large particles. Data indicate that IC failure rates due to random particles will have a tendency to increase exponentially as device geometries are scaled [1].

Functional testing alone is inadequate to detect random defects because functional testing cannot duplicate all of the customer possibilities in using complex ICs, no matter how long the test time. Parametric tests are required to detect random defects. For example, Motorola estimated that it would take at least 2 million years to functionally test the 8-bit 6800 microprocessorneither realistic nor cost-effective. Also, many CMOS defects will escape a functional test set, but will fail in customer use. What is the solution?

Thus, integrated circuit testing requires the use of both functional and defect-oriented tests. Functional tests serve as a method of design verification, but they are neither totally comprehensive nor do they provide a metric as to when the process of testing is complete.

Integrated circuit testing has progressed from functional to fault model testing to defect testing. Once considered a simple task for the back end of the IC manufacturing process, testing start-of-the-art ICs to guarantee a defect-free product has become next to impossible. For a complex IC, it takes as much time and effort to develop a test vector set as it does to design the IC itself. The test process requires a structured approach at the inception of design in which goals are clearly defined by a multidisciplined team concerned with design, manufacturability, testability, and reliability.

Structured testing identifies failure modes and devises quantifiable tests that are tailored for detection of these failure modes. Structured testing asks not whether the design is correct, but is the integrated circuit without flaw. Structured testing therefore allows the test program to quantify how many of the possible defective situations have been examined in the IC under test. Structured testing can take two forms in designing a test set.

1. Use of fault modelsabstract models are hypothesized to represent the faulty behavior of the product; a fault is not real.

2. Use of defect modelsthe actual physical imperfection caused by errors in design, wafer fabrication, assembly, and handling. A defect model is a behavioral description of a specific defect or class of defectsit models real properties. Defect models are required for developing accurate automatic test pattern generation.

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The physical defect approach is more deterministic, while the fault model approach is more mature but found to be lacking in terms of real defects or faults (see fault simulation and test generation later in this chapter). Production IC test programs must be oriented for detection of specific defects. Thus, both test approaches have a vital role and are often used synergistically. This chapter discusses in detail the issues involved in electrically testing VLSICs.

Historical Ssi and Msi Test Program Development Methodology

Until very recently, most test programs were developed manually (see Table 8.2). This was a tedious and time-consuming task, fraught with many opportunities for creating errors.

The dominant method for SSI and MSI device test pattern or vector generation was by a functional model or by a heuristic approach, rather than by using logic simulation and fault simulation techniques. This test development

Table 8.2 Steps in Manual Test Program Development by the Test Engineer

Learn device organization and electrical specification (from IC suppliers or design engineer/circuit designer and other sources in various forms):

Functional description.

Logic function.

Controlling signals to each pin of the device.

Block diagram of internal structure.

Pin out.

Timing diagram for each critical sequence.

Develop test strategy.

Generate test code per documentation:

Observe signals and compare with functional truth table and logic diagram.

Start with simple and basic tests to confirm that devices behave properly, such as DC and functional tests.

Then begin adding tests to exercise remaining device pins.

Next work toward more complex pattern and timing tests.

Debug and refine software.

All of these involve utilizing the test engineer's prior knowledge and experience (i.e., their reference libraries, if you will), which results in tests that are compact in form.

Perform characterization testing; this determines which patterns are effective in weeding out faults, and which should be used in 100% testing and still not reduce fault coverage.

Generate 100% inspection test program.

Release test program.

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method, though the most costly, was utilized because, in fact, test engineers at both the IC suppliers and the users really had no other choice. The IC logic designers designed their circuits with no concern for testability. Once the circuit was designed they turned the design over to the product engineer and, subsequently, to the test engineer, without much documentation. By the time the test engineer received the task of generating the test program, the design engineer was on another project and unavailable for consultation. The users had similar difficulty in obtaining information upon which to develop a test program for a given device. The IC supplier did not provide sufficient logic details from which the user could synthesize a data base, nor did they provide any test vectors or test programs.

Without logic details and fault simulation, the user was unable to generate functional tests with measurable fault coverage at the MSI levelthe real shortcoming of this approach. Fault coverage was obtained by means of a trial-and-error process that relied heavily on system and field testing to find failures. The results of the subsequent failure analysis were fed back to the test engineering group for incorporation into, and modification of, the test program.

However, this procedure was too time-consuming, costly, and ineffective, and often resulted in test programs that to some extent were overkills. As the ICs to be tested became larger and more complicated, the situation grew worse, to the point that creating a new program and debugging it into a marginally useful test routine had typically become one of the major cost elements in a product development project. With the advent of VLSI circuits, the task of hand generating test programs that would adequately exercise the devices became virtually impossible. What was required was an easier method to determine the fault coverage and generate the subsequent test vector set. This led to the development of various fault models, such as the stuck-at fault model, which are used in conjunction with the now existing engineering (CAD) workstations.

The Nature of Vlsi Circuits as it Impacts Testing

Electrical testing of VLSI circuits presents some unique and challenging problems, all having to do with the peculiarities of these ICs. It is important to understand the nature of VLSI circuits, and then put into perspective some of the considerations that must be made in attempting to test these devices.

1. VLSI circuits consist of standard ICs, application-specific ICs (ASICs), and application specific standard products (ASSPs). However, the preponderance of VLSI circuits are application-specific. ASICs are characterized by many different designs, low quantities of parts used, rapid change, quick fabrication turn cycles requiring the rapid generation of flexible and comprehensive test programs, and high circuit density, high pin (I/O) count, and high-speed devices.

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2. Integrated circuits have gone from being 10,000-gate, 10-MHz, 40-pin LSI devices to 200,0001,000,000-gate, >100-MHz devices with in excess of 200 external pins. This significant density and performance change has brought with it new and major problems in device design, manufacturing, and testingresulting in an exponential increase in both design time and test program development. Testing of very-large-scale and ultra-large-scale integrated circuits accounts for 45% of total product costs (see Fig. 1.12), and these costs may escalate as VLSI and ULSI devices continue to shrink. Two examples of the length of time it takes to test specific ICs are now presented.

Example 1. Combinational circuit: How long does it take to test the add function of a 32-bit microprocessor (mP) at a test rate of 1 MHz?

Input port A: 32 bits with 2³² combinations.

Input port B: 32 bits with 2³² combinations.

Example 2. Sequential logic: How long would it take to test a 1K RAM for all possibilities that a customer might use assuming a 1-MHz test rate?

This calculation does not include the pattern-sensitive possibilities. Pattern sensitivity has historically been a major concern in memory testing, but for VLSI DRAMs it is not a significant issue. Note that increasing the test rate by a factor of 100 will not appreciably affect overall test time for a thorough test.

3. VLSI circuits implement the best design/processing technology to achieve the desired functional performance. As such, these circuits increasingly contain mixed functions, both digital and analog, fabricated with one or more technologies: CMOS, BiCMOS (bipolar and CMOS combined), DMOS (double-diffused MOS), and/or bipolar processes. This complicates test program generation and further requires that a general-purpose mixed-technology tester be used.

4. For circuits with structured organizations (memories), extra elements (spare rows and columns) are utilized in the chip design to aid in producibility (increase the yield), and to increase system reliability. In implementing redundancy one needs to be able to tell whether or not redundant elements have been used in the finished device and, if so, what circuitry they have replaced so that these circuits can be

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checked (tested) for sensitivities as well as nearest neighbor and other architectural effects. Externally, users of redundant devices cannot detect whether or not the device has been repaired with a redundant element, or to what extent. Because of this, effective testing is not possible. An example illustrates the technical nuances in testing ICs with redundant elements in place: DRAMs used in mainframe computers experienced hard failures at power on. Extensive investigation and testing revealed that a slow VCC ramp rate (a parameter not specified by the IC supplier) deactivated the spare rows and columns that the supplier had programmed in to replace faulty rows and columns, resulting in partially functional memories.

5. Integrated circuits have become far too complex to expect test engineers to develop test programs without the design engineers having considered the issue of test circuit development. The best way to avoid problems is to integrate circuit design and test program development early in the design process. Design and test engineers must learn to communicate with one another in an effort to develop circuits that are testable as well as functionally correct.

VLSICs contain either built-in self-test (BIST) or design-for-test (DFT) capability with external ports being available for this activity as well as on-chip error correction circuitry (ECC). DFT considers both debug and production needs during the logic and circuit design phases of development, putting the test burden squarely on the shoulder of the logic designer. ECC tends to mask device problems simply by its intent, such that process defects are not visible. Figure 8.1 summarizes the key elements of the integrated design test flow process.

6. Every new device application requires a new test program. No matter how simple and straightforward program generation becomes, the proliferation of a multiplicity of ASIC devices will tax the ability of test engineers to produce efficient programs in a timely manner. The ICs are only going to be as good as the test program.

7. The de facto standard test methodology (Table 8.2) used for SSI and MSI devices is not sufficient nor applicable for VLSICs.

8. VLSI circuits require a new thought process (both for design and test program generation); they are no longer isolated circuits, but systems on a silicon chip geared for a specific application. As such, a system's mental attitude must be adopted.

9. The availability of cost-effective engineering workstations to provide computer-aided design tools for custom VLSI chip design allows functional pattern data from the IC design phase to be available for transfer to the test group. Test vectors used during logic simulation

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Figure 8.1
ASIC integrated design test flow.

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can be used to verify prototype chips on the production line. This, combined with fault simulation, allows the test engineer to evaluate, modify, and resimulate test vectors in order to determine an optimum test vector set for a given device type.

10. The roles of design and systems engineers are changing. Due to the availability of engineering workstations and accessibility of remote design centers, more systems designers are designing their own ICs, taking those designs beyond the net list to the data base tape. This requires an extensive knowledge of IC design and fabrication principles and the availability of accurate logic building block/process models. Conversely, IC designers are gaining an increasing role in system design by virtue of the end product and its subsequent use.

Testing Vlsic Devices

Testing any IC involves simulating the voltage, current, and timing environment it would see in a real system, and sequencing it through a series of states, checking its actual against its expected responses.

VLSICs are bringing renewed emphasis to testing. The main issue is one of testability, that is, a design characteristic that allows the status of a device to be determined with confidence in a timely manner. This involves the task of controlling all inputs simultaneously and then trying to observe all the outputs simultaneously. At the heart of this issue are some important questions that must be addressed: (1) Can a test that detects all faults be assured? (2) Can testability be assured? (3) Can test development time be kept short enough to be economical? and (4) Can test execution time be kept short enough to be economical?

Testing VLSI circuits concerns fault simulation and fault coverage, testability analysis, BIST or DFT, and matching the logic simulation environment with the ATE environment, whereas SSI, MSI, and to some extent LSI circuits by their very nature did not need to pay attention to these issues.

Test Philosophy

The problem of testing VLSI circuits must first be approached with the philosophy that the device is basically untestable (i.e., the control and observation of every node are not possible). The implementation of this philosophy requires that solid engineering decisions be made as to what to test, what not to test, and what depth to test within the constraints of material, capital, and personnel resources. As such, it is no longer possible to review a device specification or data sheet, define all possible test conditions, and implement that test.

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The process of VLSIC test definition places heavier emphasis on the chip designer to develop an efficient and effective test vector set for a given device, and upon the test engineer to integrate these test vectors with available ATE and its capabilities.

Systems on Silicon

VLSI circuits have virtually become systems on silicon. As such, one must adopt a systems mentality and methodology in the total approachdesign, development testing, documentation, and managementof dealing with these devices. Many of the disciplines involved, if properly implemented, are the same as, or similar to, those utilized by systems designers. When one examines the problems with VLSI circuit development, it becomes apparent that using a systems approach may help alleviate these problems.

The systems approach synthesizes all needs up front (i.e., concurrent engineering using cross-functional work teams) in the program, and develops requirements that reflect all of these needs. A project leader is established to carry the system (IC) design from conception through to development, qualification, and production. The project leader is also responsible for the achievement of overall cost goals. Circuit designers, systems engineering and manufacturing specialists, and support functions assist the project leader in these endeavors. The circuit design, systems manufacturing, and support functions are selected for their overall knowledge and assure that the proper integration of all the specialized engineering technologies to be used in the design/development process is achieved. By having an overall project leader and staff, there is no question about a responsible function to ensure the development of an acceptable functional design that meets performance objectives over the environmental envelope, is producible, is testable, and is supportable by the final user. It is especially important that the IC design team develop and understand the relationship between the IC electrical parameters, the generated test vectors, the physical defects, and the in-line wafer fabrication process monitors.

The systems approach, as applied to VLSI circuits, aids in the determination of automatic test equipment, computer-aided engineering (CAE) equipment, manufacturing processes, and the device technology to be used, prior to initiation of the design. Thus, the limitations and attributes of each of these development functions would be known and could be properly translated into design requirements. As with larger system developments, testability is as important in the design/development phase as in the functional operation stage.

By knowing the extent of available support equipment and its limitations, one can project what additional capabilities are required to support a new VLSI circuit. Thus, the cost for testability is considered in the up-front cost projections,

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and the necessary task schedule will be time-phased to be compatible with the VLSI circuit development. In this way, the current problem of designing very complicated and costly VLSI circuits whose functions cannot be verified, either because of the unavailability of test equipment with suitable capability or the inability to access given functions, can be solved. By defining the functions to be tested prior to design development via DFT and/or BIST, the access hooks can be designed in the same manner as built-in test equipment is accomplished in larger systems.

The systems approach to VLSI design calls for periodic design evaluation via formal design reviews by the circuit designer, the test engineer, the process engineer, the package engineer, and the reliability engineer to assure the proper interpretation and implementation of the design requirements for testability and producibility. Their involvement through the design cycle is paramount to achieving a testable design.

The primary function of the project leader is to establish a time-phased, cost-apportioned program that ensures all functions utilized in the design, development, and production of a VLSI circuit work together as a cost-effective team. The project leader ensures that the entire project of VLSIC development from concept, design, development, production, testing, and marketing are all considered initially, and then through each phase, as work progresses. The project leader also ensures that all team members are working toward the same end, to have a marketable, testable, and functionally operable (over specified environments) VLSI circuit, and to achieve this in the most economical manner.

This approach should minimize the current nonintegrated design, foundry, and testability problems currently being experienced and discussed herein.

The Designer (User)-Foundry (Supplier) Interface

A cooperative relationship between suppliers (or foundries) and users (or designers) that is based on mutual trust, honesty, and respectand is characterized by open lines of communicationis beginning to appear. The cooperative venture is replacing the often adversarial relationship that prevailed in supplying standard SSI, MSI, and LSI devices.

With the widespread availability of engineering workstations, and the accessibility of design library models and foundries, many companies have turned to designing their own application-specific ICs. No matter how much up-front work the users do, though, they eventually have to interface with the silicon foundries. The interface between users and suppliers, or designers and foundries, can occur at several points in the design cycle. Some suppliers will accept a functional block diagram, while others require a simulation and net list. Wherever the interface takes place, both the suppliers and users must make sure that each

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area of responsibility is clearly and specifically defined before the design process begins, especially for the area of design verification or testing. When a design and fabrication activity spans multiple companies, the question of design verification becomes complex. When all is said and done, it is the designers who are responsible for design verification and testing since they generate the net list from their circuit design simulations, fault simulations, and timing analyses.

There must be close communication between the suppliers and users in order to achieve successful design collaboration. Therefore, it is wise to have several design review sessions in which the designers of the logic and the foundry determine whether the design does indeed implement the logic requested, and whether it does so to the desired electrical specifications. Every step of the process should be discussed, documented, and agreed upon.

An important part of the design process, a part that should proceed in parallel with the design of the device itself, is the generation of the test program. An understanding needs to be reached with the foundry as to who is responsible for the generation of the test program. In some cases, the test program can be generated with the same software used to generate the circuit layouts; in others the test program must be written as a separate task.

Also, one must decide who performs what tests. Users will have to take on more responsibility than they have in the past. This is because potential ambiguities in specifications put the responsibility for ultimate verification for any IC's fitness for use on the company who designed it.

This brings up the question that if a circuit fails in its application in the field due to a fault that the test pattern does not detect, where does the responsibility fall? This is a key issue for the foundry because users often attempt to return parts that fail in their systems but pass the supplier's test program, and this is a point where the relationship between supplier and user can become strained. It would seem logical that since the user is responsible for developing the test pattern and, thus, the fault detection, then the field failure as described here is the user's problem regardless of what caused the failure. It is also the user's responsibility to correct the test pattern and to request that the change be incorporated in the supplier's test program.

The use of outside (third-party) design houses by the user creates more problems and complicates the user-foundry relationship still further. Third-party design houses generally have design expertise, but they often lack adequate knowledge of both the process model and the ability to specify test conditions and develop test vectors commensurate with the specific automatic test equipment (ATE) used by the foundry. This leads one to question the capability and inherent accuracy of the test vectors thus generated to separate good devices from bad.

The trend toward the use of these third-party design houses is increasing. This can further impede communication between the user and the foundry, and

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can make it difficult to determine who is responsible for what. To make matters even more complicated, electronic distributors are entering into semicustom design. Thus, who agrees to do what for whom? Does the third party contract with the silicon foundry to fabricate and test the circuit? Will the third-party house negotiate the test criteria and specifications? These questions must be answered before a circuit can go into production.

Consequently, it is important that all areas of responsibility between the user and the supplier are thoroughly defined, understood, documented, and agreed upon. Specifically, what defines an acceptable product?

Test Specifications

The device specification or data sheet is the major place where problems arise for the foundry's test engineers. The foundry's responsibility regarding test is to ensure that the device is tested per the user's data sheet. It is the responsibility of the user to ensure that the device meets the data sheet specifications. Problems arise when the initial silicon fails to meet the test requirements. Is the problem with the foundry, the test methods, or the design? A rapid solution can only be brought about through mutual cooperation by both partiessupplier and user.

In many cases, data-sheet performance specifications are inadequate. They are often based on design criteria and circuit simulations. This is all well and good if the actual circuit meets these specifications. However, limitations and shortcomings of the model (both circuit design and process), conditions of simulation, and design shortcomings all seriously affect and hinder the compliance with the specifications. In this case, the data-sheet limits will have to be derived through characterization of the silicon implementation.

Thus, the test specifications for a given IC should be clearly and concisely defined.

1. Which parameters are 100% tested?

2. Which parameters are tested over temperature?

3. Do output loading conditions apply over VCC (power supply voltage) and temperature?

4. Which parameters are guaranteed by the functional tests?

5. Which parameters are guaranteed by design or need not be tested?

Furthermore, the user must provide details such as the following.

a. Operating temperature range

b. Power supply range

c. Input voltage levels

d. Output voltage levels

e. Output loading

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Figure 8.2
Repertory dialer timing.

f. Timing delays and pulse widths

g. Input and output leakage

h. Static and dynamic power consumption

i. Specification conditions for each test

Then there is the issue of electrical parameters that are important to the application of the IC, but that are either not defined and specified, or not fully defined, specified, and characterized. Some of these include setup time, valid data, edge rates, undershoot, effects of multiple input and output switching, and ground bounce,* to name a few.

With increasing frequency, foundries are encountering test specifications that are application-specific rather than circuit-specific, especially circuits that are derived from existing PC (printed circuit) board designs. Often, these application-specific tests add nothing except test time, since they are purely design verification checks. Problems arise when the test parameters exceed the tester capability. Figure 8.2 shows the timing requirements for a repertory dialer circuit at the system level. To recreate this timing on a test system would be difficult, since the timing range exceeds the tester's capability from 4.59 MHz down to several hertz. To simulate this timing in a Sentry tester, for example, clock burst mode would have to be used. However, since the timing specifies a range for the valid response (minimum to maximum), a much slower binary

*See Ref. 14 for more details on ground bounce.

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search algorithm would be needed for the test. A test engineer could easily use weeks of test time developing, debugging, and correlating this test. It turns out that for this device, the timing is guaranteed by the functional test that runs at the 4-MHz test rate. The point is that if a specification appears in the data sheet, the foundry must test it even if it is a redundant test that consumes a lot of test time.

One might argue that the test engineer should have known this from the outset. This is true if the test engineer is working with the designer and is involved in the test vector development. However, in a silicon foundry, the test engineer is usually involved after the pattern generation (PG) tape is delivered, and sometimes after the first silicon. In this situation, all the test engineer has to go on is the specification information. Often, due to the time lag between design and the first silicon, the designer has gone to another project, and the details of what to test and what not to test in the specification are not clear. To prevent this, the designer must write test specifications that clearly detail what is tested and what is not. Better still, the foundry's test engineers should be involved during the test vector development and preparation of the specification, further underscoring the need for effective and open communication between user and foundry.

Specification problems arise in part from the tendency to test the design (design verification) rather than to test for manufacturing defects arising from process variations. Many novice designers are unfamiliar with the issues of testing silicon, and unknowingly include design verification tests. For example, consider the output voltage test on CMOS devices. A sufficient test is to measure the outputs under full-load conditions (including capacitance) and at no-load conditions. Both tests can be performed during the functional test by designing a single load that can be switched in or out during the test.

Then too, data sheets often specify output voltage tests at three different load currents, such as VOL at IOL = 0 A, 100 mA, and 2 mA. Testing at full compliance is necessary since it verifies that the gate threshold and channel diffusion are correct. However, testing at the midpoint of the transfer curve does not add anything to the test except time. Not only does it cost test time, but often adds test complexity and, consequently, test development time, since the test engineer would have to resort to either a slower DC measurement or would have to build a second set of AC loads.

Integrating Design and Test

Traditional approaches to IC development separated the design and test engineer. The design engineer's job ended when the design was finished. It then became the test engineer's responsibility to facilitate transfer of the design to manufacturing with an effective test set. Because the designer was typically only

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concerned with functionality, the testability of the design when received by the test engineer was often unknown, and frequently inadequate, since only functional testing was considered to be part of the design process. The challenge for the test engineer was to make the best of a bad situation in an attempt to address manufacturing test requirements. This frequently led to schedule delays, or resulted in shipment of lower quality products, introduced prematurely, in order to meet production schedules. Concurrent engineering applied to design and test offers solutions to these development issues.

When applied to design and test, concurrent engineering means that the testability of the design and its quality, reliability, and manufacturability are all considered early in the design process. If test is a focus of the design effort, it will lead to improved testability, quality, reliability, and manufacturability.

Thus, in order to completely test an integrated circuit, test development must begin when circuit development begins. Design engineers must take into account the testability of their circuit as well as the functionality. Until recently, logic designers were not concerned with generating the test vectors and diagnostic data used to screen out products with manufacturing defects, or verifying the performance of their designs. However, the very nature of ASICs and the tight delivery schedules demanded, in addition to end usage requirements, are providing the impetus for designers to consider the testability of their designs, something once the sole concern of test engineers. Planning a chip's test strategy during the designeven during architectural definitionpays off in time: the time it takes to write and verify effective production test programs. Notice what was said: Designers must address testability. This is a significant statement indeed, and a departure from how designers have perceived themselves in the past. It is made with the knowledge that the roles of circuit (IC) design and test engineers are changing and overlapping.

Design engineers can no longer remain isolated from the physical test issue. This does not imply that design engineers have to understand the characteristics of the tester as completely as test engineers do, but it does mean that the design engineers must understand the basic problems involved in test generation and, specifically, any potential problems that affect the testability of the integrated circuit they are designing.

By confronting the test issue early in the circuit development, the circuit designers, who know the most about the complexities of the circuit, can make optimal design and test trade-offs. The design engineers can determine whether circuitry needs to be added to make the circuit more testable, whether the functionality of the circuit can be modified, or whether the tester can economically test the circuit without any modifications. Thus, it is important that a multi-disciplined team approach be taken to IC design so that frank and open discussions of all parties will enable them to develop a manufacturable and testable circuit (by exchanging ideas early in the design process) that meets customer requirements.

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Also, by simulating the circuit using techniques that the tester (ATE) is able to perform, the problems of translating simulation results into tester input are significantly reduced. When design engineers are forced to avoid simulation shortcuts, they quickly become aware of the difficulties involved in testing their circuit, and they become more willing to design their circuit so that it is testable.

The test engineer still has a very significant role to play. The process of test definition places heavier emphasis on the chip designers and their infinite knowledge of the circuitry, as it should, to develop an efficient and effective test vector set for a given device, and upon the test engineers to integrate these test vectors with available ATE and its capabilities. The test engineer takes the ball from the design engineer at the point where the design is ready for fault simulation, and proceeds from there to aid in applying a vector set for a given ATE system. Thus, the testing of ASICs becomes a partnership between the design engineer and test engineer working with a common focus.

The test engineer must also be the catalyst in developing both new test languages that simplify programming and advanced test vector generation techniques to reduce the circuit designer's burden.

The integration of design and testing functions has begun. With new tools at hand, experienced designers are using their simulators and test generators to both create testable circuits and to build better ICs. For their part, test engineers are drawing on high-level programming and hardware description languages, typically design aids, to devise more efficient ways of modeling faulty circuits. Thus, there is now a sharing of their respective tools of the trade.

The Simulator-Tester Relationship

Logic simulator inputs and results do not provide the information required to allow the test engineer to perform timing tests (e.g., setup and hold-timing tests). For example, logic simulators operate at high frequencies and, in general, do things that ATE systems cannot. Thus, tester-specific limitations must be incorporated into the test vectors at some point during the design phase. A circuit designer will often write test vectors that run at megahertz and gigahertz speeds, with pin independence, and for hundreds of thousands of vectors. However, this is incompatible with current ATE. Thus, the simulator must have knowledge of the operating characteristics of the target ATE.

Stimulus and response patterns, generated during device simulation, provide a starting point for generating test vectors to be used in the test system. But, unlike the simulator, the tester offers finite timing resolution. So some incompatibilities usually arise between the theoretical simulation vector set and what a tester actually uses.

This problem arises because software simulators and testers operate differently. Simulators are event drivenone event can cause anotherwhile

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testers are state drivenstates can change synchronously based on a well-defined cycle time. This is better understood by considering how a simulator and tester actually work.

With simulation, a change at the input of a gate in the device model will result in a change at its output after a time t, where t is the propagation delay of the individual gate. The output of a model of an entire device is therefore the sum of the actions of each of its gates and their various propagation delays in reaction to a change of input. The output of the device can change at any time, depending on the total propagation delay of a particular signal path. There is no inherent notion of a cycle time in most CAE simulators.

With a tester, on the other hand, inputs to the device under test (DUT) and the time at which the output is sampled must be specified in relation to the tester's master clock. Even though input edges and sample times may be offset within the basic cycle, it is always possible to generate a simulation pattern that requires more timing edges than the tester can provide.

Consequently, to derive test patterns from simulation vectors, users must take tester-imposed constraints into consideration. This usually means that some of the simulation signal edges must be moved slightly to line up with those that the tester can generate. But what edges to move and how far they can move without losing test coverage is not a trivial problem.

Simulation input vectors are generally specified as waveforms that can change state at any time. On a tester, stimulus is applied within predefined cycles, and a pin can be programmed to pulse or not pulse during a given cycle. Programmed transition delay times and pulse widths determine the length of time that the stimulus is applied. To make matters worse, testers may not be able to handle the nanosecond resolution typically permitted by simulators (Fig. 8.3).

Also the simulation environment does not take into account the limited resources of testers. For example, testers have a limited number of comparison strobes and mask registers (the mask registers disconnect strobes or timing generators from bidirectional I/O pins during a test). A designer might design, and successfully simulate, an IC with bidirectional pins that change direction frequently, and then find that the VLSI tester that will be used does not have enough mask registers to test the part. In addition, testers have a limited amount of pattern memory behind each pin, and can only apply a test vector that fits within that pattern memory (or reload the pattern memory to continue testing).

Most engineering workstations and ATE manufacturers offer post-processors, which are programs that bring simulation vectors and logic simulation outputs into the test environment. When simulation data are converted into production test vectors, some of the postprocessed vectors will not run on a real tester. If the test engineer cannot come up with a suitable set of test vectors, the designer will have to provide new vectors or redesign the IC.

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Figure 8.3
Designers typically specify a stimulus as a continuous waveform that can change at any time, but test equipment can only apply a
stimulus within predefined cycles with a programmed transition delay time and pulse width.

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When simulation does not reflect tester limitations, circuit designers do not know whether their product will be testable on a real tester. Neither do they know how the tester itself will affect product performance. For example, the driver/sensor pins on a VLSI tester can affect the capacitive loading on the output pins of an IC and, as a result, change the timing. If this type of problem is not modeled during simulation, erratic behavior will result when the device is being tested.

Valid initialization routines are not always provided for in the circuit implementation. As long as the logic simulation produces the correct result, the designer rarely considers how the physical chip will be initialized. Simulators provide the designer with special commands to set the state of the circuit. However, testers cannot perform these same commands. This causes a test engineer to spend a lot of time trying to initialize the circuit to the proper state before the test can begin.

Also, random or nondeterministic test vectors cause tremendous difficulty during test program debug. Since these test vectors have nothing in common with the functionality of the circuit, when a test vector is consistently failing, it can be very hard for the test engineer to locate and correct the source of the problem. Even the designer has difficulty isolating the problem because the vectors have been developed randomly without a logical sequence that can be understood by either the design or test engineer.

In summary, logic simulation vectors allow one to establish the functional and timing integrity of a design. In contrast, test vectors are used to verify that a chip is free of defects only to the extent detected by the vectors applied to the fault model used. The dynamic simulation of a circuit by a tester is subject to constraints that do not affect a logic simulator. Testers have a limited test frequency that is slower than the operating speeds of many systems and chips. Also, inputs to the circuit being tested inevitably experience skew that can be attributed to ATE pin electronics drift and differences in the signal paths to the device under test. Finally, completeness of test vectors is important, because the primary objective for the design of test vectors is high fault coverage rather than functional verification.

As the designer's involvement with fault simulation increases, the test engineer also benefits. The more extensive the designers' test patterns are, the more they help the test engineer get going. Thus, fault simulators are useful for both design and test engineers. The test engineer needs a fault simulator to build the test program and to evaluate the validity of the test patterns.

The IC designer needs the fault simulator to check whether the inputs to the verification exercised every part of the circuit. However, the designer does not use the fault simulator until most of the design is completed. It tells whether the test patterns are adequate. Fault simulation helps the designer find logic errors, such as redundant logic elements, before a design is cast in silicon.

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Test Generation and Fault Simulation

Test generation involves the search for a sequence of input vectors which cause relevant faults to be detected on the primary device outputs. However, a complete set of functional vectors does not imply an adequate test. With VLSI circuits, test generation is complicated by buried flip-flops, circuit initialization needs, asynchronous circuits (timing races, hazards and multiple transition times), complex clock conditions and edge rates, indeterminate states, nonfunctional inputs, switching multiple inputs simultaneously, and susceptibility to overshoots and undershoots. All of these must be addressed when developing a test strategy. They demand attention at the circuit design stage, and they depend on an intimate knowledge of the internal circuit details.

The goal of test generation is severalfold: chip design verification in conjunction with the chip designer, incorporation and implementation of the customer's specification and/or patterns into a manufacturing test program, and fault detection by using means such as fault simulation. Fault simulation is an analysis of the operation of a given circuit design under fault conditions. The chip designer must analyze, classify, model, and test the potential physical failures of VLSI circuits based on the technology. In addition to architectural issues, the principles of both logical design-for-testability and physical design-for-testability (device layout) must be applied so that the resulting circuit will be testable and cost-effective (trade-off chip size vs. testability) to produce.

Fault simulation initially requires a good circuit simulation; thus, it is closely related to logic simulation and timing analysis. Logic simulation tells one how the IC works, that is, it verifies the functionality of the design and ensures that all of the timing constraints are met. Fault simulation tells one if enough analysis has been performed so that the IC can be produced. It helps get silicon back that is right the first time.

Logic simulation is essential to the design of VLSI circuits. The logic simulation allows the design engineer to create a circuit model in software and simulate this mathematical representation as if it were a physical breadboard or prototype of the circuit. Thus, a design can be totally exercised and its performance analyzed without fabricating a single wafer.

The basic function of a logic simulator is to imitate the behavior of a circuit whose various physical parameters have been described to it via applicable design and process models and rules. That is, given a sequence of input signals to the circuit, it predicts what the output signals should be. In addition, the logic simulator provides the means of inspecting logic values on internal portions of the circuit. The design simulator takes the place of an engineer's paper, pencil, breadboard, and benchtop instruments. Designers use the simulator to create a model of the IC. The designers create a simulation of the design and then exercise that simulation to make various performance and functional measurements instead

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of using benchtop instruments like oscilloscopes, power supplies, pulse generators, and logic analyzers.

After the circuit designers believe they have a good design, and want to fabricate that design, they will attempt to develop a set of functional test vectors to exercise the real physical device. When they believe they have created the proper set of input stimuli, they run them through a fault simulator, which provides a measurement of how well they have done.

In fault simulation, the true value behavior of a circuit and the behavior of each possible fault circuit are simulated using fault models. A fault model for a circuit is a computer model of the circuit that has been modified to conform to some premise or conjecture about real physical defects. Fault models assume an abstract model of how a product fails; a fault model is a hypothesis. Computers can understand a fault model, but have difficulty dealing with actual defects [2,3].

To use a fault simulator, one starts by modeling circuit faults. A fault list is generated that identifies all faults that are to be modeled. Next, a set of test vectors is simulated against a fault-free model and all of the fault models. Those faults that cause an erroneous signal to appear at some output pin of the circuit model during fault simulation are flagged as detected. Fault coverage is computed as the number of faults detected, divided by the total number of faults modeled [4]. If the fault coverage is not sufficiently large to permit reaching the desired quality level, more test vectors are created and simulated. If the test does not spot the fault, either the test or the circuit design is incorrect. To correct the test, one may need either additional input waveforms to improve the test patterns, or to add an extra package pin. If the test is not the problem, then the circuit design is the source of the trouble, in which case circuit modification or partial redesign might be required.

The most widely used fault model in testing has been the single stuck-at fault (SSAF) model that assumes all failures occur because one of the signal nodes becomes shorted to one of the power rails. Table 8.3 summarizes the salient features of the single stuck-at fault model. Other models, such as the stuck-open fault model and the bridging fault model, as summarized in Tables 8.4 and 8.5, respectively, are gaining increased use due to the limitations of the SSAF model.

Test coverage has a significant impact on quality. Quality and cost of repair are driving fault grading and simulation. It is important to note that fault coverage and quality levels are not necessarily one and the same. High fault coverage is not an indicator of high-quality ICs. Quality cannot be easily related to fault coverage and thus the actual physical defects.

Test coverage numbers are typically derived from simulations of fault models that have little to do with the way that the faulty chips behave. For example, while it has been shown [911] that bridging faults are the most

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common type of failure in some technologies, the stuck-at fault model is still used more often than the bridging fault model primarily because designers have a long history of using it and are comfortable with it. Nonetheless, the single stuck-at fault (SSAF) model is not a reliable predictor of quality levels, and is insufficient to measure the quality of dense CMOS ICs and VLSICs. One hundred percent fault coverage using the SSAF model yields a high level of further defects (lower quality level). High stuck-at fault coverage is necessary but not sufficient

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to obtain a high-quality level. The SSAF is not dominant in CMOS failures; therefore, more accurate defect-oriented approaches are now being used by many IC suppliers. The SSAF model must be supplemented to address the following faults:

Multiple stuck-at faults

Transistor stuck-on faults

Bridging faults

Delay faults (slow-to-rise, slow-to-fall faults)

Transistor stuck-off fault (also called the CMOS stuck-open fault)

IDDQ variation

Effects of noise and other circuit interactions

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Bridging faults (faults between unconnected lines) may be responsible for up to one-half of all the faults. However, the majority of random defects in static CMOS ICs manifest themselves as timing delay faults [12], that is, faults where increased propagation delays cause gates in the circuit to exceed their rated specification, rather than a catastrophic failure. Per IBM, the predominant cause of delay defects in CMOS ICs is resistive openings in the first layer metal.

Static designed CMOS ICs have a transient power supply current that peaks when logic gates are switching and then settles to an extremely low current value during the quiescent state. This quiescent power supply current [13] (also known as IDDQ or standby current) is an effective test to detect leakage paths due to the following defects:

Gate oxide shorts

Parasitic transistor leakage

Bridging defects

Leaky p-n junctions

Punchthroughs

Open drain or source defects (stuck-open faults)

Open gate defects

Transmission gate opens

However, not all delay faults will elevate IDDQ. The measured IDDQ of a defect-free CMOS IC is approximately 20 nA. Most physical defects elevate IDDQ by one to five or more orders of magnitude.

Thus IDDQ tests uncover many shorts not detected by the SSAF model. IDDQ tests can also be used to diagnose failure mechanisms, processing problems, and design errors before they get out of control. Experimental results show a clear relationship between IDDQ tests and the quality and reliability of devices in the field [13]. As a pass/fail production test, IDDQ testing provides a better quality metric for physical defects as opposed to conventional testing based solely on the assumption that all IC abnormalities produce internal stuck-at faults or incorrect logic outputs. The use of IDDQ tests in conjunction with functional logic level testing can discover between 2% and 11% more failures in a given population of parts than would otherwise be detected.

Fault testing has an advantage over functional testing since a fixed number of faults exist in a circuit and their detection by a test set can be graded. Fault testing has disadvantages in that the failure mechanism often does not match the fault description, especially for CMOS circuits. However, it should be noted that it is impossible to model all faults that could conceivably occur in a circuit.

Testing for defects is the only way to achieve zero defects in product output. However, opens, shorts, and parametric defects require multiple test strategiesthere is no single magic test for zero escapes.

All test sets are evaluated against their ability to detect real defects. Thus,

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a strong failure analysis effort must be maintained in order to determine exactly what the real defects are. Examples of real CMOS IC defects include the following. (These are discussed in detail in Chapter 15.)

1. Gross defectsscratches, mask blotches, and cracks

2. Gate oxide shorts

3. Bridging across metal, polysilicon, and diffusion interconnect regions

4. Leaky p-n junctions

5. Transistor punchthrough

6. Parasitic transistor leakage

7. Open-circuit defects at gate, source, and drain terminals

8. Defects that cause errors in timing due to subtle imperfections in construction, such as increased via resistance or transistor threshold increases

Most common defects are metal shorts that result in an intermediate voltage level. Scan test does not detect this or many open defects in both transistors and metal. Narrow open-circuit defects in CMOS ICs often result in a gate that functions at low frequencies, but fails at high frequencies. These narrow opens can be caused by electromigration, poor step coverage, and stress induced voids.

In summary, the expected quality level can vary greatly depending on what type of failure or failures are occurring, and what type of failures were targeted by the test vector set. This means that in order to expect the predicted quality level to match reality, the fault model used must also match reality. Thus, the test coverage must be based on fault models that accurately describe the behavior of faulty chips, and that the simulated faults accurately represent the failures that actually occur, that is, physical defects. However, more than one fault model may be necessary to model the behavior of all of the potential defects that can occur with a given process.

When the same simulator is used for both design and test, it supplies the designer and the test engineer with a common data base; the test engineer thus inherits much critical design information that previously had to be generated from scratch, with the result that test program development time can be cut by 50% or more.

Highly accurate simulation capabilities also make product development more efficient by improving the quality of both the VLSIC design and the test program. By rigorously screening complex designs for subtle logic and timing errors, and by flagging testability problems (such as the omission of initialization mechanisms or the existence of unwanted feedback paths), simulation helps designers create products that not only function reliably but, in addition, can be tested efficiently in production.

A simulator that can model the characteristics of the target test system, as well as of the circuit to be tested, can save valuable test integration time, while

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ensuring that the test programs developed are executable by the tester. The fault simulator must relate the actual possible physical faults or defects inherent in the fab process to the fault model.

A fault simulator cannot evalute the coverage of physical faults that are not covered in the fault model, such as short circuits in metal, diffusion, or polysilicon, shorts between semiconductor layers, or parametric irregularities. The simultaneous occurrence of two or more faults is also not simulated because of the very large number of possible fault combinations, even though a processing defect is quite likely to lead to multiple faults, especially with small circuit geometries.

Redundant circuits can also affect the accuracy of fault coverage simulation. They allow faults that are not detected in a test because the faults do not cause a circuit to work improperly. In addition, simulators have no way of distinguishing between faults hidden by redundant circuits and valid faults that the test program simply cannot identify.

The model of the fault distribution predicts that for denser chips, a higher degree of fault coverage is needed to obtain the same quality level. In smaller geometries, a defect caused by a dust particle, for example, will damage more gates, because the particle will be larger relative to the gate size. Also, defects tend to cluster rather than occur uniformly across the wafer. Since more gates will thus be affected by a single particle, there will be more faults to flag the effects it causes.

An estimate of the number of faults that will be uncovered by a chip test goes a long way toward reducing the time needed to generate tests. The overall process of generating a test program for a chip is like shooting at a progressively smaller target. The first set of patterns may test and detect, say, 70% of the possible faults in a circuit. An additional set of test vectors will detect another 20% of the faults, increasing the total coverage to about 90%. As the coverage increases, the value of each additional test decreases. At approximately 90% fault coverage, the test strategy is usually changed; at this point, specific nodes of the circuit that have not yet been tested are targeted with specific vectors. They generally push the fault coverage to between 95 and 98.5%.

The key to estimating fault coverage in this way is computer simulation; only by simulating a circuit can the fault coverage of test vectors be evaluated. The test engineer simulates each possible fault in a circuit to determine whether that fault was uncovered by the test. This indicates the fault coverage of the test vectors.

The next step in the fault analysis process, which appears simple on the surface, is the generation of a test pattern. The test engineer takes the input stimulus and the expected response, expands that, accounts for such things as circuit initialization and ATE peculiarities (timing and strobe conditions), and then creates the proper set of conditions necessary to make all of the DC and AC measurements.

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In an ideal situation, a complete test program, including AC and DC parametric measurements would be generated as part of the design cycle. Unfortunately, there are a number of problems that must be overcome before this is possible. In general, the biggest problem is that the designer does not have a full understanding of what the circuit test requirements are. Furthermore, from a testability standpoint, both logic and fault simulation suffer from the same deficiency. They do not reflect the limitations and physical resources of the tester that will be used. For example, ATE is much more limited in terms of timing and flexibility than the logic simulators the circuit designer works with, causing many problems when trying to directly convert test vectors unless tester limitations are taken into account during design. In addition, parametric measurements require certain setup procedures with which the designer may not be familiar and that logic and fault simulators do not require.

Other Methods of Applying Simulation to Test

Besides the usual procedure of logic simulating functional tests and fault simulating manufacturing tests, there are several other ways to apply logic and fault simulation to test. They include methods for quickly assessing the testability of the circuit early in the design process and for verifying incremental fault coverage due to newly generated tests.

1. Toggle test the functional test vectors.

2. Fault simulate the functional vectors.

3. Fault simulate each new test vector after it is generated.

Toggle Testing

Toggle testing is the simplest and least time-consuming method of applying simulation to test. Functional tests can be used in the earliest stages of development to estimate the testability of a design. Toggle testing is used to provide that measure by checking the activity of circuit nodes. This is accomplished by tracking circuit activity resulting from a set of test vectors, and identifying those parts of a network that exhibit no activity. Any node that has not toggled obviously means that the applied test vectors did not affect that node and that faults on such nodes will not be detected by fault simulation.

Toggle testing is faster than fault simulation because it is based on logic simulation only. Unfortunately, toggle count is limited in that it only shows whether a node can be activated by a test and does not address observability of the node. Therefore, devices with good toggle count scores may still have low fault coverage for the same tests. For this reason, fault simulations should be run to determine the fault coverage of the tests once a high level of circuit activity is detected through toggle testing.

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Fault Simulation of Functional Tests

Using logic simulation in the development process is not a new concept. For years IC suppliers used functional simulation to verify the operation of digital circuitry. But using fault simulation in the IC development process is relatively new. Fault simulation can be used early in the design process as an effective design analysis tool. The outputs of any fault simulation algorithm include lists of detected faults, potentially detected faults, and undetected faults. These lists can be used to locate potential problems with the testability of the design, which typically include redundant or untestable logic. Correcting these problems early in the design cycle can result in substantial savings in development and manufacturing.

Fault Simulation After Each Test Vector is Generated

Fault simulation is also used to determine the quality of the test vectors generated to enhance fault coverage. High-quality tests for a complex VLSI circuit may often take many man-years to develop resulting in high costs and significant delays before the product arrives in the marketplace. To generate high-quality tests in a reasonable time requires effective software and hardware, which consist of a test pattern generation system, and a fault simulator. Tests are first generated to detect specific faults and then processed through the fault simulator to determine their quality.

It is important to fault simulate the design after each new pattern is generated, because, even though a pattern was targeted to catch one fault, new patterns usually catch multiple faults, and since accelerated fault simulation is often faster than test pattern generation, it is more efficient to eliminate these extra faults.

Testability

Closely related to fault simulation and test program generation is testability. Designers use testability measures to identify portions of a circuit that would be difficult to test. Because a product's testability ultimately depends on its intrinsic design characteristics, it makes sense to make testability the designer's responsibility. A circuit element, such as a gate, is testable if its inputs are controllable and its outputs observable. That is not much of a problem with a single gate. However, if a gate is isolated by thousands of others, it may be impossible to control its inputs with test vectors or propagate the output to a location where it can be observed.

Testability analysis examines each node in the design and determines how difficult it is, using the chip's input/output pins, to control and observe the logic value at a node (to test the circuit). Testability analysis has its greatest value

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during the design phase before designs are committed to silicon. The key question that must be answered is, is this design testable?

An overall testability measure for a circuit is derived by calculating the difficulty of testing each node in the circuit. Testability analysis programs are computationally simpler than generating a test vector set for a chip, and thus they can be used relatively quickly while a circuit is being designed on a computer. After identifying a general section of a chip that has poor controllability or observability, the designer can then modify the circuit to make it more testable.

However, the usefulness of testability measurement programs is limited. Analytical approaches have failed to relate the results of these programs to the fault coverage of particular circuit nodes. Testability measures are poor indicators of which specific faults in a circuit will remain undetected and which will be detected by a test program. They are good, however, for indicating blocks of circuitry that may be hard to test.

Current design practices lead to many test problems. Since designers are primarily concerned with generating a circuit that meets functional specifications, many test problems are created during the design of the circuit. As mentioned earlier, most designers do not consider the problem of initializing the circuit into a known state, and when they do consider it, they rarely add extra circuitry to shorten the initialization procedure. Therefore, test engineers have to develop special initialization routines that designers could have developed in less time.

Sequential circuitry and cascaded latches can make test programs extraordinarily long. Test information has to be sequentially clocked through this circuitry; therefore, it can take considerable time to test each portion of the circuit. Instead of a single vector being used to test a portion of the circuitry, a sequence of vectors is required.

The way in which a testability measurement program operates depends on whether a circuit is largely sequential or largely combinational. A combinational circuit is basically a hierarchy of logic gates through which a signal will propagate in a single clock cycle. In such a circuit, controllability and observability are defined in terms of the number of logic gates that a test program must manipulate to either control or observe a node.

Sequential circuits generally have registers that must be clocked to allow signals to propagate. In these circuits, a series of state transitions must be made in order to control or observe a node. Thus, controllability and observability are defined in terms of the length of the sequence of inputs needed to control or observe a node.

Testability analysis programs do not work well with sequential circuits, because such programs are based on making some approximations when analyzing complex circuits. In combinational circuits the complexity does not increase proportional to the circuit size as much as in sequential circuits, for which approximations cause great inaccuracies.

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This limits the usefulness of testability analysis programs, because most chips are a combination of both sequential and combinational circuits. Some circuits, such as microprocessors, are largely sequential, with relatively little combinational circuitry embedded in the chip.

VLSI circuits often contain embedded RAMs and ROMs (read only memories). These memory devices require many test vectors for an adequate test, and without direct access to their inputs and outputs from the package leads, they can be extremely difficult if not impossible to test. In these cases, either design-for-test (DFT) or built-in self-test (BIST) techniques must be used and the appropriate circuitry embedded on chip by the designer. There are many testers available for specifically testing RAMs and ROMs, but current IC testers lack the vector depth and algorithmic capabilities to sufficiently test embedded memory devices.

Redundant circuitry and error-correcting circuitry (ECC) cause severe test problems as well. The purpose of redundant or spare circuitry is to correct an error so that it does not appear at the output of the circuit. However, in testing the IC, this circuitry may mask imperfections that occur during processing unless special test circuitry is available that allows the circuit to be tested both with and without the redundant or error-correcting circuitry being activated.

ECC that is rarely excited during normal operations can be very hard to test as well. This circuitry often involves a complicated sequence of stimuli to activate the circuitry, and an even longer sequence of stimuli to determine whether the circuitry is responding correctly. These long test sequences imply that the circuit spends a lot of time on the tester, while these small portions of circuitry are tested.

Testability has a greater impact on ASICs, because any difficulty encountered in test development is normally exacerbated by the geographical separation between the designer and test engineer. The problem is minimized if the designer is readily available to answer questions. Without details of the circuit, the test engineer is severely limited and must rely on pass/fail criteria to analyze a problem. For example, often, due to race conditions, improper simulation, or incorrect specification parameters, the test engineer cannot pinpoint the problem or draws incorrect conclusions because the real problem is masked by other symptoms. A race condition can appear as a threshold problem from the outside due to the rise and fall of the competing input signals (creating the race problem).

This iterative test development process uses the functional pattern as the basis for the analysis. Long test patterns will complicate the analysis and should be avoided. One obvious way to come up with an optimized (short as possible) pattern is through the use of on-chip logic for controllability and observability. In addition to this, the designer should observe the following guidelines:

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1. Minimize switching transients by avoiding patterns that simultaneously switch several output drivers. However, in-use conditions require multiple output switching.

2. All functional patterns must stand alone within the capacity of the test system's functional test memory.

3. When using logic analyzers for capturing stimulus and response patterns (truth table), make sure that the strobe is well away from the signal transition regions.

4. Avoid race conditions and, if the simulation requires specific delays to collect them, document the timing and pass it on to the test engineer.

5. Add logic to allow software reset of all internal latches, that is, do not use the power-on reset circuit as the only means for resetting the device.

6. Run the simulation at different strobe and cycle times to ensure that the outputs were captured correctly (outside propagation delay limits).

7. Where possible, design patterns to allow compression through clock burst and subroutines.

Design-for-Test

Staying ahead of the competition means producing high quality, complex products that get to market quickly. As technology and customer needs advance, engineers are forced to overcome demanding challenges to meet design and test requirements. IC suppliers are becoming more aware that to maximize the quality of their products, they must employ design-for-testability (DFT) techniques and generate tests with high fault coverage.

As design complexity increases, obtaining high fault coverage levels becomes more difficult. Attempts to elevate quality levels can require significant resources and special expertisewith no guarantee of success. Such efforts can result in increased silicon area, compromised performance, and excessive time on the tester. Generating test patterns and evaluating them with fault simulation are time-consuming processes. Consequently, the development of ICs with demonstrably high fault coverage needs to be managed carefully in order to transfer products into production on schedule.

A number of test methodologies offer solutions to these problems. For years, fault simulation has been used to determine the effectiveness of test vectors in identifying faults that may occur during manufacture. Sometimes even fault simulation is not sufficient. Comprehensive strategies based on adherence to specific design disciplines, the addition of DFT structures, the use of the best available tools, and the involvement of an experienced engineering staff are all critical to developing an approach that reaches the highest fault coverage levels.

Design-for-test is a process in which a deliberate design effort is expended

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to assure that the VLSI circuit is testable with minimum effort and cost and that high confidence may be given to the test results. It is the most effective means of reducing test development and production costs. Without design-for-test rules, designs may be testable, but the probability of creating an inherently testable design decreases sharply with increasing circuit complexity. All design-for-test methods are techniques that ensure a design has adequate observability and controllability to allow complete and efficient testing. An observable node can easily be read from one of the IC outputs; that is, one can easily determine the state of that node. Controllability is the ease of controlling or forcing a node to a particular value. Complete testing of a logic network involves forcing every node to each logic state and verifying that the node took that logic state.

For sequential circuits, chip designers are increasingly employing a technique known as scan design. Scan design gives the engineer access to sequential circuitry by adding registers and creating artificial paths built into the circuit especially for that purpose. Through clever placement, the end effect of these artificial pathways is to temporarily convert sequential circuitry into combinational circuitry for testing purposes.

With scan design, however, the engineer is not actually testing the circuitry by operating it as it was intended to operate in the functional application. Instead, the chips are designed to be put into a mode for testing each logic gate with a much simpler program than would otherwise be possible. Thus, with the aid of computer programs not available for sequential circuits, the engineer can usually generate test vectors in a few hours.

The price that designers pay for using scan design is a requirement for additional logic in a circuit-increased chip size. This overhead, which degrades the performance of the chip somewhat, results in much quicker test generation than most alternative ad hoc methods.

Most design-for-test techniques subdivide or partition the testing problem into manageable and known forms: to improve observation and control and, thus, ease the automatic test generation problem, and to reduce the size of the network that is fault-simulated, reducing costs.

Ideally, a partitioned circuit would be designed with a test mode that would connect the inputs and outputs of each partitioned block to the output pins of the chip, so that the block could be observed. Test vectors would be multiplexed in the test mode through a set of input/output pins. The I/O pins would be used for each block in succession until the entire chip was tested. Partitioning has been used primarily in circuits, such as microprocessors, that have architectures with natural partitions. At present, there is no economical way of imposing partitions on otherwise unstructured circuits.

Typical design-for-test rules are summarized in Table 8.6.

Some of the currently popular design-for-test techniques that have received in-depth coverage in the technical press are serial scan, LSSD, boundary scan,

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Table 8.6 Design-for-Test Design Rule Summary

Design initializable circuits.

Avoid redundancy.

Avoid race conditions.

Avoid asynchronous timing.

Provide access to device clocks.

Allow feedback to be opened/closed.

Provide access to major buses.

Use wired logic cautiously.

Use control and test points.

Use circuit partitioning and selective control.

signature analysis, BILBO, unstructured design-for-test, and IEEE Std. 1149.1. These techniques are covered in depth by the reference works listed in this volume and by the many papers contained in the Proceedings of the International Test Conference.

There is a real need for design tools to interface closely with the IC production areas that have traditionally been responsible for test (wafer probe and final test) as well as enhancing design engineering productivity.

Engineering Workstations

The emergence of engineering workstations to provide computer-aided design tools for VLSI circuit design allows functional pattern data from the IC design phase to be available for transfer to the test group. Test vectors developed during logic simulation, and validated and optimized during fault simulation, are used to verify ICs on the production line. The engineering workstation addresses the quality of the design through various design verification processes, while the quality of the manufacturing process is verified both by process monitors and test structures and by electrical testing using ATE.

Since most VLSI circuits are designed using CAE systems (computer-aided engineering; engineering workstations), the test development environment should also be able to use information present in the design database to help create the production test. CAE design files often contain pin-outs, physical packaging dimensions, process parameters, and timing requirements, as well as functional-stimulus and expected-response patterns from simulation runs. Properly used, these data can be the starting point from which fixture descriptions, test patterns, and test limits for standard production tests (wafer probe and final electrical) are produced automatically.

Ideally, CAE workstations allow an engineer to move quickly and easily

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from the concept stage to the finished, detailed design, and automatically generate the programs needed to test the circuit. Although none of the currently available systems provide this totally integrated start-to-finish capability, some are getting very close, and they all offer aids that relieve the designer of many noncreative, repetitive, and error-prone tasks. In addition, these systems allow the test engineer to move development work from the test system to the workstation.

Current graphics-based workstations allow the circuit designer to create and draw functional block diagrams and schematics utilizing IC data and symbols resident in extensive element libraries. Utilizing this circuit design information as a data source, a variety of software tools can access this same central data base to perform many analytical, fabrication, and test-related tasks, including the following.

1. Functional, logic-level, and circuit-level simulation utilizing device models of actual devices

2. Logic analysis and timing verification

3. Thermal analysis

4. Circuit testability and fault coverage analysis

5. Fault simulation

6. Test program generation

7. Auto diagnostics and repair instruction development

Computer-aided testing (CAT) is that subsection of computer-aided engineering (CAE) concerned with either the creation of test vectors (the digital inputs and correct outputs of a circuit used to verify correct operation) or a test program [the actual software for the test computer (ATE)] that performs the automatic test. CAT tools include logic simulation, testability analysis, fault simulation, and test vector generation and grading. Thus, as can be seen, CAT tools occupy a portion of both the design engineering and test engineering disciplines. As such, these tools are eroding the traditional barriers that have separated these disciplines, and allow both design and test engineers to address the issue of testing.

Testability's foundation is a suite of software programs that work off the same data base as simulation, tightly interwoven within the CAE environment.

As engineers enter and verify schematics on CAE workstations, they create a complete design data base that includes the entire circuit's logical behavior. Tools that tap the design data base effectively allow engineers to improve the testability of the design early in the design phase, provide a comprehensive test pattern to detect production defects, and facilitate functional test patterns derived from simulation to be used directly by the ATE. Fault simulation is the cornerstone of testability, but a fully integrated test solution aids design testability and reduces test program development time.

Testability tools of varying functionalities are offered by software vendors,

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special test houses, and ATE vendors. The missing ingredients are an interactive environment and the ability to integrate these tools with accurate simulation tools. Design engineers need the ability to apply the testability tools interactively and modify the designs at a conceptual level before committing themselves to a gate-level description. Furthermore, these results must be consistent with results obtained through logic simulation and timing verification.

In essence, these testability tools must form a tightly coupled link with the verification phase. All test and verification tools must be linked to, and operate off, the same data base and use the same models, thus ensuring that results from fault simulation will always be consistent with results from logic simulation. The link is critical because different logic and fault simulation results can cause an inaccurate level of confidence in the test vectors.

The structure of the link allows CAT and CAE to occur in parallel, saving time by making it a simple step for the designer to monitor the design's testability. Design engineers produce a more testable design if they can determine testability early in the design phase, and continue to monitor and evolve the testability as their verification progresses. Trying to look back at testability after physical implementation is fruitless.

There are also a few CAT tools that aid in the creation of test programs. These tools typically translate from a higher order test language to the detailed language of the particular tester (ATE). Automated test program generation (ATPG) takes the test vectors generated by the circuit designer and translates them to the tester language. ATPG software packages drastically reduce the engineering cost of generating the test programs for a VLSI tester. ATPG software can accommodate test patterns generated either manually or by a CAD system. Furthermore, ATPG can also ensure that the test program performs no illegal and equipment-damaging switching of tester resources, such as hot switching of relays.

ATPG converts patterns from a variety of input formats to the required tester format. The input patterns could come from simulators or from a different test system. While the routine can be as intelligent as desired, in its simplest form it converts patterns as a straight-line code. A more useful form converts the test patterns, compresses them into the best form for the specific ATE pattern processor to be used, and, if needed, breaks the test patterns for multiple passes if the ATE lacks the resources required to implement a specific set of test patterns.

The most noticeable feature of test programs produced by current CAT systems is the absence of pattern, structure, or intuitive meaning. The main cause of this phenomenon is the local view taken by all the algorithms, which have no knowledge of the circuit's overall structure and function. This knowledge is a primary attribute of the test engineers that developed the earlier generation LSI test programs.

To handle test problems with the complexity of current VLSI chips, CAT

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architecture must develop to a point at which techniques can be applied that are similar to those used by human experts. An expert (test engineer) uses previous knowledge and experience to create his test algorithms. Future CAT systems must contain a reference library of testing techniques and solutions that can be used to produce and implement a test strategy. Such systems will be interactive; they will let users select alternative algorithms for all stages of production test and make decisions for algorithms, in a standard cell design approach, for example.

A major problem with CAT pattern generators is that they produce a voluminous number of test patterns, more than can or need to be tested. The test engineer must then take these and reduce them either manually (which is most often the case) or with an automated compression technique determining which patterns are redundant, which are not likely to occur, etc. Because of this, it is far easier in many instances to take the functional approach to test vector generation.

At present, there is no completely automated and single means of taking the logic diagram, performing logic and fault simulation and testability analysis, and generating the ATE test vectors. Thus, although automatic test program generators do exist, the reality is that for most involved, generating test programs is still a highly intuitive task that involves some manual intervention due to the large number of test vectors created and the cost of simulation. IBM found that even by using signature analysis in conjunction with LSSD and logic and fault-simulation techniques, 25% manual intervention was required to provide adequate fault coverage for unsimulated faults. Although computer-aided design and test tools have helped speed IC design, development, and test, the interfaces and compatibility between the various tools are extremely poor.

For CAT to be successful, it must utilize efficiently and cost-effectively, to the fullest extent, the ATE to which it interfaces. Test vectors in the workstation must find their way to the target ATE system.

At present, realizing this shortcoming, several workstation manufacturers have signed partnership agreements with ATE manufacturers to work on solutions to this problem for given test systems. An intensive effort is presently underway to standardize interfaces between CAE, CAD, and ATE systems. The Electronic Design Interchange Format (EDIF) is a team effort by IC suppliers, CAE manufacturers, and ATE manufacturers that has developed a universal format that allows transfer of IC design data to silicon foundries and test data to ATE systems without a clumsy interface process. EDIF is neither a programming language nor a data-base system. Rather, it is a single, large data structure or format for the transportation of electronic design information.

Ate Software Verification

Software is becoming an increasingly larger part of the IC manufacturing process. As such, systematic testing of the software to find latent defects and verify

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conformance to requirements is important to ensure high-quality software. Additionally, better methods are needed to decrease testing time. Once an IC test program is completed, the test engineer must verify that it does what it is supposed to do, namely, exercise and test the device accurately and completely. With manually generated test software, every step (line of code) in the sequence is comprehensible and checked by the engineer for manually generated errors. Based on their levels of experience, the test engineers can almost sense when something is not correct.

In contrast, due to complexity of VLSI circuit test programs (especially with automatically generated test vectors) and due to the fact that it is not feasible to manually check each step in the test sequence, fault simulation and logic modeling errors could show up in the automatically generated truth table. Thus, the test program must be checked or verified.

The software requirements and testing process should include the test plan, the IC device specification, the chosen tester rules and instructions, and development standards and rules. Software testing is a difficult process to perform whether it be manually or automatically. Furthermore, the software testing process is further restricted because computer-automated programs for verification of test software are very limited.

A number of techniques exist for checking ATE software. Some techniques can easily locate certain sources of errors, but may prove less useful for detecting other types of errors. The blend of hardware and software in ATE points out the need for a method that will exercise the inputs, outputs, and associated routines, regardless of who writes the test programs. Software specialists, for example, may lack the necessary insight into hardware complexities and introduce related errors into test programs. On the other hand, hardware specialists, with some software experience, may not possess the requisite software familiarities to know how to mate hardware with software.

One method of verifying the integrity of the software is to run the software generated from fault simulation and logic modeling against a discrete implementation of VLSI circuit. The test vectors are fed as inputs to the discrete implementation and then the outputs are monitored for functionality.

Another method is to use software simulations to exercise the inputs and associated routines under conditions that approximate those of actual test operations without utilizing the ATE itself. The problem here is that errors contained in the CAD/CAT logic modeling and fault simulation processes are further simulated and the errors compounded.

In order for one to use software simulation verification effectively, the test program must be broken down into understandable and comprehensible bite-sized chunks. Simulation is used only at those points that will provide the greatest chance of uncovering errors. Thus, the experience of the circuit designer who understands the structure and organization of the VLSI circuit working with

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the test engineer is of utmost importance. We just cannot get away from commonsense human intervention.

In most cases, concentrating on a single program module (e.g., a single test routine) proves wise, although test personnel can check a larger section if the particular program structure allows it. During the process of checking, remember that the purpose of simulation involves uncovering errors. With this approach, engineers can concentrate on ferreting out errors, as opposed to an approach in which the end purpose simply involves proving that the program functions correctly and does so by merely obtaining a few error-free runs.

Simulation techniques can detect certain categories of software errors more readily than they can others. The following categories of errors should be pursued when checking software with simulation techniques.

Errors in specifications and limits

Improper pass/fail routines

Incorrect commands to test equipment

Incorrect calculations

Incorrect READ/DATA and array statements

The main point of this section is that it is critical that the test software be checked and verified as being correct. Incorrectly written software, inaccurately written software, or software containing errors can cause both defective devices to be accepted as good and good devices to be rejected. The importance of testing software was affirmed by the panel sessions at the 1991, 1992, and 1993 International Test Conferences.

Conclusion

Effective test strategies including design-for-test must be an integral part of the VLSIC and ASIC development process, and are the only way to produce high quality ICs and manageable life cycle costs.

References

1. D. L. Crook, Evolutions in VLSI reliability engineering. International Reliability Physics Symposium Proceedings, New Orleans, Louisiana, 1990, pp. 211.

2. R. K. Fritzemeir, H. T. Nagle, and C. F. Hawkins, Fundamentals of testabilityA tutorial. IEEE Trans. Ind. Electron. 36(2) (1989).

3. J. Souza, Goncalves, and Teixeira, IC defectsBasic testability analysis, International Test Conference Proceedings, Nashville, Tennessee, 1991, pp. 500509.

4. R. B. Elo, An empirical relationship between test transparency and fault

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coverage, International Test Conference Proceedings, Washington, D. C., 1990, pp. 10061011.

5. J. M. Soden, R. K. Treece, M. R. Taylor, and C. F. Hawkins, CMOS IC stuck-open fault electrical effects and design considerations, International Test Conference, Proceedings, Washington, D. C., 1989, pp. 423430.

6. F. Ferguson, and T. Larrabee, Test pattern generation for realistic bridge faults in CMOS ICs, Session 23 of International Test Conference Proceedings, Nashville, Tennessee, 1991, pp. 492499.

7. Bridging and other faults in CMOS circuits, International Test Conference Proceedings, Baltimore, Maryland, 1992, pp. 466495.

8. IDDQ and logic testing of CMOS bridging faults, Session 3 of International Test Conference Proceedings, Baltimore, Maryland, 1993, pp. 5491.

9. J. Galiay, Y. Crouzet, and M. Vergniault, Physical versus logical fault models of MOS LSI circuits: Impact on their testability, IEEE Trans. Comput., C-29(6):527531 (1980).

10. W. Maly, Realistic fault modeling for VLSI testing, Proceedings of 24th Design Automation Conference, Miami Beach, Florida, 1987, pp. 173180.

11. J. P. Shen, W. Maly, and F. J. Ferguson, Inductive fault analysis of MOS integrated circuits, IEEE Design Test, December: 1326 (1985).

12. See Sessions 9, 34, and 43 of International Test Conference Proceedings, Baltimore, Maryland, 1993, and Session 6 of International Test Conference Proceedings, 1994, Washington, D.C. for more details on delay faults/testing.

13. See the following reference material for details of IDDQ testing: (a) C. F. Hawkins and J. M. Soden, Electrical Characteristics and Testing Considerations for Gate Oxide shorts in CMOS ICs, International Test Conference Proceedings, Philadelphia, Pennsylvania, 1985, pp. 544555. (b) C. F. Hawkins and J. M. Soden, Reliability and electrical properties of gate oxide shorts in CMOS ICs, International Test Conference Proceedings, Washington, D.C., 1986, pp. 443451. (c) Session 13: Quality and reliability I, International Test Conference Proceedings, Washington, D.C., 1987, pp. 300323 (d) Session 23: CAE for IDDQ testing, International Test Conference Proceedings, Nashville, Tennessee, 1991, pp. 598632. (e) Session 6: Should we go beyond stuck at faults to improve quality?, International Test Conference Proceedings, Baltimore, Maryland, 1992, pp. 151177. (f) Session 36: CAE for defect detection and IDDQ testing, International Test Conference Proceedings, Baltimore, Maryland, 1992, pp. 762787. (g) Session 3: IDDQ and logic testing of CMOS bridging faults, and Session 31: Novel and practical power supply current test techniques, International Test Conference Proceedings, Baltimore, Maryland, 1993, pp. 5491 and 626651. (h) IDDQ testing of VLSI circuits,

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special issue of J. Electron. Testing Theory Appl., eds. R. K. Gulati and C. F. Hawkins, 3(4) (1992). (i) Sessions 7, 18, 24, and 28 of International Test Conference Proceedings, 1994, Washington, D.C.

14. E. Kurzweil, M. Lallement, and R. Blanc, Catch the ground bounce before it hits your system, International Test Conference Proceedings, Baltimore, Maryland, 1993, 574584.

Selected Reading

1. M. K. Badawy, Getting the most from a cross-functional team, Electronic Business Buyer, August (1994).

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PART III
CONTAMINATION AND MANUFACTURING ERRORS*

The primary goal in the manufacture of integrated circuits is the highest yield, which translates to the lowest possible cost per electronic function performed. The main features of the IC fabrication process can be best understood in terms of this goal. These features include the fabrication of many circuits at a time, the reduction of the circuits to the smallest possible size, the maximum simplification of the processing technology, and most importantly, the elimination of defects in the various manufacturing steps.

The pervasiveness of electronics has been achieved as the result of smaller design rules and increased functionality of integrated circuits. The continual reduction in feature sizes (see Table III.1) of 1520% per year results in an increase in the number of defects because the smaller silicon geometries are more sensitive to smaller particles and defects. In Fig. III.1, which depicts this relationship, notice that the defect density per square centimeter per level increases with the square of the feature size reduction.

*Portions of this section used with permission from Ref. 1.

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Table III.1 The Path from Early VLSI to Complex ULSI (Ultra Large Scale Integration) [1]

Year

Minimum feature size (mm)

Typical die

1982
3 (VLSI)

64K DRAM

1984
2

1986
1.5 (Early ULSI)

256K DRAM

1988
1.25

1990
1.0 (Complex ULSI)

1M DRAM

1992
0.650.8

4M DRAM

1994
0.5

16M DRAM

It is assumed that any particle larger than 20% of minimum feature size is potentially damaging. This means that for ultra-large-scale integrated (ULSI) devices with 1-mm geometries, the maximum acceptable particle size will be roughly 0.2 mm.

With minimum feature sizes becoming smaller, process complexity is

Figure III.1
Effects of changes in minimum feature size on defect density [1].

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increasing rapidly. The result is an increase in the cumulative number of particle-critical masking levels in the manufacturing process involved in the defects-per-square-centimeter parameter. Concurrently, the size of the typical die is increasing in response to the need to place more functions onto a single die.

If present trends continue, process complexity will increase at a rate of about one particle-critical mask level per year, and die size will increase at a rate of about one particle-critical mask level per year, and die size will increase about 25 mils/edge every 2 years (Table III.2). Figure III.2 shows the effect on die yield of increasing the number of critical mask levels and increasing die size; it does not include the effects associated with reducing minimum feature size. The die-yield equation is highly sensitive to both cumulative defects per square centimeter and to die area.

The relationships between defect density, die size, and yield can be predicted using either the standard Murphy model or the Seeds model. The Murphy model was plotted in Chapter 3 (Fig. 3.46) and is repeated here in Figure III.3. Most MOS IC facilities are operating at 0.42.0 defects per square centimeter, whereas most older bipolar and BiCMOS fabrication lines are typically operating in higher defects per square centimeter ranges (Table III.3). The 0.5-mm advanced CMOS and BiCMOS defect densities are much higher than the 0.8-mm technologies. This is due to the newness of those processes. It has been predicted that by late 1994 the 0.5-mm technologies will have moved down the learning curve and exhibit 0.5 defects/cm² (CMOS) to 1.0 defects/cm² (BiCMOS) defect densities.

Overall, considering that probe yield is basically a function of die size and defect density, the only way for IC manufacturers to sustain adequate probe yields has been to decrease defect densities. Figure III.4 shows how the IC industry has met this challenge thus far. Moreover, the figure shows the defect improvement that must be achieved in order to economically produce the leading-edge IC devices of the early to mid-1990s. According to the Semiconductor Associations' (SIAs) technology roadmap, defect density must decrease

Table III.2 Process Complexity Trends [1]

Year

Process complexity (critical levels)

Die size (mils/edge)

1982

6

200

1984

7

275

1986

8

300500

1988

9

325750

1990

10

3501000

1993

1315

5001200

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Figure III.2
Effects of changes in number of critical mask
levels and die size on die yield [1].

from 0.1 defects/cm² (1992) to 0.002 defects/cm² (2007) in order to fabricate 16-Gb DRAMs, 4-Gb SRAMs, and 20M gate arrays. These improvements must come from all contamination sources, including process equipment, wafer handling, personnel, air, chemicals, and gases. Contamination (e.g., particles) is the largest contributor to wafer probe yield loss, as shown in Table III.4. For recently designed products, design margin (i.e., design within the capabilities of the process) is a larger factor than listed (1025% probe loss).

The following table shows the required defect density and minimum required particle detection size for producing ICs with a reasonable yield for a given feature size.

Year

1994

1997

2000

2005

Feature size (mm)

0.5

0.25

0.18

0.10

Defect density (#/cm²)

0.10

0.03

0.01

0.002

Required detection minimum size (mm)

0.100.20

0.030.05

0.020.03

0.010.02

The primary sources of wafer contamination include

Particulate (defect-causing)

Chemical (etchants and dopants)

Personnel

Chemicals and water

Equipment

Process

Chemicals and water

Personnel

Air circulation

Process

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Figure III.3
Murphy's probe yield model (as a function of defects/cm²).

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Table III.3 Typical 1993 Defect Levels

Process technology (defects/cm²)

Feature size (mm)

HMOS 7-10 masks

CMOS 14-16 masks

Advanced CMOS 18-20 masks

Advanced BiMOS 22 masks

Bipolar 8-10 masks

Bipolar 14-16 masks

Advanced bipolar 22 masks

5.0

1

-

-

-

3

-

-

2.0

1

1

-

-

-

2.3

-

1.5

-

0.6

-

0.7

-

1.3

0.7

1.0

-

0.5

0.4

0.9

-

-

1.0

0.8

-

0.4

0.5

1.1

-

-

1.2

0.5

-

-

1.5

2.0

-

-

-

Integrated circuits have historically been affected by particulate contamination. The smaller the feature size, the smaller the particle that can create a killer defect (a killer defect is one that will cause the IC to be inoperable). A report issued in the September 1991 issue of Solid State Technology stated that more than 80% of the yield loss of VLSI circuits can be attributed to random visible structural defects (or pattern defects) due to particles adhering to the wafers. Therefore, to attain adequate levels of yield and reliability in advanced devicesor to improve yield to more profitable levelscritical control of particulate contamination is required throughout wafer processing. Considerable effort (with much success) has been expended in reducing the level of manufacturing defects through air, human, and process material filtration as well as incorporating fault-tolerant design and advanced material filtration as well as incorporating fault-tolerant design and advanced material choices. Nevertheless, manufacturing defects continue to cause both yield and reliability failures.

Today (1994) clean rooms and personnel bunny suits are effective in preventing airborne and human-derived contaminants. Additionally, the materials, gases, and chemicals, used in IC manufacturing are very pure. The focus of particulate control has shifted to the wafer fabrication equipment, the processes themselves, and getting a clean-room-like environment in the package assembly areas. This improvement and change in the source of particulate contamination is graphically depicted in Fig. III.5.

A significant attribute of defects (especially particle defects) is the clustering effect usually encountered in IC manufacturing. The clusters of defects are often near the outer edge of the wafer. Some attribute these clusters to the build-up of particles in fabrication-line equipment. These particle clouds are then dislodged by vibration, changes in pressure, gas flow, etc. After landing on the wafer surface, the particle clouds display a clustering effect.

Another reason postulated for clustering is the electrostatic attraction to

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Figure III.4
Die size and defect density trends.

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Table III.4 Typical 1993 Silicon Wafer Probe Yield Losses

Probe yield problem

Yield loss (%)

Percent of total probe yield loss

Contamination

30

60

Process variation

7

14

Photolithography errors

5

10

Design margin

5

10

Material defects

3

6

Total loss

50

100

Probe yield (100%-die loss) = 50%

the open edge of the wafer as it sits in a wafer boat or carrier. Whatever the reason, the clustering effect of particle defects has been shown to exist.

Additionally, concurrent improvements in the flatness, cleanliness, and gettering characteristics of silicon wafers to enhance circuit performance and yield are required for fabricating ULSI circuits. Random leakage currents due to chemical impurities and structural imperfections, for example, result in excessive power dissipation, degraded power delay, and reduced refresh performance,

Figure III.5
Sources of particulate contamination.

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constituting one extremely important class of yield detractors for dynamic random access memories (DRAMs). The sensitivity of ICs to leakage currents is expected to become an even more critical factor due to the greater circuit complexity and demanding application requirements for ULSI circuits.

Each design, fabrication, assembly, and test step in the complex IC fabrication process has the potential for introducing errors that can affect device quality and yield in a serial additive manner. Thus, it is important that quality workmanship procedures be incorporated in each phase of IC design and manufacture. No area is exempt.

The quality issue (controlling and eliminating defects in designs, fabrication processes, assembly and test) is most critical to producing reliable integrated circuits. The following chapters address the issue of manufacturing errors, focusing on contamination, as they affect the quality of the finished device.

References

1. J. Burnett, World Class ManufacturingWhy Class I practice? Microcontamination, May (1985). Copyright © 1985, Canon Communication, Inc.

2. W. Maly, H. T. Heineken, and F. Agricola, A simple yield model, Semiconductor International, July 1994, pp. 148154.

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9
Contamination

Integrated circuit electrical performance and yields (i.e., quality) are the result of introducing only the desired impurities into the wafer and the ability to precisely reproduce the mask dimensions on the wafer surface.* Unfortunately, ICs are sensitive to unwanted contamination, even from amounts as small as several parts per million. Pattern dimensions, too, are altered by dirt as small as a few microns in diameter.

At this level of sensitivity almost everything in a normal production environment would be judged too dirty to make ICs. A considerable amount of technology and money must be invested in maintaining a clean IC production line environment. By way of comparison, a hospital surgical room is many orders of magnitude dirtier than a VLSI wafer fabrication area. The cleanliness requirement is particularly stringent in the photomasking area. Not only are all of the critical dimensions produced here, but the frequent chemical operations present many opportunities for accidental contamination.

The problem of contamination affects three areas:

*Portions of this section used with permission from Ref. 1.

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1. Device processing

2. Device performance

3. Device reliability

Device processing in a contaminated environment can cause wafers to fail in-process quality checks. Dirty air, water, gases, or chemicals can contaminate the wafers in process. Microscopic particles of dirt can cause holes in the sensitive photoresist layer. These failures result in lower fabrication yields and higher production costs due to reworking the wafers, if possible.

Contamination causes failure in integrated circuits through two methods. The first is a physical effect in which the particle shadows or masks an area from the intended process or punches through a thin process layer. The second is a chemical effect in which the contaminant is diffused into the product. The chemical effect is usually nonvisual, so microscopic inspection will exclude this contribution to the total percentage of items rejected for contamination-related defects. Device performance problems are those contamination-related electrical failures such as soft or leaky junctions and premature breakdown.

Contamination failures are the most insidious causes of poor device quality. Low levels of contamination can be introduced during wafer fab and/or assembly and not be detected during normal circuit testing. However, in time the contamination will migrate to the active devices and reach a level high enough to cause a circuit failure. In cases where low-level contamination is suspected through observed failure modes, environmental stress screens, which accelerate time-to-failure, are imposed on the finished IC prior to installing it in fielded equipment. The topics of IC failure modes and mechanisms and stress screening are discussed in later chapters.

As IC geometries become smaller, the likelihood of particulate contamination increases and the effect of this contamination on yield becomes more significant. Table 9.1 is an overview listing of particulate types and sources.

Particles larger than 0.5 mm are produced by mechanical abrasion

Table 9.1 Particulate Overview

Particle type

Source

Hair, skin cells, oils
Personnel

Fibers
Garments, equipment

Silicates, ash, carbon
Airborne dust

Metals, ceramics, polymers
Equipment

Oxides, chlorides
Corrosion

Salts, inert sediment
Wet chemicals

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processes. They are pieces of material broken from a larger object. The chemical composition of these particles is similar to the composition of the larger pieces from which they came. Sources of these coarse particles in clean rooms include people, mechanical bearings, vibrationally loosened particles, and robots, as illustrated by Fig. 9.1. The particles include pieces of skin, hair, cosmetics, dandruff, paper, metals, minerals, salts, other organic materials, filter pieces, wood pieces, and anything tracked in or carried in by people. Nearly anything that exists in any solid or partially liquid form may be found in the coarse particle form. These particles become airborne in clean rooms by movement of people, robots, conveyers, equipment, and turbulent air. These particles cause IC failure by bridging across a space between conductors, by breaking a conductive line, or by obliterating or damaging a device. While HEPA and ULPA filters remove

Figure 9.1
When people walk by a critical point, they carry a cloud of
contaminating particles with them. The turbulence caused by this
movement causes particles to move both vertically and laterally [1].

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almost all of these particles, turbulent eddies caused by a person walking by can cause these particles to become airborne and move vertically and/or laterally to contaminate a critical device without ever having to penetrate the filter.

Particles smaller than 0.1 mm (called nuclei mode particles) are produced by evaporation/condensation and combustion processes. In other words, they are generated by hot surfaces or processes. The hot process vaporizes material, which recondenses when the surrounding air cools the vapor. Since the surrounding air also dilutes the vapor quickly, the particles produced by this method do not have an opportunity to grow very large. Nearly all of them probably remain smaller than 0.1 mm until they deposit on a nearby surface or on a HEPA filter. Sources of these particles in clean rooms include ovens, hot bearings, and hot components on a circuit board, illustrated by Figs. 9.2 and 9.3. Their chemical composition matches that of the vapor, which may include lubricating oils, human oils, NaCl, and whatever contaminant may be on the hot surface that evaporates at the temperature of the surface.

It is important to recognize that the mechanisms that produce these particles usually have no relationship to the mechanical abrasion, which produces particles larger than 0.5 mm.

There are a number of ways that these nuclei mode particles may cause IC failure. Their high concentrations can cause multiple particles to deposit on a critical spot of the semiconductor during its manufacture. Since the thickness of semiconductor layers is often much less than the line width (in some cases, thicknesses of 0.020.04 mm are now being used), any particle that penetrates a layer can certainly cause failure. However, particles do not have to penetrate a layer or bridge between two conductors to cause failure. The chemical composition of the particle may cause that particle to poison a much larger portion of the semiconductor than the physical size would cover. Consider an NaCl particle, a

Figure 9.2
Mechanical devices such as conveyor systems may cause coarse particles from mechanical
abrasion and tiny condensation nuclei particles from hot surfaces such as hot bearings.

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Figure 9.3
Ovens contain hot surfaces, which can evaporate vapors, which
subsequently recondense to form tiny condensation nuclei particles.
Mechanical moving parts such as hinges can be a source of coarse
particles.

highly destructive contaminant for semiconductors. An oven can vaporize a trace amount of NaCl, resulting in millions of 0.02-mm NaCl nuclei particles. One of these particles can destroy an IC. There is another way for submicrometer particles to destroy ICs. If a 0.05-mm particle masks a small spot during the photomasking process, that spot may grow into a cone-shaped part of that layer during the subsequent etching process. The result is a layer-penetrating failure in the IC. Thus, these particles can cause failure of an IC because of vertical penetration of a layer, chemical poisoning of a much larger spot, photomasking of a sensitive spot, and degradation of a device caused by their large numbers. Inexpensive condensation nucleus counters can easily measure them.

Airborne particles in the 0.10.1 mm diameter range are called accumulation mode aerosols. Freshly generated aerosol particles are usually not in this size range, but begin their life in the nuclei range. They grow into this range by condensation and coagulation of smaller particles. The rates with which these two phenomena occur depend directly on the vapor and/or particle concentrations. Because clean-room particle and vapor concentrations are so low, it is doubtful if particle growth is the dominant mechanism for introducing these particles into the clean room.

It is likely that these particles come into clean room from a combination of two factors: (1) makeup air comes from the outdoor atmosphere, which has high concentrations of accumulation mode aerosols, and (2) HEPA and ULPA filters have their maximum penetration (minimum efficiency) for particles in this size range. Thus it is probable that these particles come primarily through the filters from the outdoor makeup air, as illustrated by Fig. 9.4.

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Figure 9.4
Recent HEPA and ULPA filters remove nearly all coarse and condensation nuclei
particles. However, they pass significant numbers of 0.11.0 mm accumulation mode
aerosol particles, which probably come primarily from makeup air.

These particles cause IC failures in the same way as particles in the higher and lower size ranges.

There is one more characteristic of clean-room particles that has been largely ignored by past discontinuous monitoring programs. Particle concentrations in clean rooms consist of two components: (1) a rather constant background level of particles for a room in steady-state operation, and (2) sudden bursts of particles from a source inside the room. The background level plays the major role in defining the class number for the room and is the concentration which exists during 95%, perhaps over 99.9%, of the time at any specific location in the room. It is this concentration that is almost always measured by a counter that is wheeled in every week for a few minutes. It is also the concentration that is nearly always measured by a properly operating single counter/rotary valve monitoring system.

Particle events are the usual way in which sources inside a clean room emit particles. They are usually very short events, 110 sec in duration. During this short time, the concentration at a single affected point in the room may reach hundreds of thousands of particles per cubic foot, even in a Class 10 room. This phenomenon occurs for all sizes of particles.

Consider the case of a person walking past a critical point in the process (Fig. 9.1). It is well known that people can be the largest single source of airborne particle contamination in clean rooms. As the person walks past a critical point, he produces thousands of coarse particles, which are carried along in his turbulent

Page 367

wake. The turbulence of his wake causes some of these particles to move vertically and laterally so that they arrive at the critical point. The 90 ft/min downward air flow flushes the burst of particles down past the critical point rather quickly. The entire event usually lasts only a second or two, but long enough to do the damage. The same scenario can occur for a robot arm that emits a burst of particles when it moves in a certain way, for a hot bearing on a conveyor that emits oil vapor whenever it passes a given location, and a power transistor that emits NaCl vapors when it gets overheated during a specific operating cycle.

Reliable identification of particle sources requires continuous monitoring at every critical point. Particles at specific points in Class 1100 clean rooms consist of low levels of single, randomly occurring particles recirculated through the HEPA filters plus events when hundreds of particles are generated by in-room sources such as persons walking by, robot arms flexing, or hot bearings passing by. The events last only 310 sec because the air flow quickly flushes the area clean. But by that time, the defect may already exist. Only by continuous monitoring at every critical point can these sources be identified and eliminated.

The primary purpose of particle counting in IC clean rooms is not to certify the class number of the room, but rather to identify and eliminate defect-causing particle sourcesleading directly to improved yields. Separate measurement of each of the two size ranges of particles can yield valuable information, which may lead to identification of the source. Many particle sources generate particles for very short periods of time and reappear sporadically. Thus, not only is the particle size and source location important, but also the timing of the particle event.

Literally everything the wafer comes in contact with is a potential source of contamination, from the ingot melt right on through wafer fabrication and assembly into the device package. Inhomogeneities in the substrate materialusually crystal dislocationare caused by impurities and aggravated by the thermal stresses produced by high processing temperatures. Mechanical surface treatments such as wafer cutting and polishing can cause disorder in the crystal lattice as well. These problems influence the physical behavior of the device, largely by changing the electrical characteristics of the p-n junctions.

Microscopic dust particles can collect on the photolithographic masks employed in device manufacture. If these particles are on transparent areas, their images transfer to the wafer. Compounding this problem, most of the masks actually used in IC manufacture are copies of a master that may also have been contaminated by such particles. Therefore, the working mask (plate) may already contain defects. In this circumstance, only real-time process monitoring can catch a seriously defective mask before it produces large numbers of faulty devices.

Particles can block etching, metallization, or ion implantation, leading to shorts, open circuits, pinholes, or localized areas of high resistance or conduc-

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tivity. Often such defects result in total circuit failure. For example, particle-generated pinholes in thin-gate oxide films are one of the chief causes of low yields in MOS ICs.

The charge density of smaller particles, as found in today's clean rooms, is much higher than large particles (which are typically filtered out) because the total charge per particle is approximately the same. This leads to a greater attraction of smaller particles to the surface of a wafer and the formation of stronger bonds (Table 9.2). Going from 10-mm to 1-mm particles results in more than a 10-fold increase in relative adhesiveness. Furthermore, as device geometries become smaller, these small particles become a more significant proportion of the feature geometry and also a greater proportion of the overall chip.

The surface density charge is greatest at regions of small radius of curvature. With increasing surface topography and circuit density, a commensurate increase in charge density results at the edges of features. Thus, feature edges have a tremendous attraction for charged particles.

Differences in frictional flow and conductivity lead to different degrees of adhesiveness for particles in different fluids. Fortunately, most particles in chemical solutions will not stick to the surface of a wafer because the electrostatic and other attractive forces are relatively weak and the particle charge can be dissipated through the liquid with relative ease. In addition, the abrasive force of liquids is relatively strong. In air, on the other hand, the attractive force between particles and a wafer is expected to be greater due to the higher static charge on the particles and because the abrasive force of air is significantly weaker than liquids. Thus, particles in air are more likely to be attracted to the surface of a wafer and remain attached.

Other abnormalities appear as surface contamination, caused by impurities in water and other chemicals used during fabrication. Catastrophic deformations in gate oxide layers can result, causing transistor gate and channel shorts. Because of their origin, these pin holes distribute uniformly across the IC surface.

Integrated circuits are particularly sensitive to the ions of certain metals,

Table 9.2 Adhesive Force Versus Particle Size

Particle size (mm)

Relative adhesive force (gravity force)

100.0

510

50.0

2,159

10.0

57,716

1.0

674,600

0.1

749,552,300

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primarily sodium or potassium, introduced into (or on) the wafer during processing. These particulate materials have been found to react with silicon dioxide during oxidation, creating localized regions that are high in ionic contaminants. Once in the wafer (surface metal ions are diffused in during high temperature steps) the ions can migrate to the active junction regions, causing a variety of device performance problems. Such particle-caused defects generally affect device performance, rather than cause failure. Typically, in MOS ICs with ionic contamination, circuit leakage increases and threshold voltage levels are degraded.

Statistics on electrical breakdown have shown that wafers cleaned in low particulate chemicals have significantly improved dielectric breakdown strength when compared to those cleaned in standard electronic-grade chemicals. In addition, these devices take a longer time to reach failure for any given test field.

By way of illustration, some of the major sources of wafer contamination are as follows:

Particle contamination to the wafer can reach 2000 particles per liter when a solenoid on a gas furnace is actuated.

Particle contamination can reach 10,000 particles per liter when a photoresist spinner is actuated.

Condensable organic deposits on the wafer can be traced to wafer carriers. Additionally, metallic pigments and mold release metallics contaminate the wafers; films of 5001200 Å have been measured. (Note that particles are 0.1 mm or greater in size.)

The act of closing a lid on a storage box can create an environment for the wafers that contains up to 2000 particles per liter.

Plastic used in wafer equipment becomes triboelectrically charged and therefore attracts the smaller dust particles with opposing charges. An individual or metal surface either discharges the plastic or causes a field collapse. The particles then deposit on the next charged surface, the wafer.

Sulfur from the atmosphere coalesces on the wafer surface.

These problems are a challenge and an opportunity for the equipment, chemical, wafer, photomask, wafer/mask carrier, and gas suppliers to meet. They must be resolved in order for the product to function. A reduction in particulate levels will result in yield and performance improvements. However, the degree of improvement will depend on the device and process used.

Wafer Ecology

As device suppliers have approached and bypassed the 1-mm barrier, a change in the philosophy of contamination control has become apparent. From a device

Page 370

standpoint, this change in perception has been made necessary by several factors, including submicrometer gates, sub-100-Å gate oxides, the need for reliable dielectric structures, bilevel gates, and multilevel metallization. The result has been higher sensitivities of the product to particulate contamination below 0.3 mm, to molecular levels of contaminants, and to the effects of static electricity. These increased sensitivities, combined with technical limitations such as reduced efficiencies of installed HEPA (high efficiency particulate air) filters below 0.3 mm, different capture mechanisms below 0.3 mm on membrane filters, and inadequate control of electrostatic effects in the fabrication area, have forced suppliers to review their contamination control philosophy and look at the total environment that the wafer experiences during fabrication, from crystal growth through device packaging. This is called wafer ecology.

The historic approach to this problem has been to control the clean-room environment by using high-purity air, chemicals, gases, and so forth. This approach was effective once, but it is insufficient in maintaining today's technology requirements. The fundamental change to wafer ecology means that one must look at the environmental challenges from the environment of the wafer itself rather than that of the clean room. It is a change from looking at the external environment around the wafer to the internal environment of the wafer.

Advances in analytical instrumentation such as laser-based wafer inspection equipment, ESCA (electron spectroscopy for chemical analysis) as a tool for analysis of wafers, and monitors that can detect organic contamination on wafer surfaces have allowed IC suppliers to approach the IC contamination problem from the internal environment of the wafer outward.

The goal of wafer ecology is to clean up all process materials, equipment, and techniques that impact product quality. This requires an empirical approach removing 100 percent of the contaminants by involving all vendors and suppliers who have a hand in producing semiconductors.

Wafer ecology is a crucial problem involving many factors. Contamination can take many forms: particulates, organics, trace metals, even intangible contaminants such as static electricity. The challenge is to track each contaminant to its source and then prevent it from entering the wafer ecology.

Sources of Contamination

There are primarily three fundamental types of contaminants in the IC fabrication process: molecular, ionic, and particulate. The sources of these contaminants vary; operators (production personnel), their clothing, and the general atmosphere surrounding the plant at atomic and molecular levels; metallic substances in the gases and etchants used to manufacture the circuits; and ionic and organic components in process fluids such as photoresists. Some organic contaminants have even been traced to the distribution system within the semiconductor plants,

Page 371

such as organic leachables in DI (deionized) water piping systems. The sources of these contaminants according to their position in the total IC manufacturing process follow:

1. Starting silicon wafer

2. Wafer fabrication

a. Air

b. Production facility

c. People

d. Water/water distribution systems

e. Chemicals

f. Gases

g. Static charge

h. Equipment

i. The fabrication process

3. Assembly process

a. Moisture

b. People

c. Static charge

d. Equipment

Each category represents a unique contamination source that must be controlled. Thus, as a first step to controlling contamination, the cleanliness of each IC processing step must be controlled.

Receiving less attention, but just as critical a contamination problem, is the accumulation of an invisible film on wafer surfaces as a result of airborne or reagent-borne molecular organic and hetero-organic species. Organic contamination is known or suspected to cause a host of silicon-wafer surface problems, including the problems of visible streaks or smears, ultrafine-particle degradation haze, and transformation to a hydrophobic surface state. Many organic compounds contain atoms other than carbon, such as phosphorus, sulfur, halogens, and certain metals. Some of these elements cause undesirable electrical properties in devices if conditions are such that they diffuse into the silicon surface during processing.

Some ways in which films can acquire deleterious contaminants are; if the wafers are stored in the proximity of many types of plastics; water contamination; clean-room exposure; during wafer clean and autoscrub; and if aggregation or condensation into cleanups occurs.

Such aggregation occurs whenever the surface temperature of the wafer falls below the dew point. This phenomenon was observed when a contaminated wafer was placed on a cold chuck for a brief period of time. After the wafer had been allowed to return to room temperature, its surface exhibited a hazy appearance, indicating the presence of the originally invisible (latent) organic

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films. This finding explains why contaminated wafers packed under humid conditions or stored and shipped where extremes of temperature are encountered are susceptible to what is generally known as degradation haze.

Let us now turn to these various categories of contaminants and discuss them in greater depth.

Starting Wafer Material

The characteristic nature of the starting material, be it silicon or gallium arsenide, forms the basis for the quality of the finished product, in addition to the subsequent additive contamination-inducing processing steps. Table 9.3 lists potential defect mechanisms/contaminants that affect the starting silicon material. Control of oxygen concentration is essential to obtaining high quality wafers. Better understanding of the hydrodynamics (motion) of the silicon melt and its influence in oxygen transport is crucial to this control.

Oxygen comes from the quartz crucible of the Czochralski (CZ) furnace, which slowly dissolves into the silicon melt. The faster the crucible dissolves, the more oxygen is introduced into the melt. Oxygen concentration can be controlled by crucible rotation rate, thus controlling the rate of dissolution of the quartz crucible. Typically, this rate must continuously increase as the crystal is grown.

In addition, crucible dissolution is affected by its position in the hot zone. As the melt becomes depleted during a run it results in less contact between the melt and the crucible. Thus, the crucible position in the furnace is gradually changed, along with the changing rotation rate, to maintain a relatively constant oxygen concentration.

Silicon wafer technology has advanced through more accurate control of the physics and chemistry of the CZ crystal growth process and furnace improvements that provide a greater control of bulk silicon characteristics. Until

Table 9.3 Silicon Wafer Defect Mechanism Summary

Structural

Chemical

Mechanical

Wafer imperfections
Bulk oxygen precipitation
Bow/warp

Oxidation induced

Oxygen concentration

Local site

Stacking faults

Oxygen gradient

Flatness

Micro defects

Carbon concentration

External gettering

Bulk metallics

Epitaxy
Native oxide

Surface wetability

Surface metallics

Front surface particles

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recently, for 3- to 2-mm technology, semiconductor suppliers have generally been concerned with mechanical specifications and frontside cleanliness. Electrical silicon specifications have typically been of less concern.

For VLSI circuits, silicon crystal growers are being asked for improved control of silicon ingot and wafer imperfections, contaminants, and dopants, resulting in better uniformity of silicon characteristics such as resistivity, oxygen, and carbon. Uniformity involves a specification, along with characterization of the behavior of the specified bulk silicon characteristic throughout the semiconductor manufacturing process. In addition, uniformities can be macroscopic (i.e., defined radially and axially within a silicon ingot) or microscopic (i.e., referring to a small scale on a wafer).

Control of silicon crystal uniformities, particularly at the macroscopic level, is the focal point of many recent improvements to commercially available CZ furnaces, which are the major source of the silicon used in the semiconductor industry. Most of the recent improvements to CZ furnaces involve computer control of silicon process recipes, which enable precise control of the physical and chemical aspects of the crystal pulling process.

Some of the bulk silicon developments that will be required for VLSI circuits are

Metallic impurities will have to be controlled to less than 0.1 ppb (parts per billion) on the surface of a wafer and to less than 0.001 ppb in the interior.

Defect densities will also have to be dramatically improved through the regions of the silicon where the active circuits are fabricated.

While 50100 defects/cm² silicon wafers may have been adequate for 2- to 3-mm processing, less than 5 defects/cm² will be required for submicrometer technology.

Reduction of grown-in defects and dislocations will be required. Microresistivity variations, which affect MOS circuit threshold voltages, must be minimized.

The initial distribution of oxygen in the silicon crystalboth laterally and longitudinallymust come under greater control in silicon used for submicrometer technology.

The carbon concentration is also of importance in relation to the oxygen concentration and formation of microdefects.

Control of these parameters is not only important on the surface of wafers, but in zones (Fig. 9.5) throughout the bulk silicon, all the way to and including the back surface. Each so-called zone must be addressed specifically and specified individually.

The complex material properties needed in VLSI circuits require the design

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Figure 9.5
The transition to 1-mm technology will require silicon wafers
engineered with zones of specifications [2].

and consistent availability of multizoned material systems. Three wafer fabrication processes will become important in the production of these so-called systems: backside polysilicon deposition, frontside epitaxial deposition, and, as appropriate, predenuded zones.

Expitaxial films (zones), which are particularly important for CMOS technology, must be highly controlled for dopant uniformity, crystal defects, thickness, and mechanical strain. Depositing epitaxial silicon onto the best quality polished surface involves extensive engineering of the epitaxial-to-substrate interface, resulting in the lowest density of defects.

Denuded-zone silicon products appear to be an essential ingredient for high-yielding submicrometer circuit processing.

Paramount to the processing that will develop for VLSI circuits, suppliers of silicon wafers will have to design the most appropriate gettering mechanisms into their wafers. The two types of gettering most likely to become dominant are internal via precipitated oxygen and external via polysilicon deposited on the back surface of the wafer.

Uniform and controlled precipitation of oxygen is essential to the minimization of wafer warpage and the maintenance of the desired wafer flatness. These

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internal defects can also be utilized for internal gettering and delineation of the denuded zone (zones 2 and 3) to improve circuit performance.

Increased crystallographic perfection (and reduction of metallic impurities) near the surface region where the circuit resides is important to reduce excess leakage currents. The reduction of this important IC yield detractor is facilitated by the use of an enhanced gettering technique that removes process-induced metallic contaminants away from the circuit active zone. This is achieved by a thin polysilicon layer deposited on the wafer back surface, creating numerous polysilicon grains that getter process-induced contaminants away from the circuit active zone (zone 1) during IC fabrication.

Polysilicon layer gettering is proving to be more effective than previous methods of damaging the back surfaces with mechanical abrasion or sandblasting, because it is inherently cleaner, provides a close thermal match to single crystal silicon, can be oxidized to seal the back surface, and is believed to last throughout wafer processing.

Wafer cleanliness (haze- and artifact-free hydrophilic front surface), front-surface particle density control, and the absence of particles on the wafer backside become critical as feature size approaches typical particle sizes. Backside particles can affect frontside flatness when a wafer is chucked on a lithography exposure system. Elimination of those back-surface particles that may interfere with effective alignment, and therefore optimal resolution and lithographic pattern fidelity, is also essential.

Because wafers are cleanest immediately after polishing and final cleaning, it may become more common for silicon wafer vendors to supply preoxidized wafers. Such oxidation helps maintain factory cleanliness and also provides a passivating effect. Oxidized hydrophilic surfaces are relatively impervious to contamination and do not electrostatically attract particles.

Gallium arsenide wafers have some unique characteristics of their own. The quality of performance in GaAs ICs is strongly dependent upon the number of dislocations present in the starting material. GaAs, compared to silicion crystal growth, is more sensitive to thermal gradient and temperature changes during the growth process. These changes generate crystal dislocations. Reduction of crystal dislocations is directly related to the reduction of axial and radial temperature gradients at the crystal melt interface.

Most liquid-encapsulated Czochralski (LEC) pullers have used the same hot zones developed for silicon. These have sharp gradients above the crucible; the temperature of the crystal falls several hundred degrees in only a few centimeters. Current LEC furnace design objectives include modifications of the hot-zone geometry and the reduction of convective mixing in the melt. For example, similar to silicon crystal growth technology, research using magnetic field dampening of the melt is also considered possible for GaAs. Until recently, the GaAs available for ICs had typically 200010,000 dislocations per cm².

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Vendors of GaAs wafers have succeeded in reducing this number of dislocations to about 200 dislocations/cm² using high-quality LEC techniques. This opens the door for the fabrication of LSI and VLSI circuits on GaAs substrates.

Additional developments that are required to produce high-quality, high-yield VLSI circuits include

Improved standards of wafer flatness. To produce submicrometer geometries with stepper-based lithography will require local flatness less than 1 mm across the stepped field of view (1020 mm). Flatness must also be maintained across all usable areas of the wafer. It is crucial to recognize that flatness is affected by processing.

Improved front-to-back surface parallelism (taper) to avoid refocusing during lithography exposure. This will aid in achieving maximum throughput with steppers.

New methods for ensuring wafer inspection as well as in-process wafer test. Included would be measurements of lifetimes, and breakdown and flatband voltages, to test selected wafers on a production line so potential wafer performance could be predicted. Specifically, these developmental efforts must be directed toward the ability to test starting silicon wafer characteristics and meaningfully correlating them to ultimate chip yields.

Low-temperature doping processes. As wafers sizes increase, the continued use of high-temperature doping processes result in significant wafer warpage as shown in Fig. 9.6. Continued improvements in various chemical vapor deposition (CVD) and ion-implantation processes as well as realization of molecular beam epitaxy (MBE) and focused-beam processes are required.

Airborne Contaminants*

The inside of a wafer-fabrication facility must be extremely clean and orderly. Because of the small size of the structures being manufactured, even the tinest dust particles cannot be tolerated. A single dust particle can cause a defect that will result in the malfunction of a circuit. Special clothing is worn to protect the manufacturing environment from dust carried by the human operators. The air is continuously filtered and recirculated to keep the dust level at a minimum. Counting all the dust particles that are a micrometer or more in diameter, a typical wafer fabrication plant harbors fewer than 100 particles per cubic foot. For the purpose of comparison, the dust level in a modern hospital is on the order of 10,000 particles per cubic foot.

*Portions of this section used with permission from Ref. 3.

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Figure 9.6
Silicon wafer warpage as a function of
temperature.

The Clean Room

The main purpose of a clean room is to prevent environmental factors from interfering with IC processes. Thus, the major contamination source that must be controlled is the air in the fabrication facility. Plain everday air (even nonsmoggy air) is dirty. The atmosphere contains copious amounts of particulates and water vapor as well as photochemical smog. The small dimensions involved in photomasking are smaller than the diameter of the most common particulates in air. Figure 9.7 shows typical particulate sizes and Fig. 9.8 shows the geometric comparison of a 2-mm diameter particle on a wafer with 1 mm of photoresist. In addition, energy disturbances, such as vibration and electrical noise, must also be controlled. Vibration is especially detrimental to photolithographic processes, and electrical noise spikes may affect computer-controlled equipment. The clean room itself (i.e., the materials used in the construction of the clean room) is a source of contamination. Reference 5 discusses this source of contamination in detail.

The design of a clean room begins with a consideration of the characteristics of the ICs that will be made in it. For example, since bipolar ICs are high-current devices that require relatively complex metallic conductors, provisions must be made for extensive metal deposition equipment. Conversely, since CMOS ICs are typically low current devices and use simpler polysilicon or aluminum alloy conductors, different process equipment is required.

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Figure 9.7
Relative size (mm) of airborne particulates [4].

Similarly, different products display varying degrees of sensitivity to contamination. For CMOS chips, designers must pay particular attention to the possibility of heavy metal contamination because these devices depend on surface-state phenomena that are inhibited by metal contamination. In contrast, the junctions of bipolar devices are below the surface and are therefore less susceptible to surface contamination.

The vulnerability of any VLSI circuit to defects increases with its size. Thus, particle concentrations that would be acceptable for clean rooms devoted to small-scale integrated circuits would be totally unacceptable for the larger VLSI devices. Chip sizes have increased over the years. The larger size chips would not have been feasible without the concomitant gains in defect density control. Many mathematical models exist that predict chip yield based on chip area and defect density.

Another factor that determines the degree of clean room control is minimum feature size. For example, ICs with 0.5-mm design rules have much greater susceptibility to damage from the same size particle than chips with 1.0-mm design rules.

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Figure 9.8
Relative size of airborne particulars to
wafer dimensions [4].

The trends are clearICs are becoming larger and minimum line sizes are becoming smaller. Both trends combine to place extreme demands on clean room processing. Superimposed on these trends is an added factorthe different processes used for bipolar and CMOS devices create varying sensitivities to contamination.

In 1963, Federal Standard 209, Clean Room and Work Station Requirements, Controlled Environment, was established to define degrees of particle control regardless of methods used to obtain that control. Figure 9.9 illustrates how clean-room technology has advanced in controlling particulate contamination using Federal Standard 209 definitions. As shown, particulate control will require a 100-fold improvement when moving from Class 10 to Class 1 levels. Since it is quite difficult to statistically accurately measure 1 particle per cubic foot, some companies are measuring larger volume samples.

Table 9.4 shows the Federal Standard 209E cleanroom definitions. As compared with Fig. 9.9, it should be noted that the particle counts are per cubic meter, not cubic foot. Clean rooms can be classified at these cleanliness levels when the particles are measured in accordance with procedures described in the Standard.

Table 9.5 compares the different contamination classes for different

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Figure 9.9
Clean-room particle size versus population.

Table 9.4 Federal Standard 209E Clean-Room Definitions

Maximum allowable count per cubic meter

Room class
0.1 mm
0.2 mm
0.3 mm
0.5 mm
5.0 mm

M1
350
75.7
30.9

10

-

M1.5
1,240
265
106

35.3

-

M2
3,500
757
309

100

-

M2.5
12,400
2,650
1,060

353

-

M3
35,000
26,500
3,090

1,000

-

M3.5
-
75,700
10,600

3,530

-

M4
-
-
30,900

10,000

-

M4.5
-
-
-

35,300

247

M5
-
-
-

100,000

618

M5.5
-
-
-

353,000

2,470

M6
-
-
-

1,000,000

6,180

M6.5
-
-
-

3,530,000

24,700

M7
-
-
-

10,000,000

61,800

-, Not applicable.

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Table 9.5 Comparison of Clean Room Class with Environment

Environment
Class

Particle size (mm)

VLSI area

10

0.3

VLF hood

100

0.5

Typical fabrication area

10,000

House room

100,000

Outdoors

>100,000

environments. Particulate quantity levels are measured in the air stream in the process stations. LSI clean rooms must filter the air to a 0.5-mm level, while VLSI processing requires levels down to Class 10 at a maximum particle size of 0.3 mm.

However, controlling airborne particles involves more than simply setting limits on particle concentrations. For example, when a person or machine releases particles into the clean-room airstream, what are the dispersion characteristics of the flow path? And how quickly will the clean room recover from this burst of particles? Dispersion and recovery characteristics are specific, measurable functions of clean-room design.

Temperature, relative humidity, and vapor pollutants are airborne influences that must also be controlled by clean room design. Temperature variations affect the ability of precision equipment to maintain dimensional control to the necessary fractional micron tolerances. Air moisture content can adversely affect the adherence of photoresist films to wafer surfaces. Vapor air pollutants can deposit on sensitive wafer surfaces and chemically interfere with VLSI processes. Table 9.6 lists some critical clean room requirements placed on airborne influences affecting VLSI chip manufacture. The evolution of clean-room designs for the semiconductor industry has and still is proceeding along lines to include the human operator in close (in most cases too close) proximity to the product (wafers). The expense to build and maintain a systemany systemthat strives to approach zero units (in this case particles) of ever-smaller size (submicrometer particles) in a large volume of a media (2.53 million ft³/min of air) is following an upward exponential curve. It has also led the industry to more expensive and more extravagant methods to package the people to protect the product.

Clean-room air must be continually cycled through a purification system to prevent suspended particles from settling onto the wafers. The prefilters, which have low to intermediate efficiency, are used to prolong the life of the far more expensive final filters, which are of the HEPA (high-efficiency particulate air) type. HEPA filters can remove as much as 99.99% of all airborne particles larger

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Table 9.6 Controls on Airborne Factors

Particle control

Concentration

Class 100 (operating conditions)

Class 10 (clean room certification)

Dispersion

Not measurable beyond 24 in. from envelope of contaminant generator in zone 18 in. above floor to 36 in. below ceiling

Recovery

1 min from removal of contaminant generator

Temperature control

General clean room

70 ± 1.0°F

Photolithography areas

70 ± 0.5°F

Stepper aligners

Special chambers to achieve 70 ± 0.2°F

Relative humidity control

General clean room

35 ± 5%

Photolithography areas

37 ± 2.5%

Vapor control

Fume scrubbers as required on incoming makeup air

Effective chemical exhaust capture at VLSI process stations

Source: Ref. 3.

than 0.3 mm. Where vapor pollutants would be harmful, absorption-type filters or vapor scrubbers should be provided.

A clean room may be described as either mixed flow (Fig. 9.11), or laminar flow (Fig. 9.11), depending on the techniques used to control its air flow. Both types of design include all of the elements shown in Fig. 9.12. Recirculating fans provide air movement through the room as well as through its prefilters and final filters. Maintaining a constant laminar airflow is not cut-and-dried. Total airflow is never laminar because fixtures and movement within the clean room create eddy currents and other deviations in the flow. An efficient clean-room design will minimize these anomalies, but cannot eliminate them entirely.

Air-handling units handle cooling and heating requirements. Makeup fans provide air to pressurize the clean room and to replace air lost through process exhausts and leakage out of the room.

If a mixed-flow clean room is supplemented with high flow rates of HEPA-filtered air (about 100 fpm), it can be made to provide Class 100 conditions. However, its dispersion and recovery characteristics are inadequate for VLSI processes. On the other hand, a vertical laminar flow (VLF) clean room can maintain at least a Class 100 level throughout its work zone and at least Class 10 level under acceptance testing conditions. The term laminar describes the single-pass flow of air from the filtered inlet point past the work point to the exit point. This piston of air drives airborne particles out of the room, since there are essentially no eddy currents to recirculate particles back to the work point.

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Figure 9.10
A mixed-flow clean room where turbulent zones can be created by
nonuniform air distribution and by obstacles in the way of the airflow path. The
resulting eddy currents will recirculate contaminant particles [3].

The classic VLF clean room design (Fig. 9.13) has a perforated floor as the exit point for the piston of air. This can create problems in plants not having structural height clearances high enough to accommodate penthouse space for air handling and make up air equipment. The room is constructed with HEPA filters in the ceiling and grated floors to allow the downward flow of clean air. The flowing air carries any particulates from personnel or equipment down below the working surfaces. Table tops in this ultraclean room are perforated to allow air flow. The room must be operated with meticulous procedures to eliminate outside contamination from entering.

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Figure 9.11
A laminar-flow clean room where uniform, high-flow air delivery from the ceiling
and perforated floor minimizes airflow disturbances and accomplishes quick
removal of particles in the airflow path [3].

A number of plant services are needed for clean-room operations. High-purity process gases and liquids must be transferred to the processing area in high-quality, noncorrosive piping. Filters are added at the point of use to remove particulate contaminants. Chemical wastes require proper collection and treatment. Since some of the processing gases and liquids are toxic or corrosive or flammable, appropriate safety precautions should be followed. In addition to toxic gas monitors, which sound an alarm if a gas leak occurs, clean-room design and personnel training should take into account emergency safety procedures.

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Figure 9.12
Both types of clean rooms provide recirculating fans to move
air through the work area as well as through prefilters and final
filters [3].

Random energy sources, such as vibration, noise, electrical power spikes, and radiofrequency transmissions, can disrupt VLSI processes. Such energy sources may be within the factory (exhaust fans, air-conditioning equipment) or outside the factory (highway traffic vibration, electrical power failures). Some clean-room equipment can also create random energy disturbances that must be controlled. Examples of such equipment are plasma-etch vacuum pumps and clean-room recirculating fans.

Many straightforward engineering methods exist for controlling noise and electrical energy disturbances. Electrical noise spikes may be controlled by the use of line filters and power conditioning units attached to the power line input to the sensitive equipment. Vibration control, on the other hand, has become a difficult and costly problem. Photolithographic alignment equipment and line measurement equipment are especially vulnerable to disturbances from vibration. Much work has gone into vibration control, and designs exist for everything from small air-supported tables and special platforms for stepper aligners to the complete restructuring of the clean-room floor to isolate it from the rest of the factory.

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Figure 9.13
Viewed in cross section, considerable space is needed above the clean-room
work area to hold air handlers, and even more space is needed below for various
services and vibration control.

The Clean Station*

To reduce the contamination level of large clean rooms, the semiconductor industry developed the clean station concept, since it is easier to maintain the required cleanliness levels in a smaller volume individual station as compared to an entire room. The wafers are only exposed (and processed) in the process

*This section used with permission from Ref. 4.

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stations, called vertical laminar flow (VLF) stations, which are miniature versions of clean rooms. A cross section of a typical VLF hood is shown in Fig. 9.14.

Room air is pulled into the hood top through a prefilter by a blower unit. The air passes through a special filter and on down to the work surface. The arrows in Fig. 9.14 indicate the laminar nature of the air flow. A VLF hood is effective for two reasons. Wafers in the hood are exposed only to clean air, and any contamination from the room or personnel is prevented from entering the hood by the slight positive pressure of the air flow. The final filter used in VLF hoods is the HEPA filter. Constructed of fragile fibers, the filter has an accordian-folded design, allowing a large filtering area at an air velocity low enough for operator comfort.

A particular problem arises in maintaining wafer cleanliness during the many chemical or wet operations. The fumes from the various chemicals have to be exhausted from the room for safety reasons. The classic fume exhaust hood used in chemical labs solves the safety problem, but the dirtier room air is drawn across the wafers.

This problem is solved by setting a VLF unit on top of a fume hood as shown in Fig. 9.15. With this addition, both safety and cleanliness can be achieved. The hoods have to be designed so that the acid fumes are exhausted out the back, with clean laminar-flow air covering the front portion of the work surfaces.

The operators, technicians, supervisors, and engineers necessary to run a fabrication area are themselves a major source of particulates, and their movement about the area stirs up particulates that may end up in a process hood or on the

Figure 9.14
Cross section of a VLF hood [4].

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Figure 9.15
Cross section of a VLF fume exhaust hood [4].

wafers. The tunnel approach to clean-room design is used to control particulate contamination from this source.

The purpose of the tunnel concept is to isolate a portion of the fabrication line in its own tunnel. Only the personnel required to operate that portion of the line are near the wafers, and the tunnel walls protect the wafers from dirt stirred up in another portion of the fab area.

The tunnel is fitted with ceiling HEPA filters and VLF work stations to insure a clean environment.

Clean-Room Procedures*

The successful operation of a clean room requires control of every possible source of contamination. Each source represents a different danger and requires special procedures to control the contamination.

Construction of a clean room is a trade-off of cleanliness versus cost. However, every facility is built upon basic principles. All floor, wall, and ceiling materials are nonshedding and smooth surfaced. Where accoustical-type ceiling panels are used they are covered with a nonporous material such as mylar. Piping

*This section used with permission from Ref. 4.

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holes through walls and ceilings must be calked and sealed. Vacuum and mechanical pumps should be located outside the area, as should all portions of equipment requiring periodic maintenance and replacement of consumables. Flat surfaces not under laminar flow should be minimized to prevent the collection of dust.

Light fixtures should have solid covers to prevent dust buildup on the bulbs. The area should be supplied with nonshedding towels, and cleaning solutions should be as metal ion free as possible.

VLF hoods should not contain large bulky equipment that interrupts the laminar air flow. Pencils are also banned from use in fabrication areas. All production forms should be printed on nonshedding paper, or polymer paper substitutes.

Even in a filtered airflow, wafers should not be allowed to stand idle for too long. For example, photoresist should be applied within 2 hr of growing the oxide layer to prevent wafers from picking up moisture and particulate contaminants. When changes in product flow cause suppliers to miss this 2-hr window, wafers should be kept on hold under laminar-flow hoods and then heat-dried before the photoresist is applied.

Isolation of the fabrication area from contamination brought in from the outside is accomplished by several techniques (see Fig. 9.16):

1. Air-pressure balancing

2. Double-door entrances

3. Air showers

4. Tacky floor mats

An air filter has a lifetime proportional to the amount of work it has to do. A dirty room will shorten the filter lifetime and increase the chance for accidental contamination of the wafer or the VLF hood interior. The production room air

Figure 9.16
Top view of fabrication area [4].

Page 390

can be reduced to a Class 10,000 condition or better by proper balancing and maintenance of the room pressure.

At Class 10,000 level or below, the VLF stations perform more efficiently and longer than they do in a dirty room. By raising the room pressure above that of the rest of the factory, any dirt in the air is prevented from entering the area. A further refinement is to utilize a double-door entrance area, with tacky mats to collect dirt from shoe bottoms. By balancing the pressures such that P₁ >P₂P>₃ the production area is protected from the factory. With no outside dirt entering the area, the VLF hood filters only recirculate clean room air.

An additional refinement is an air shower at the fabrication entrance to dislodge loose particulars carried in by personnel entering the area.

Since most of the photomasking operations are temperature sensitive, it is imperative that the temperature be controlled to 70 ± 1°F for process control as well as personnel comfort. Humidity is also a parameter that requires control. High humidity causes adhesion problems of the photoresist to the wafer surface. Low humidity can lead to the generation of static charge. A typical specified humidity range is 1550%.

Projection aligners are particularly sensitive to temperature and humidity variations. Special stations with temperature control to ±0.2°F are required to house the aligners.

Then there is the problem of smog. Unfortunately, few semiconductor suppliers are located in smog-free areas. It has been established that smog causes unwanted and unpredictable results in photoresist development. The problem is minimized by using charcoal filters in the house air-conditioning system.

Wafer Storage and Transportation

During processing, the wafers are transferred between clean stations and stored in sealed containers to protect them from contamination. Various designs and materials are available. Generally, plastic boxes intended for home use should be avoided as they often give off contaminating vapors. Flip-load polypropylene boxes also must be used with care. The hard plastic material can chip wafers as they are flipped into the boxes. The resultant silicon dust can further contaminate the wafers. (Automatic flip machines reduce this problem.) Wafer boxes should be inspected and cleaned regularly. A good practice is to blow out each box with filtered nitrogen immediately prior to loading the wafers. Data taken from wafers stored in various plastic materials (polyethylene, polyvinyl chloride, teflon and others) showed that polyethylene is the lease objectionable package from a contamination standpoint.*

Contamination is further reduced by the use of antistatic materials for box

*See Ref. 6 for more information.

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and carrier construction and using air ionizers to prevent electrostatic particulate adhesion to the wafers.

Wafer Isolation

Reducing defect densities while keeping fabrication costs under control is going to be the greatest IC manufacturing challenge of the 1990s. One method that is displaying the most promise is the so-called micro- or minienvironments (Fig. 9.17). SMIF (standard mechanical interface) techniques, the most popular microenvironments, were first developed at Hewlett-Packard in 1984. The purpose of SMIF is to reduce the size of the required wafer fabrication clean area (and thus defect density) from a full clean room to a clean microenvironment (run box of SMIF pod), dramatically reducing capital equipment costs. For example, by incorporating complete isolation technology in a SMIF system to provide a Class 1 environment for its wafers, LSI Logic Inc. increased die yield by 10% (reduced defect densities) without the costs associated in building an expensive new fabrication facility [7]. Figure 9.18 provides a listing of commonly used wafer isolation terminology.

Water

In the course of the fabrication operation, a wafer spends several hours being rinsed in water. Water is by far the most abundant substance to come in contact with the waferfrom 100 to 1000 gallons per wafer. Therefore, on the basis of volume, water poses the greatest threat to wafer ecology. This is the highest

Figure 9.17
Conventional versus minienvironment fabrication facilities.

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Figure 9.18
Commonly used wafer isolation terminology.

level of exposure to any one environment, other than the room air. And like air, water can contain high levels of contaminants. The unavoidable presence of water in IC manufacturing and processing provides an environment conducive to corrosion. Sources of water in hermetic parts are the component materials (ceramic, metal); the sealing materials (glass); the coatings, die attach adhesives, or encapsulants; the gas present in the equipment where the parts are actually sealed; and the package leak rate. Plastic molding compounds are more susceptible to corrosion that hermetically sealed packages due to the poor moisture resistance from the outside. Corrosion cannot take place without the presence of ions.

The three main sources of ionic contamination for IC devices are die-handling operations (specifically postfabrication and resealing), when the IC is highly vulnerable to uncontrolled environment from mechanical and human handling; wafer fabrication, where inadequate cleaning and rinsing of the wafers can leave contaminants; and package hermeticity failure, which allows the ingress of ions as well as moisture from the outside environment. Other sources can be an improper amount or bound form of phosphorus in the passivation glass or improper plasma processing that leaves fluorine embedded in the Al metallization.

The efficiency of the IC manufacturing process is closely tied to the quality of purified water. Ultrapure water is essential. It is important that contaminants

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that may affect water qualityand, ultimately, product quality and systems operationsbe identified and isolated from the water system. The primary contaminants that affect water quality are

1. Dissolved minerals or ionic species

2. Particulates

3. Bacteria

Each contaminant is removed from the water with a special technique.

The water in a city system contains significant amounts of dissolved mineral salts, existing in the water as ions (NaCl becomes Na⁺ and Cl⁻), which can be electrically active in ICs. The ions are removed by two techniques: first, through a reverse osmosis process; second, through deionization by ion exchange. In-line measurements are made of the water purity before the water is released into the fabrication area.

In many purified water systems, resistivity is used as the major quality criterion. Demineralization (deionization) of water changes it from a conductive medium to a resistive one. In fact, pure water exhibits a resistivity in excess of 18,000,000 W-cm at room temperature. This fact allows us to measure the degree of deionization by a resistivity measurement of the water.

Semiconductor facilities strive to produce 18 MW-cm water, but often allow a lower limit of 15 MW-cm. Table 9.7 shows the relationship between water resistivity and dissolved solids. However, because resistivity measures only the ionized particulate content of the water, high-resistivity water may contain unacceptable levels of bacteria, particulates, and organics.

Water Purification Systems

Most fabrication facilities use a recirculating system, where water that tests above a certain resistivity is reclaimed. The majority of water used in the fabrication process is recycled for two reasons: (1) It is normally cheaper to reclean (reclaim)

Table 9.7 Resistivity of Water Versus Concentration of Dissolved Solids [4]

Resistivity W-cm at 25°C

Dissolved solids (ppm)

18,000,000

0.0277

15,000,000

0.0333

10,000,000

0.0500

1,000,000

0.500

100,000

5.00

10,000

50.00

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used water than to clean up a new supply of water, and (2) to meet the industrical effluent guidelines of the city and state in which the fab facility is located. Excessively dirty water is directed to the drain. For ecological considerations, all waste water is treated to a neutral condition (pH = 7) before discharge. However, the likelihood of residual deionized (DI) water contamination is increased by the use of reclaim water. For example, contamination in DI water has been implicated as a probable cause of excessive leakage current in MOS ICs, reducing product yield.

Although water purification systems are capable of producing ultrapure water with a resistivity of 18 MW-cm, product water may collect impurities as it sits in storage. Point-of-use filtration can help ensure that product water is free of suspended solids when it arrives in the fabrication area. Solid particles are removed from the water, down to the submicrometer range, by various methods. Techniques include sand filtration, diatomaceous earth filtration, and membranes with 0.1-mm pores.

A water purification system is very complex in nature. A typical DI water system [8] for two wafer fabrication areas, as shown in Figs. 9.19 through 9.22, contains four major sections: pretreatment, makeup, polishing, and reclamation. At the pretreatment side, the system is designed to accommodate some degree of variation in the collodial content of the feedwater, since the source of feedwater is a combination of surface and well water (Fig. 9.19). The feedwater is prefiltered by means of positively charged depth filters with a 0.8-mm nominal rating. It should be mentioned that uncharged depth-type prefilters were found to be inadequate for submicrometer particle removal. The use of surface

Figure 9.19
Pretreatment system process flow schematic
(D = depth filter) [8].

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charge-modified filters before reverse osmosis (RO) helps prevent colloidal fouling of RO membranes. Conversion from conventional polypropylene depth filters to charge-modified depth filters eliminated the randomness of RO membrane cleaning and extended the time between cleanings to over 1 year.

The next section of the water system consists of the makeup water supply (Fig. 9.20). RO product water is deionized by a series of two mixed-bed ion-exchange columns, after which filtration is accomplished by means of conventional depth filters. Cost considerations, coupled with the fact that this stage of filtration is intended primarily for the removal of resin particles that are normally larger than 1 mm, led to the selection of a more open, commodity-grade depth filter. Previous testing had shown that 0.2-mm membrane-type filters were unnecessary at this stage of filtration as long as the resin columns were well operated and adequately maintained.

Makeup water is further treated at the polishing stage. Two recirculating supply loops produce high-purity (18 MW-cm) water with two mixed-bed ion-exchange columns in series as well as ultraviolet sterilization for two separate fabrication areas (Fig. 9.21). The polishing system and the supply loop to the fabrication areas were separated to prevent contamination in one fabrication area

Figure 9.20
Makeup system process flow schematic (D = depth
filter) [8].

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Figure 9.21
Polishing system process flow schematic (D =
depth filter, M = microporous membrane filter, and
UF = ultrafiltration) [8].

from reaching the other area. The principal difference between the two areas is that the East Fab includes an ultrafiltration (UF) system, whereas the North Fab does not. Charge-modified membrane filters were used (Fig. 9.21) because they have been found to remove colloidal contaminants at a higher efficiency than did the similarly rated cartridges (ultrafiltration).

Figure 9.22 shows a schematic for a DI water reclamation system. In this example, two such dedicated systems are used, one for each fabrication area. It has been found, however, that even in well-designed, continuous-flow distribution systems, bacteria can and will grow and collect.

Bacterial growth can be controlled by regular sterilization procedures. Sterilization with hydrogen peroxide on a weekly basis will successfully keep bacteria growth to very low levels, but even this process will allow some bacteria to reach photomasks and be deposited.

Following sterilization, it has been found that the carcasses of dead bacteria can coalesce and migrate to the rinses, where they too can be deposited on the photoplates. The most satisfactory protection from this problem is point-of-use bacterial filters. This method has significantly reduced the level of bacterial particulates deposited onto masks in process and rinsing.

Bacteria*

Bacteria and fungi find water a favorable host, and if allowed to exist they act as a contaminant on a wafer. As contaminants, bacteria are the most important

*This section used with permission from Ref. 9.

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Figure 9.22
Deionized water reclamation system process flow schematic
(M = microporous membrane filter, D = depth filter, and asterisks
indicate proposed upgrades) [8].

indicator of purified water quality. Bacteria are a form of self-replicating particulate as well as a source of organic contamination. Particulate and organic fouling creates serious problems for ICs. In addition, bacterial fouling can significantly decrease the life of reverse osmosis (RO) membranes, ion-exchange resins, and microporous filtration systems.

By nature, industrial water systems designed to remove dissolved and particulate matter create a nutrient-depleted environment for bacteria. Like other living creatures, these organisms require certain conditions for growth and replication to occur. Thus, limiting one or more of these conditions will limit bacterial survival to some extent. However, bacteria that have been isolated from environments very similar to those found in purified water systems are known to adapt to nutrient-limited conditions. Since bacteria in large-volume purified water systems have a limited capacity for modifying their environments to suit their own complex requirements for survival, they respond to their situations by altering their metabolic activities. These unusual organisms have evolved complex enzyme systems that enable them to utilize picomolar (10⁻¹² mol/L) concentrations of nutrients without expending undue amounts of energy. Bacteria and other organisms capable of growth in nutrient-limited environments are sometimes called oligotrophs.

The main purpose of such adaptations to extreme environments is to provide the bacteria with the means to grow as fast as possible at low concentrations of essential nutrients. The bacteria most commonly isolated from purified water

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systems are capable of utilizing complex organic substances for growth and replication. The major growth-limiting nutrients are listed in Table 9.8. Organic carbon is the single most important determinant of biofouling potential. To a point, the greater the total organic carbon (TOC) concentration, the more cell mass is developed. A major component of bacterial cell mass is extracellular polymeric material, often referred to as slime. It is this material that is most often responsible for the bulk of biologically mediated fouling of RO membranes, deionizing resins, and micrometer to submicrometer pore size filters.

In many instances, there is a direct correlation between TOC levels and viable bacterial counts. The relationship between TOC and the number of

Table 9.8 Nutrient-Limiting Substrates for Bacterial Growth [9]

Substrate

Examples

Organic carbon
Hymic and fulvic acids (source waters)
Pipe plasticizers
RO pretreatment polymers
Fiberglass-reinforced plastics (FRPs)
Membrane surfactants
Pump and gage lubricants
Microbial byproducts
Personnel
Airborne dust

Nitrogen
Humic and fulvic acids (source waters)
Nitrates and nitrites (source waters)
Microbial byproducts
Airborne dust

Phosphorus
Phosphates (source waters)
Microbial byproducts
Airborne dust

Sulfur
Sulfates (source waters)
Sulfuric acid (RO pretreatment)
Membrane surfactants
Airborne dust

Trace metals and salts
Source waters
Process piping
FRPs
Stainless steel system components
RO pretreatment chemicals
Personnel
Airborne dust

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bacteria is dependent on the concentration as well as on the organic species present in the water. Therefore, water containing low levels of a particularly labile organic species might result in greater cell numbers and biomass than would water with a high concentration of a poorly metabolized organic species. The bacterial population present in the purified water system is also an important determinant of the degree to which various organic species will be utilized as nutrients.

The bacterial cell is composed of various carbohydrates, proteins, lipids, and inorganic salts. Bacteria can contribute to both the organic content and the ionizable dissolved solids content of purified water. However, the relative contribution of biological foulants to ionic and organic contamination is not known.

One determinant of cell growth is the environmental ratio of carbon to nitrogen (C:N). A high C:N ratio favors increased biomass production in lieu of cell division, and vice versa. Therefore, while the C:N ratio may be a limiting factor in microbial replication, it is also an important determinant of cellular biomass. Limiting metabolically available nitrogen in a purified water system that contains a high concentration of unstable organics would thus yield lower plate counts at the expense of increased biomass in the form of slime.

In industrial water systems, the number of bacteria associated with the overlying water represents only a small fraction of the total number present in the system. The largest fraction of bacteria, in terms of both cellular mass and numbers, is attached to surfaces. Furthermore, the vast majority of free-floating bacteria originate from attached populations that have sloughed off from the intact biofilm. The ratio of attached bacteria per square centimeter to free-floating bacteria per cubic centimeter in these systems is often 10,000 or greater.

The two major factors influencing bacterial attachment in purified water systems are surface area and nutrient concentrations. Industrial water systems, unlike most natural environments, offer a tremendous surface area for attachment (in fact, surface area is one of the limiting factors for microbial proliferation in natural aquatic systems). RO membranes, degasifier packing material, DI resins, storage tanks, pleated cartridge filters, piping systems, and point-of-use delivery systems all provide surfaces suitable for bacterial attachment and growth. Among the major reservoirs of bacterial contamination in purified water systems are the DI resins. Fouling of these resins is primarily a function of their large surface area, which not only facilitates entrapment of essential nutrients but also provides ample attachment sites for the bacteria.

Nutrient-limiting environmentsparticularly those limited in organic carbonpromote the attachment of bacteria to surfaces. It is important to note that the first substances associated with clean surfaces are not bacteria but trace organics, which concentrate at the solid-water interface. Consequently, bacteria

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find their carbon sources concentrated on surfaces, providing the so-called primary fouling layer. Once this layer has been established, bacteria and other particulate matter as well as trace metals and other ionic species are concentrated at the solid-water interface. Deposition of the organic layer begins almost immediately after the clean pipe surface comes into contact with the overlying water. In stainless steel piping systems, this type of fouling layering has been associated with corrosion activities. Development of a mature biofilm may take several hours to several weeks, depending on the system. One mechanism for bacterial attachment and subsequent biofouling of purified water systems is shown in Fig. 9.23.

Although surface characteristics do influence biofilm structure, bacterial attachment is not significantly influenced by construction materials. Smoother surfaces delay the initial buildup of attached bacteria but do not appear to reduce the total number attached. A similar observation has been made for the influence of flow rates on bacterial attachment. At higher flow rates, a denser, somewhat more tenacious biofilm is formed. As a result, these surfaces often appear to be free from foulants, since they are not slimy to the touch. In closed-loop polishing systems, such as purified water systems, higher flow rates do result in more frequent filtration and ultraviolet (or ozone) contact, reducing the number of free-floating bacteria and the concentration of nutrients that can contact surfaces. However, higher flow rates will not prevent the attachment of bacteria to pipe surfaces. Bacteria are removed from the water by filtration, after being killed by ultraviolet light sterilizers.

Figure 9.23
Biofilm development on pipe surfaces [9].

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Sources of Microbial Contamination*

An understanding of potential contaminant sources is essential to the identification and isolation of microbial contaminants. Reservoirs of contamination may be found in any area of the purified water system in which the nutrient and microenvironmental conditions promote bacterial replication. Growth-promoting substances and microorganisms may enter the purified water system by the following means:

Source waters

Personnel

DI resin beds

Treatment chemicals

Point-of-use dispensing systems

Degasifier HEPA filter

RO/DI storage tank vent filter

RO/DI storage tank sight tube

Filter housings

Piping/distribution systems

The aggressive nature of high-purity water also creates problems in that the water acts as a solvent for most materials of construction.

The major source of biological fouling of RO membranes is the feedwater supply. Bacteria present in source waters adhere to the membrane and form an intricate biofilm that is constantly nourished by compounds present in the feedwater. Appropriate and effective pretreatment of RO feedwater is the most effective means of controlling RO membrane fouling. Pretreatment strategies include reducing the concentration of such growth-promoting substances as organics and treating the water with oxidizing or nonoxidizing biocides. Biologically mediated fouling often results in a flux decline of the membranes and a decrease in product water quality. Cellulose-degrading bacteria have been associated with lesions in the membrane and may play a role in reducing operating efficiencies and decreasing the useful life of the membrane.

Regardless of whether RO-treated or DI water is stored, biological fouling can present problems in both large- and small-volume storage tanks. Bacteria, fungi, and algae have all been isolated from purified water storage tanks. The chemical content of the tank feedwater is a major factor in determining the types and numbers of isolated microorganisms. Other factors include water usage, turnover time, water temperature, tank design, and materials of construction.

DI beds and forced-draft degasifier systems are major sources of organic contamination in purified water storage tanks. Organics not rejected by the RO

*This section used with permission from Ref.9.

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system bind reversibly to ion-exchange resins, thus serving as a nutrient source for bacteria. These bacteria and their metabolites then act as a further source of organic contamination in the storage tanks. DI resins can also serve as a source of organic nitrogen. Any degradation of the resins (e.g., as a result of cholorine contact) may result in the release of organic nitrogen.

The degasifier is often located downstream of the RO system. When the degasifier well has become contaminated (e.g., because of a faulty intake HEPA filter), airborne contaminants can enter the storage tank. This problem is exacerbated when DI water is stored, since contaminants originating from the degasifier can foul the DI resins. The fouled resins can serve as a growth substrate for bacteria, further contaminating the tank.

Construction materials are another important source of growth-promoting substrates. Faulty entry hatch gaskets admit dust and light. If the gasket material is severely degraded, it can also act as an organic carbon substrate. Many tanks are constructed of fiberglass-reinforced plastics (FRPs). The FRP selected should be low in extractable substances in order to limit the growth-promoting substances.

Storage tanks are often equipped with vent filters, which allow the tanks to displace volume as water is drawn off. The vent filter should be hydrophobic in nature and have a maximum pore size of 0.45 mm. Hydrophilic-type vent filters (cellulosics) wet easily, providing a standing column of water in which bacterial growth is promoted. Additionally, a wet vent filter effectively disallows water displacement. If a large demand is placed on the tank over a relatively short period of time, the potential exists for implosion of the tank. The filter should be oriented in a vertical position so that residual water entrapment is kept to a minimum. Vent filters should be replaced as part of the routine preventive maintenance program.

Another common tank component is a sight tube, which runs the entire height of the tank and is used to measure the volume of water in the storage tank. Although it is convenient to use, the sight tube is a standing column of water that is not open to frequent circulation. It can therefore serve as a reservoir of bacteria or algae for the storage tank. Electronic level indicators provide a relatively contaminant-free means of determining water levels.

The IC industry adopted PVC piping using traditional threaded and cemented plumbing methods early in its evolution in an effort to maintain the ionic purity of the water used, unaware of the biological pitfalls to come.

A growing awareness in recent years of the devastating effect of biological contaminants on the yields of state-of-the-art ICs and the effect of aggressive deionized water on PVC has led to the wide use of fluoropolymer piping systems (PVDF, ECTFE, and PFA) as replacement materials. PVC pipe was also found to support the proliferation of bacteria colonies due to the roughness of its inside surface (fine scratches, seams in fittings, which were invisible to the unaided eye) and the probability of providing the bacteria nutrients.

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Fluoropolymers have emerged as the materials of choice since, unlike PVC and other non-fluoropolymer materials, they are pure (contain no fillers), provide excellent surface qualities, and have a much wider operational temperature range. Fluoropolymers are also more hydrophobic (will not wet) than nonfluoropolymers. It is this quality that makes fluoropolymers resistant to aggressive fluids such as deionized water acids.

Fluoropolymer piping materials exhibit excellent glasslike inside surface characteristics (similar to the electropolished 180 grit finish), which reduce the sites where bacteria can form colonies because microscopic cracks and fissures which can trap residues and promote bacteria growth are nonexistent. Instead of threaded connections or the use of glues, fluoropolymer systems are welded. However, upon welding this material using standard socket or butt fusion methods, plastic is left on the inside surface of the pipe, creating obstructions and sites for bacteria and particulate accumulations.

Production of LSI, VLSI, and ULSI devices is predicated upon a contamination-free ecology for wafer-processing. Essential to the achievement of such a high purity ecosystem is that its critical fluids contact only unchanging, nonreactive materials of construction in storage, in transport, and in processing. This criterion is particularly important with respect to the most voluminous liquid reagent used, 18 MW-cm deionized water.

The effects of prolonged exposure [10], 22 weeks at 100°C, of commercial piping of polymers containing fluorineperfluoralkoxy fluorocarbon resin (PFA) and the fluoropolymers polyvinylidene fluoride (PVDF) and ethylene-chlorotrifluorethylene (ECTFE)to 18 MW-cm water indicated that only piping of PFA fluorocarbon resin was unaffected. Piping of PVDF and ECTFE were visibly and chemically affected. Electron spectroscopy for chemical analysis (ESCA) data indicated that the attack of 18 MW-cm water on piping of PVDF and ECTFE was progressive. Scanning electron microscopy (SEM) examination indicated that physical changes in the exposed pipe surface also occurred during the exposure.

Often, water leaving the system is relatively low in bacterial numbers; however, at point-of-use locations bacterial counts are found to be unacceptably high. Dead legs in purified water distribution systems account for most of the point-of-use bacterial contamination problems observed. Although there are many definitions of what constitutes a dead leg, insofar as bacterial contamination is concerned any length of piping that contains water and is not open to frequent recirculation may be considered a dead leg. On standing, purified water rapidly declines in quality, both chemically and microbiologically. Organic and ionic compounds are extracted from process piping and from other distribution and storage components. In dead leg areas, a concentration gradient occurs that provides bacteria with growth promoting substances.

System dead legs must be eliminated, since any areas where the fluid

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velocity is reduced to below 5 ft/sec will support bacteria colony formation. Current plumbing practice allows as much as 69 pipe diameters of dead leg, which does not allow for complete flushing and will create an area of stagnation. Distribution lines should be plumbed as close as possible to the point of use. Ideally, all goosenecks and spray rinsers should be designed with recirculating loops, allowing a minimal volume of residual water to remain in the line.

In sanitary design, minimum bend radii should be strictly followed so as not to inhibit the fluid flow within the system. One hard 90° elbow in a system can have the same pressure loss as adding an additional 10 ft of pipe.

Most deionized water distribution systems in use today are controlled by pressure only. A backpressure regulator is employed to control the total system pressure without regard to the fluid flow/velocity within the system. Systems that are only controlled by pressure have been found to develop very large areas of stagnation (dead legs) during hours of peak usage. This can be avoided by employing both flow and pressure regulation, with the availability of extra pumping capacity where required.

Flow rates in distribution systems also have an effect on bacterial numbers in the overlying water. The optimal flow rate is dependent upon other design considerations (e.g., type of pipe used, number of outlets, system demand, and storage capacity). Distribution systems constructed with parallel outlets and varying pipe diameters are sometimes associated with high bacterial numbers. In these types of systems, flow rates are often very high in some areas and either very low or nonexistent in others. Dead legs and low flow rates also reduce the effectiveness of system biocide treatments.

Any part of the water system that comes into contact with personnel should be considered a potential reservoir for contamination. For this reason, attention should be given to the three most common types of dispensing systems in semiconductor manufacturing facilitiescascade sinks, dump-rinser sinks, and hand sprayers. In most fabrication areas, sinks and hand sprayers are enclosed in a Class 100 laminar flow hood. However, macro- and microparticulate contamination of these wells is frequently observed as a result of human contact. Contaminants such as skin oils, hairs, and respiratory droplets can serve as a direct source of bacteria as well as a source of growth-promoting factors. The low flow and turnover rates associated with some of these dispensing systems can also create a dead leg, providing a reservoir for contamination. Also, personnel should be advised of the importance of contamination control with regard to these types of dispensing systems.

In addition to the problem of personnel contact, hand sprayers can act as a dead leg in the system by virtue of their design. Ideally, hand sprayers should be designed to allow circulation of the standing water present in the flexible hose.

Routine monitoring and analysis can dramatically reduce the impact of

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biological fouling on purified water systems. In most cases, the selection of multiple sample sites coupled with high sample frequencies will result in the detection of problems before serious system or product failures can occur. Sampling locations should be selected on the basis of their potential for acting as a source of microorganisms or growth-promoting factors. The following locations should be considered for routine monitoring:

RO feed

RO product

Primary DI effluent

RO/DI storage tank

Polishing DI effluent

Ultraviolet influent

Ultraviolet effluent

Final filter effluent

Critical point-of-use locations

Return line(s)

Accurate monitoring of bacteria levels in a purified water system is the key for scheduling preventive maintenance functions for the entire water purification system. As such, preventive maintenance and treatment are important considerations in the control of bacterial fouling.

Chemicals

Throughout the fabrication process, wafers are cleaned with various acids and solvents. Like water, these chemicals contain other elements that function as contaminants to ICs and thus impact wafer ecology. Solvents such as xylene and methyl alcohol must be applied and dried evenly or they will leave unique stain patterns on the wafer surfaces. These stains can cause poor photoresist adhesion and increased undercutting during etching. Some liquid materials, such as photoresist, are sensitive to temperature and humidity changes and require carefully controlled environments during manufacturing, shipping, and storage.

Chemical contamination can alter the resistivity and conductivity of silicon. For doping, extremely pure materials are necessary, as the presence of any significant amount of impurities can have adverse effects upon the electrical characteristics of the semiconductor devices being fabricated. In particular, mobile ions such as sodium must be reduced to extremely low levelsto the order of only parts per billion.

Unlike water, chemicals are used as purchased, and cleanliness levels must be specified to the vendor. The majority of commodity acids and solvents available do not meet the cleanliness level requirements of semiconductor manufacturing. These chemicals are titled commercial grade. However, the IC industry has created a demand for chemicals of heretofore unheard of levels of

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purity. The cleaner grades of chemicals generally availableelectronic grade, semiconductor grade, reagent grade, USP (United States Pharmacopoeia), and CP (chemically pure)are crude by today's IC chemical requirements. For example, in Class 100 air, stated relative to liquids, there are no more than 3.5 particles/L that are greater than 0.5 mm and no more than 0.875 particles/L greater than 1 mm. By comparison, the level of particles in liquid chemicals is quite large. Semiconductor-grade chemicals contain between 100 and 100,000 particles/ml that are greater than 1 mm. The actual particle counts vary among vendors, measurement techniques, different chemicals, and batches of the same chemical.

Semiconductor-grade chemicals are used in over 95% of all wafer-processing applications. For example, standard semiconductor-grade buffered oxide etch, obtained from two different vendors, averaged over 400 particles/ml. This is almost 500,000 times dirtier than Class 100 air. Thus, for each minute a wafer is in contact with this chemical, it is exposed to as many particles as it would be if it sat in Class 100 air for close to 1 year. With moderate agitation of a wafer in this liquid, the flow rate could easily exceed that of air, further exacerbating the potential contamination. Each square centimeter of a wafer could theoretically come into chemical contact with in excess of 1,000,000 particles/min, greater than 1 mm in size, compared to 3 such particles in Class 100 air.

Low-particulate-grade chemicals have significantly lower particle levels than semiconductor-grade chemicals, but they still do not approach the cleanliness of Class 100 air. Most suppliers of low-particulate chemicals specify less than 10 particles/ml greater than 1 mm. Some of the better suppliers approach 1 particle/ml. Nonetheless, technologies with device geometries of 1.5 mm and less are consistently able to demonstrate improved yields with the use of low-particulate chemicals.

With agitation or recirculation of chemicals during use, flow rates of 30 to 150 m/min can be anticipated. At 30 m/min, each square centimeter of a wafer can contact up to 12,000 particles greater than 1 mm per minute of exposure to the low-particulate chemical. However, it has been found that immersion in low-particulate-grade hydrofluoric acid (HF) leaves less than 0.1 particles/cm² on a wafer. With sulfuric acid, the residue was twice that of HF.

There are presently few standards of cleanliness for chemicals in the semiconductor industry. It is not uncommon to find one supplier's semiconductor grade to be dirtier than another's electronic grade. The only reliable way to determine chemical cleanliness is to perform a chemical analysis of the product for impurities.

The chemical purity (assay) of the product must be very high to prevent unwanted reactions to the wafer from unknown chemical impurities. Clean-room packaging is also necessary to insure contamination-free wafers. Steps include bottle washing, lint-free labels, and bagging of the bottles during shipment.

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In the interest of economy, many IC suppliers purchase clean chemicals in bulk quantities. Special care must be maintained to ensure the continued cleanliness of the chemicals. Where possible, the bulk containers should be stored in clean areas, and transfer containers should be cleaned on a regular schedule. Of particular concern is cross-contamination. Each container should be reserved for one chemical only. Additional employee training and discipline are required if a bulk chemical system is used.

However, there has been a major move, primarily by SEMI(Semiconductor Equipment and Material Institute)the industry trade organization responsible for establishing IC materials standardstoward establishing a classification method for chemicals based on the particle level per unit volume, with a detection limit for particles of 0.5 mm, 1.0 mm, and 5.0 mm. The important point is the need to develop clear particle specifications between the chemical user and vendor. Such specifications imply an agreement on the maximum allowable particle level for any given chemical or group of chemicals. The timely development of particle specifications and classifications is extremely important to the semiconductor industry, which depends to a large extent on the ability to consistently measure particles within processing chemicals. Such a measurement is a prerequisite for specifying a particle count limit. There is a need for more focused efforts throughout the electronics and chemical industries toward improving consistency in particle metrology.

The selection of particle specification limits must be made carefully, with the realization that the cleanliness inside the process bath is the issue. While the prepackaged chemical entering the process vessel must be clean, the ability to maintain cleanliness within the bath is equally important.

The various steps of the wafer fabrication process have differing degrees of sensitivity to particulate contamination, and this will need to be taken into account in choosing particle specification limits. For example, chemicals used for wafer cleaning (e.g., sulfuric acid, hydrofluoric acid, and ammonium hydroxide) prior to a thermal oxidation would perhaps have a tighter particle specification than chemicals used for wet photoresist stripping. However, because the particle sensitivity issue is not yet very well understood, care must be taken when making these judgments. When no particle limits have been previously specified, it may not be wise to set initially low limits that could not be met by a chemical supplier. Intermediate particle limits can be chosen and then systematically lowered to aggressively drive the supplier to improved purity. Such reasonable approaches to improve cleanliness are necessary to maintain a cost-effective chemical program.

Chemical purity also requires filtering the chemicals to a submicron level. VLSI requirements are 0.2 mm and less. The operation of a high-quality filtration and chemical packaging operation requires a thorough understanding of filtration. It should be noted that filtration covers more than just passing a liquid through

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a filter. The entire system must be consideredtanks, piping, pumps, nozzles, filters, filter housings, etc.

Filter efficiency is a major factor in filtration. The percent of particles retained by a filter can vary by filter type, media, pressure, volume filtered, and the chemical processed. The filter, filter housing, and seals must be carefully chosen to be compatible with the specific chemical being filtered. Often, because of chemical incompatibility, capacity, or throughout considerations, one is not always able to use the best filter media available.

Generally, filter capacity is not dependent on the amount of liquid filtered, but on the amount of particles removed. Thus, total capacity will not be seriously affected by recirculation of low-particulate solutions over an extended period of time. The total volume of new material filtered and the particulate level of that liquid are the deciding factors.

It might be more desirable, therefore, to use low-particulate chemicals initially to avoid the introduction of contaminated material, rather than rely on a recirculatory system to obtain the low-particulate levels desired.

Recontamination of a cleaning or etching bath is also a major cause of high particulate levels. Thus, having several sources of supply is important.

Poor housekeeping will do more to contaminate a bath than anything else. One dirty carrier, a faulty air-filtration system, or a dirty smock can quickly create a millionfold increase in the contamination level in a bath. Once immersed in an agitated bath, wafers become exposed to all the dirt accumulated by the handling equipment. If airborne dirt is not being removed from the bath faster than it is being generated in the local environment, low contamination levels will never be reached.

Constant bath recirculation and filtration systems have been extremely effective in maintaining low particle levels within the bath while wafers are being processed. Improvements in these systems have enabled the effective filtration of hot acids and cleaning solutions up to 130°C. The cleanliness of chemicals entering the baths from prepackaged containers is equally important.

The use of in-line filtration, together with low-particulate, high-purity chemicals, assures that the best technology is in place for chemical processing. A major advantage of low-particulate chemicals is the ability to reduce process variables and increase yield.

Gases*

Semiconductor wafers are exposed to industrial and specialty gases at every process step. Table 9.9 provides a typical listing of gases used at selected process steps. As dry processing becomes more prevalent, the use of various combina-

*Portions of this section excerpted with permission from Ref. 11.

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Table 9.9 Typical Gases Used in Various Process Steps [11]

Process

Gases

Plasma etching, reactive ion etching

Carbon tetrafluorides, chlorides, bromides plus intermixtures of these with O₂ and H₂

Chemical vapor deposition (CVD)

Silane, dichlorosilane/ammonia, trimethyl gases, tungsten hexafluoride

Ion implantation
Phosphine, arsine, boron trifluoride

Laser-enhanced CVD

Silane, trimethyl gallium, arsine, trimethyl aluminum

Sputtering
Carbon tetrafluoride, argon, oxygen

tions of gases will increase even more. As reactants, gases are now one of the major raw materials employed in the manufacture of integrated circuitsin addition to their use as diluents for other reactant gases.

Gas suppliers, like chemical suppliers, have developed lines of extremely pure gases for semiconductor manufacture. Gas purity is measured in four categories:

1. Purity

2. Water vapor content

3. Particulates

4. Metallic ions

High purity is required of the reactant gases used in oxidation, diffusion, plasma etch, CVD, reactive ion etch, and other fabrication processes. If the gases are contaminated with other gases or hydrocarbons, unwanted reactions will take place, or the rate of reaction will be changed. For example, contaminants in argon used in sputtering can end up in the sputtered films.

Gas purity is specified by the assay number with typical values being 99.9999.9999%, depending on the gas and application.

Dry gases (no water vapor) are essential in semiconductor processing due to the ease of oxidizing silicon. At all process temperatures even trace amounts of H₂O can cause the growth of SiO₂, which can block diffusions or cause uneven epitaxial growth. Water vapor limits are typically 5 ppm.

Gaseous impurities (e.g., H₂O in argon) are distributed uniformly in the critical carrier gases. In wafer processing, the effects of such impurities are twofold. Uniformly distributed impurities produce either homogeneous defects or random point defects. For example, the incorporation of boron into epitaxial silicon is extremely sensitive to the presence of moisture. During epitaxial

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deposition in a hydrogen ambient, either moisture as an impurity or oxygen that forms moisture in situ can produce this general failure mode.

Conversely, both moisture and oxygen at ppm levels will oxidize silicon randomly and produce oxide inclusions, etch pits, or both. In a particular epitaxy run, the final result may well be improper boron-doping levels, etch pits, stacking faults, and future random gate-oxide breakdown problemsall dependent upon the temperature and rate of deposition during the run, as well as the integrity of the system delivering hydrogen to the reactor.

A purchasing specification of SEMI-grade hydrogen is necessarybut not sufficientto ensure the success of the process. Continuous monitoring of hydrogen purity just prior to its entry into the epitaxy reactor will not only alert one to an impending disaster, but will, during the course of time, permit one to define systematically the true acceptable levels of such sensitive impurities by correlating impurity data with process yield. Such monitoring can also provide valuable data for detection of the sources of impurities that affect the epitaxy process.

Process gases must be handled with extreme care to avoid degrading the wafer ecology. A static charge can be imparted by almost negligible friction, including the flow of nitrogen gas across a wafer's surface. An electrically charged wafer will attract ionized particles out of the environment.

In addition to this intangible contamination, process gases may contain particulates or traces of other gases. Like chemicals, supplied gases must be particulate free to below the 0.2-mm level. As is true for many other impurities, there are no reliable gas standards in the sub-ppm range. Ion implantation, for example, is a particularly sensitive process because any particulates will be implanted in the wafer along with the dopant.

Typically, particles in gases contribute to only 10% of the total particle problem. Even though people and equipment dominate over materials as sources of particles, gas-borne particles are potentially the most damaging, since they are guaranteed to be present during the critical, high-temperature processing steps. Although point-of-use filters provide a last line of defense, total process control dictates particulate monitoring and control of gases at all crucial steps.

Many of the particles found in the gas streams are oxides of metals, which silicon will easily reduce to free micro sources of metals that become point sources of impurities. The results are shorted junctions, defective oxides, lifetime killers, and lattice defects. All of the considerations and specifications concerning metallic ion contamination in water and chemicals also apply to gas.

Although semiconductor-grade specialty gases are now available with very low impurity content, storage and delivery systems degrade their purity. Gas suppliers can help prevent particulate contamination by constructing all tubing, tanks, and components of electropolished stainless steel. Electropolishing will remove surface cavities that may harbor particulate and bacterial contaminants.

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Unwanted trace gases may be virtually eliminated by dedicating bottles, even entire tank trucks, to a single type of gas during repeated use.

The semiconductor facility piping system is another source of gas particulate contamination. Great care must be exercised in installing and maintaining the in-house system. A major portion of epitaxial system preventive maintenance is system cleaning, to guarantee particulate-free gases.

Since gas transport and delivery systems are both sources and sinks for particles, and the raw material gases are constant sources of particles, gas purification is mandatory. However, total purification, that is, absolute removal of all vapor contaminants, is an elusive goal. Purifiers are designed to convert contaminants either to solids or to trappable gaseous species. By using available catalysts and absorber materials, they reduce undesired vapor impurities to sub-ppm levels. However, exactly what levels are needed for improved VLSI circuit yields is an unresolved issue. With the known propensity of gas systems for leaks, real and virtual, and for cross-contamination in downstream systems, as low as possible is a logical goal.

Filtration, especially redundant filtration, is prudent for particle purification. Filtration of gases by means of membrane technology in carefully constructed and maintained filtration systems results in particle counts at or below the 10-per-cubic-foot level.

Additionally, continuous monitoring of gas purity at the point of use is becoming mandatory to ensure process integrity and corresponding wafer yield. A continuous quality-control gas analysis system can analyze gas streams to provide both real-time process control and data for correlation of gas composition with wafer yield. Point-of-use verification of gas purity is fully analogous to continuous monitoring of DI water purity. For DI water, singular measurement of resistivity is sufficient to verify nominal system performance and to provide a measure of confidence that the wafers being processed are not at risk: It is an indicator of impending loss of control. Resistivity is a gross measurement of all ionic contaminants, and, except for diagnostic purposes, no effort is made to evaluate the nature of the contaminants. Carrying this analogy too far with purified carrier gases fails, as there is no detector for vapor impurities that is equivalent to the resistivity probe. Each impurity must be monitored separately, and each can comprise a separate source of yield loss at different steps in wafer processing, as in the example cited previously for epitaxy.

Seasonally adjusted yield and phase-of-the-moon models have found validity in the semiconductor industry. Such observations have led to identification of climate as a valid parameter. Depending on the source of the raw water and the season, DI water may contain varying levels of nonionic, nonfilterable contaminants that can affect yield dramatically. Similarly for gases, it has been found that carbon monoxide as a contaminant exhibits a strong seasonal and geographical variability. During certain critical processes such as base drive-in

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or source and drain implant annealing, carbon monoxide should be controlled to less than 0.5 ppm.

Thus, as the gas systems increasingly influence processing yield, and as they become more active components in the facility, the value of monitoring becomes much more important and critical to achieving high yield wafer processing.

Gas and Vacuum Distribution Systems

Perhaps one of the most overlooked but important aspects of a gas system is its distribution lines. These lines, with hundreds of feet of tubing or pipe, and hundreds of fittings and joints, can cause complete system failure if each component is not properly handled. Some guidelines for the construction of these distribution systems are as follows:

Use low carbon grade electropolished 316 stainless steel (316L) materials for all regulators, bellows, diaphragm valves, flow detection and control devices, pipes, and fittings.

Smooth surfaces are less likely than rough surfaces to temporarily trap impurities and particulate contamination.

A secondary treatment of electropolishing will produce smoothness and surface finishes not normally attainable by conventional methods.

Cast materials of any type are not recommended if in contact with the gas stream.

Electropolished tubing should be cleaned and purged with high-purity nitrogen, then capped and sealed.

Electropolished tubing/pipe should not be bent or formed, since there is a tendency for the surface finish to flake off during the process. Elbows should be used instead of bending the tubing.

If threaded pipe must be used in the system it should be used sparingly and with an application of a Teflon PFA-based dopant or Teflon PFA pipe tape on the threads. Don't use excessive tape, since it will tear off and get into and contaminate the system.

When using small-diameter tubing [1.27 cm (½-in.) diameter or smaller], tubing benders are preferred to individual fittings. This method is less expensive and reduces additional sources of contamination. If the bending method is used, cleaning should be done after bending and deburring of the tubing has been completed, using a Freon solvent flush followed by an isopropal alcohol rinse to facilitate drying.

For flexible lines an assembly consisting of extruded hose of virgin Teflon PFA with the appropriate stainless steel fittings and a protective stainless steel overbraid and fitting swaged to the hose is recommended. In the

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past these flexible lines have been a major source of contamination, especially corrugated copper lines.

It is important that all system components be of the same or higher quality material as the distribution system. This also applies to the process equipment. It is best to use electropolished stainless steel components and tubing after the point-of-use filters.

All regulators and flow gauges used in the system must be oil-free, such as those designated for use in oxygen service. Care should be taken to ensure that regulators and flow gauges are kept as clean as possible. Inspect all threaded portions for damaged threads or burrs. Defects of this type will produce galling and/or gross particle generation.

To maintain good leak integrity (10⁻⁷ cm³/sec), gas piping should be welded using purged orbital welding techniques wherever possible.

The use of connectors should be kept to a minimum.

As in water systems, the use of hard 90° bends should be avoided and the same radius specifications will apply.

Bellows or diaphram valves with a guaranteed leak rating of 10⁻⁸ cm³/sec or better should be used.

Wafer Cleaning*

Scrupulously clean wafers are essential in the fabrication process, and this cleanliness requirement is one of the most critical factors for both obtaining and maintaining high wafer/die yields. Wafer fabrication yields are drastically reduced when contamination from foreign particles or chemicals from a variety of sources adhere to the wafer surface. For optimum yields to be realized, as many particles as possible must be removed using various wafer-cleaning methods; and those cleaning methods must constantly be improved to address smaller and smaller particles.

Submicrometer particles are the main obstacle in wafer cleaning. For unprocessed wafers, liquid immersion is helpful but inadequate for removing all particles greater than 0.3 mm. Capillary adhesion, the strongest force binding the particle to the surface, can only be overcome by mechanical scrubbing.

Wafer cleaning has become a standard wafer-processing step. However, the optimum cleaning method varies with the specific wafer surface to be cleaned, the contaminant to be removed, and the subsequent processing to be performed.

The most common wafer surfaces to be cleaned are silicon dioxide, silicon nitride, polysilicon, metal silicides, aluminum films, refractory metal films, and sputtered or deposited glasses. The cleaning of both silicon and gallium arsenide wafers is very similar. However, GaAs is extremely fragile and requires very

*Portions of this section excerpted with permission from Ref. 12.

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gentle handling through all processing operations to maintain adequate throughput yields.

Silicon is cleanest before it is sawn from the ingot. After that is a constant uphill battle to protect the wafer's valuable real estate from a never-ending invasion of foreign particles and atmospheric contamination.

Contaminants in a clean-room environment, where all wafer fabrication is typically accomplished, come from a multitude of sources, as was discussed in the previous sections. Although most foreign particles are generated from people (skin particles, fingerprints, and inferior wafer handling), those that end up on the wafer itself actually come from the process equipment: the accumulation of dust and silicon particles on the process equipment, and the generation of particles caused by machines that have numerous moving parts in the vicinity of the wafer-handling processes. This can account for approximately 60% of the foreign particles landing on the wafers in a modern clean room. The clean-room air and the chemicals that are used for some types of cleaning in the process may contribute additional contamination.

Integrated circuit wafers are subjected to physical handling during the processes of cutting, lapping, polishing, and packaging. This leads to large amounts of molecular contamination, much of which is of unknown origin. Included in the list of such contaminants are airborne bacteria, grease and wax from cutting oils and from physical handling, abrasive particulates (usually silicon carbide, alumina, and diamond dust) from the grinding and sawing operations, and a variety of plasticizers that come from the containers and wrapping in which the wafers are shipped. Removal of these contaminants is the first step in wafer cleaning, and is usually done by rinsing in hot organic solvents such as trichlorethylene or xylene, accompanied by mechanical scrubbing, ultrasonic agitation, or compressed gas jets.

Let's address each of these types of wafer cleaning methods: chemical, mechanical, and sonic.

Chemical Cleaning

Chemical cleaning is imperative in the wafer fabrication process to remove chemically bonded ionic- and atomic-level contamination. Ionic contaminants result from improper cleaning or from etch steps during processes, such as the opening of a window or the delineation of a metal interconnection pattern. Some of the worst chemical contaminants (sodium and potassium) are due to trace impurities in the etchants and adhere to the semiconductor surface by physical absorption or by chemisorption. Light metal ion contamination is particularly undersirable in MOS ICs where it can cause instabilities in the threshold voltage. However, it can often be tolerated to a greater extent both in gallium arsenide and in bipolar silicon ICs.

Conventional chemical cleaning is performed with a series of acid and rinse

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baths. These processes are considered proprietary by most IC suppliers. Desorption of a large fraction of these ions can be accomplished by rinsing in hot deionized water for a few minutes. However, their complete elimination generally requires chemical reaction with the semiconductor surface, accompanied by flushing to remove these soluble reaction products. HCl treatments are especially effective for this purpose.

Heavy metal impurities can also be present as contaminants on the semiconductor surface, and usually come about by deposition out of the etchant solutions during device fabrication. Gold, silver, copper, iron, and nickel are common impurities found in most electronic-grade chemicals of the type used in IC fabrication technology. Although these impurities are present in a few parts per million, this represents a significant amount of chemical contamination, especially in circuits where the control of minority carrier lifetime is important. Etching processes will generally leave only small amounts of these impurities on the surface, since they involve removal of semiconductor material, with continual flushing away of the surface reaction products. Oxidizing agents, such as H₂O₂ and HNO₃, tend to form a thin protective coating on the semiconductor, so that heavy metal contamination is not severe when these chemicals are used.

Heavy metal contamination primarily comes about during processes that dissolve the IC protective oxides but leave the surface unattacked. An example of one such process is the opening of a window in an oxide or nitride layer, prior to diffusion. Here, uninhibited electrochemical displacement plating can occur, because of the large difference between the oxidation potentials of the semiconductor and the metal ions in solution, resulting in contamination levels as high as 10¹⁶/cm².

Tolerance to ionic and atomic contamination, and hence the appropriate surface cleaning treatment, is a function of the device operation. Thus, a cleaning solution involving the use of sodium-based materials (NaOH, NaOCl, etc.), which may be quite acceptable for devices in gallium arsenide, cannot be tolerated for MOS-based silicon circuits, unless a second cleaning solution is used to remove the sodium contamination. Here, surface cleaning should be carried out by the use of chemicals that are volatile in their composition: HCl, HNO₃, NH₄F, H₂O₂, and H₂O.

All wafers must receive an initial cleaning in hot organic solvents. In addition, further cleaning of wafers must be done after each processing step in the fabrication sequence, and especially before each high-temperature operation. As far as possible, the same cleaning process should be used at each point, and made as routine as possible, in order to avoid operator error.

One highly successful approach to cleaning silicon is to use two solutions in sequence, for example, NH₄OH:H₂O₂:H₂O. Here the hydrogen peroxide functions to oxidize all remaining organic contaminants on the surface, which are present

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because of incomplete removal of resists and also due to airborne materials and physical handling. Neither wet chemistry nor plasma stripping does a complete job in this area. Residues from the plasma process also present a problem here. The ammonia is effective in removing heavy metals such as silver, cadmium, cobalt, copper, mercury, and nickel, by forming complex amine groupings with them. Next, a solution consisting of HCl:H₂O₂:H₂O is used to remove the light alkali ions, and to prevent displacement plating from the solution.

Each of these steps is carried out for 1020 min at 7585°C, under conditions of rapid agitation. Nitrogen gas bubbling through the etchants is often used for this purpose. Finally, wafers are blown dry and stored in a clean environment until further processing. This cleaning technique is widely used because of its suitability for both bipolar and MOS ICs.

A large number of special-purpose techniques are also used in individual situations. Many of these are unique to each IC supplier, and are often closely guarded trade secrets. A few of the more well-known cleaning steps are described below.

Heavily doped silicon will occasionally become stained by the formation of a suboxide on its surface. A 1015 sec dip in a solution consisting of 2 volumes HF to 1 volume KMnO₄(6% solution) will remove this stain. A small amount of silicon is removed during this process.

An excellent cleanup step, widely used for silicon, consists of HNO₃:HF:HClO₄:CH₃COOH. This solution is particularly effective in removing heavy metal impurities, and has been used prior to the oxidation of silicon in high power semiconductor circuits requiring long lifetime.

Oxidized silicon wafers that are stored for any length of time will often become contaminated within the top 50 Å of the oxide layer. This contamination is best eliminated by actual removal of this upper layer of oxide in a short etch consisting of HF:H₂O. The etch rate of this formulation is about 70 Å/min, so that an immersion time of 4560 sec is satisfactory.

Water is a major contaminant of oxidized silicon wafers and can be adsorbed in molecular form if wafers are stored for any length of time. Its removal, by a 250°C heat treatment of 2464 hr, is an important process step just prior to packaging, or to the deposition of the final PSG or Si₃N₄ passivation layer. Junction walkout problems, and other instabilities in diode reverse characteristics, can be greatly reduced by this treatment.

In principle, the cleaning of gallium arsenide is very similar to that of silicon, and proceeds along these same lines. The starting point here is the use of strong solvents for removing organic residues that are present on the as-purchased wafer. The successive use of hot trichloroethylene, acetone, and methanol, each for 510 min, is very effective for this purpose. Wafers cleaned in this manner are blown dry and can be kept under methanol for a short time until ready for further cleaning or processing.

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Most of the cleaning formulations for gallium arsenide are of an etching nature, that is, they remove some of the gallium arsenide during the cleaning process. Heavy metal impurities such as gold, silver, copper, iron, and nickel have a tendency to plate out of the reagents during this process. This displacement plating can be minimized if the etch is rapid and accompanied by quick flushing away of the reaction products. Also, the etch should involve large amounts of deionized water to minimize the concentration of these metals.

Since chemical cleaning is a necessity, potential problem areas must be addressed. The clean room must be properly exhausted so that toxic odors do not introduce a hazardous environment for either wafers or personnel. Accurate control of the temperture and time must always be maintained for a repeatable process and consistent yields. The chemical solution also is degraded through the cleaning process and needs periodic replacement. One method of chemical cleaning is by centrifugal spraying, where the wafers are enclosed in a nitrogen-purged chamber and sprayed continuously in controlled sequence.

Mechanical Cleaning

Mechanical cleaning includes scrubbing one wafer at a time with a brush and/or high-pressure jet. Wafer scrubbers can be used very effectively if they are properly maintained and controlled. Ideally, they will remove both the inorganic particles and films that adhere to the wafer surface.

Scrubbing is the most effective method of cleaning. It is used in any and/or all of these steps: after sawing, lapping, and polishing, before and/or after chemical vapor depositions, before resist coating, and before the metallization processes. However, the semiconductor industry has nearly abandoned this method, because of bristle damage and particle redeposition, the problem being that most scrubbers used in the industry spray the wafer instead of the brush. If the brush is sprayed properly, a barrier of liquid is maintained around each bristle, thereby avoiding any surface damage.

High-pressure jet scrubbing is almost always used with brush scrubbing. This combination brushing action/jet scrubbing is very effective because the brush is able to dislodge films and particles, and the jet spray follows to remove any microscopic debris from circuit corners, depressions, and so on in the topography of the wafer, and any residual particles generated from the brush itself.

Sonic Scrubbing Techniques

Sonic scrubbing, better known as either ultrasonics (low frequency) or megasonics (high frequency), is another wafer-cleaning method. Though not as widely used, it can serve as an alternative to brush and chemical cleaning for specific applications. Sonic energy is transmitted into a detergent or solvent solution, whereby the resultant cavitation or wave action gently scrubs and persistently attacks particles until they are dislodged from the wafer surface and become

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suspended in the solution for removal. The advantages are high throughput, low wafer breakage, and reduction in the use of chemicals used. A disadvantage is the need for a separate process step and equipment for drying the wafers.

Drying

The cleaning process for each method of wafer cleaning involves removal of as much water and solvent as possible followed by drying. Typical methods include a high-speed spin of the wafer on a vacuum chuck, followed by exposure to a dry nitrogen stream, infrared radiation, or baking. The most popular method is to dry by spinning the entire cassette in a centrifugal chamber.

References

1. G. J. Sem, A case for continuous multipoint particle monitoring in semiconductor clean rooms, Institute of Environmental Sciences, 1986 Proceedings, 32nd Annual Technical Meeting.

2. Silicon Wafer Technology, Semiconductor International, July 1984.

3. P. W. Morrison and R. J. Yeak, Clean rooms for VLSI fabrication, Semiconductor International, May 1985, pp. 208214.

4. P. Van Zandt, Microchip FabricationA Practical Guide to Semiconductor Processing, Semiconductor Services, 1984.

5. P. L. Oliphant, The clean room enigma, Semiconductor International, September 1992.

6. L. A. Fergason, Analysis of organic impurities on silicon wafer surfaces, Microcontamination, April 1986.

7. N. Newboe, LSI reveals secret to 10% yield improvement, Semiconductor International, May 1992.

8. C. Mistry and J. Gililland, Microfiltration and product yield in integrated circuit manufacture, Microcontamination, May 1985, pp. 7188. Copyright © 1985, Canon Communications, Inc.

9. Biological fouling of purified water systems: Part I, Bacterial growth and replication, Microcontamination, October 1985. Copyright © 1985, Canon Communications, Inc.

10. J. Imbalzano and D. J. Dratzer, Effects of prolonged exposure of polymers containing fluorine to integrated circuit process water, Institute of Environmental Sciences, 1986 Proceedings, 32nd Annual Technical Meeting.

11. H. Boyd and D. De Bond, Process gas analysis for VLSI wafer fabrication, Microelectronic Manufacturing and Testing, April 1985. Copyright © 1985 Lake Publishing Corporation.

12. M. J. Daszku and G. Fong, Wafer cleaning technology for the eighties, Microelectronic Manufacturing and Testing, May 1985. Copyright © 1985 Lake Publishing Corporation.

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10
Human-Derived Contamination

Clean rooms are not closed systems. People, equipment, and materials are continually entering these fabrication areas, bringing with them particulate, organic, and metallic contaminants. In the 1980s people were the largest single source of particulate contamination. This is no longer the situation. Human-derived contamination has decreased, due to the attention paid to this category of contamination, from 45% of all sources of wafer fab contamination to about 5% today (1994). The items discussed in this chapter regarding human-derived contamination have been implemented, and then some, to effect such a dramatic reduction.

Human Traffic

Movement of workers within the clean room creates air currents that interfere with proper laminar flow. Any clean room that is short of perfect laminar airflow is going to have pockets of less clean air and areas of settled particulates. Unnecessary movement in the clean room will stir up these problem areas and may allow contamination to be drawn onto the product.

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The use of particle count control charts will help identify problem traffic areas, which tend to have wide limits and erratic ranges. Traffic should be limited in these areas to only those personnel necessary for performance of the job. It is also a good idea to check for contamination sources in adjacent areas whenever this control chart pattern is seen, since the particles being drawn by traffic into the monitored area must come from some adjacent area.

One way to check for sources is to set the particle counter alarm to go off when it counts a particle (some counters do not have this feature or else do not automatically reset the alarm). In this way one can trace the shape of the particulate stream back to its source, in much the same way that a Geiger counter locates the source of radioactivity. Particle counters that have an indicator on the probe showing approximate particle levels can be used in a similar way, with the source of contamination indicated visually rather than audibly.

Traffic should be limited in process-critical areas in any case, even if no pattern is recognized in the control chart. Any extraneous functions (e.g., data recording, socializing, or any other activities not directly involved with production) should be conducted away from process-critical areas. These areas may be restricted to only certain employees, since the particle counts in any one area will increase with the presence of each additional operator. If production is slow, anyone who is neither working nor cleaning should be removed from the clean room. Also, the number of visitors to the clean room must be limited, preferably to zero.

Visqueen or Plexiglas shields can be useful in isolating the critical areas. It is important to check the airflow at the edge of such a shield to ensure that turbulence created by air flowing over the edge is not causing room air to be drawn over the product. This check should be done using dry ice or liquid nitrogen.

Talkthroughs (or intercom systems) and passthroughs are helpful in maintaining low traffic levels. Any passthrough should be accompanied by a talkthrough or an intercom system to prevent the use of the passthrough for purposes of conversation.

A typical facility utilizes a double-door entrance as a dressing area. Entering personnel don various garments stored in the partially clean area. Before moving into the clean room itself, the personnel are required to pass through an air shower to knock off particulates. At the entrance door, there is a tacky mat to pull off any dirt on the shoes or shoe coverings.

Ultimately, the solution to human-induced contamination will involve replacing clean-room operators with a fully automated system capable of monitoring its own operation and correcting out-of-specification performance. But getting humans out of the clean room is only a partial solution to the contamination problem. We also must build automated equipment that will not add its own contaminants to the process environment.

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Human dirt and effluvia create contamination problems that are simultaneously bacterial, chemical, and particulate. The human body continuously sheds an incredible number of microscopic particles.

Moisture droplets are ejected with every exhalation, blink of the eye, sneeze, cough, and even every word spoken. The clothes we wear also shed tiny particles. The natural chemical complexity of human dust is compounded by the proliferation of cosmetic preparations that are rubbed, sprayed, and painted on the skin: Powders, cosmetics, powdery deodorant sprays, and hair sprays all eventually end up as airborne contamination. These products contain an amazing variety of compounds and metals, including iron, zinc, and titanium compounds, mica dust, carbon black, and numerous organics. In addition, each microscopic skin scale is a potential raft for bacteria, which, when provided a nutritive environment, can multiply and become another source of chemical contamination.

Human Dust

Let's look into this human contamination problem in greater depth. Human dust or skin flakes, composed of the protein keratin and appearing white in color, are shed by the human body in a continuous cell growth process. A complete layer of skin is shed every few days. These skin flakes might not be too serious a contaminant if they occurred alone as a dry material. But the cells are associated with oily glandular secretions, which cause them to adhere to surfaces. Skin flakes exhibit great variety in appearance and size, depending on their source and history. They are fluorescent and can be detected with ultraviolet light. Freshly rejected scalp or beard flakes are heavy with body oils and, occasionally, clinging dirt particles. If these flakes were to fall on a wafer and be broken into smaller particles, releasing their associated oils, they could be sites for defects, depending on the subsequent processing steps.

In the form of dust, skin flakes are exposed to the air and settle on surfaces, and their oils dry out. Skin flakes may fragment under the slightest mechanical force, even the pressure of an air gun. Strong mechanical forces such as brush cleaning or ultrasonic agitation can crush them into tiny particles and disperse them across the surface. Human dust has been found to be highly insoluble as well as resistant to heat.

While large skin flakes and individual cells usually can be recognized in the light microscope or the electron microscope by their physical appearance, tiny fragments are very difficult to identify. Sophisticated chemical analytical tools, such as the fluorescence microscope, may even confuse the identification by picking up traces of elements from associated cosmetic contamination (e.g., zinc from a compound used in some shampoo formulations).

Because skin flakes are soluble in ordinary processing chemicals, they may

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absorb liquid and change in appearance accordingly. For example, upon exposure to hydrofluoric acid (HF) or common organic solvents the particles may appear irridescent, particularly when viewed on a reflecting surface.

To study the effect of human dust on wafer quality, two bare silicon wafers were deliberately contaminated by skin flakes from hair, a beard, and a fingerprint [1]. The wafers were exposed for 20 min at 1000°C in an oxide furnace (O₂ + HCI + N₂). Photographs taken before and after oxidation demonstrated that all of the contaminants caused defects in the oxide film (i.e., the oils interfered with the oxide formation). In another experiment, skin flakes were added to a wafer and exposed to the low-pressure chemical vapor deposition (LPCVD) nitride process. The results were very different from those of the oxide experiment. All of the residues, particles and oils alike, cause defects in the nitride film, but the particles appeared to be consumed in the process.

Skin flakes and oils can be transferred to products by handling and by contact with contaminated tooling or instruments. Because the back as well as the front of a product is immersed in process tanks, care must be taken to clean tooling surfaces that contact any part of the product. Moving parts from which particles can be dislodged must also be kept clean. Clothing fibers are usually decorated with skin flakes of assorted sizes. The large dry fibers can easily be blown or washed away, but the associated skin flake residues are often left behind on the surfaces.

Detergent cleaning, which requires rinse and dry procedures, is the most effective means of removing fresh human contamination. Optical parts are sometimes cleaned with ether or chloroform diluted with alcohol. Strong chemical combinations that include hydrogen peroxide as an effective agent are used for cleaning semiconductor wafers. Steam cleaning is helpful for some products. Skin flake residues that become embedded in product layers constitute permanent defects.

Protective Garments

Although the problem of human-induced contamination is well recognized, a viable technological solution does not yet exist. The only solution available is to eliminate as much surface dirt as possible and cover up the remaining dirt. This involves the use of special clean-room garments (bunny suits). Even the best clean-room garment available is not capable of containing all of this human-generated contamination. The degree of personnel garmenting and cleaning depends on the type of devices being made and the yield experience of a particular company. The basic dress of a lab smock made from a nonshedding, nonstatic-producing material is ineffective. Additional gear includes a hat or hood; shoe coverings; gloves; and special hoods or surgical masks for facial hair.

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The range of gowning practice is from street clothes (low tech) to extremely elaborate procedures, requiring head-to-foot suits (VLSI).

Before investing in a garmenting system, it is worthwhile to find out approximately how many of the visual defects in the IC are actually traceable to human contamination. This can be accomplished, with reasonable certainty, by sending high-defect-density rejects to a scanning electron microscopy (SEM) lab for characterization of the visual defects, normally after an oxidation step. If the results indicate a probability that the defects are generated by human dust, garments offer a good solution for maximum protection. Even if the results are inconclusive, one should not rule out the use of a more protective garment for clean-room workers.

Table 10.1 compares five different clean-room garment types. Although the construction of the protective garment is a factor in determining its efficiency as a barrier, the information presented in Table 10.1 assumes that construction is of equivalent quality for all garments.

Table 10.2 summarizes the clean-room garment requirements for various categories of clean rooms. While the information in Table 10.2 will vary from source to source, it nevertheless offers a good estimate of what type of garment is required for each cleanliness level. (It should be noted that regardless of the garment precautions taken, it is necessary to limit the number of people in the clean room area at any given time.) Figures 10.1 and 10.2 show examples of several commercially available clean-room garments.

Perhaps the greatest danger of contamination to wafers comes from an operator's hands and fingers. The salt and oils always present on human skin can render the devices inoperable due to sodium contamination. To combat this problem, stainless-steel tweezers, commonly found in chemical and medical laboratories, were used in the semiconductor industry. However, the tool's design allowed gripping the wafer in the center, causing torn photoresist and contamination, and today limited-grasp tweezers, specifically designed for handling wafers, have become the standard design. This design limits wafer contact, except at the very edge. Unfortunately, the physical contact of the tweezer with the wafer edge still results in some chipping and torn resist. The chipped region can serve as a starting point for crystal damage, and during processing the damage can spread from the edge to the wafer interior.

Vacuum wands resolve both the wafer surface and edge damage problems. The wafer is held on the back by vacuum from a small wand. Another advantage of vacuum wands is their permanent location. Unlike tweezers, they are not convenient for use as screwdrivers or fingernail cleaners and do not get stored in lint-infested pockets.

In some situations, wafers must be placed or picked up from a horizontal flat surface. Bernoulli pickups are convenient for this task. A stream of filtered nitrogen flows out of the apparatus, creating a negative pressure. The principle

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Table 10.1 Characteristics of Several Clean-Room Garment Types

Weave

Dacron

Carbon-impregnated Dacron

Expanded PTFE laminate

Tyvek

Characteristic

Taffeta

Herringbone

Taffeta

Taffeta

Nonwoven

Pore size after wear

30100mm
1530mm
94% exclusion at 1 mm
<0.5 mm
<0.5 mm

Acid resistance
Poor
Poor
Poor
Good in short duration
Good in short duration

Vapor transmission
Good
Good
Good
Good
Poor

Relative cost per unit

Low
Low
Medium
High

Low, but must be replaced often

Antistatic properties

Poor; topical required

Poor; topical required

Excellent; carbon thread spun in

Poor; topical required
Poor; topical required

Miscellaneous information

Washable, durable fabric

Washable, durable fabric

Carbon thread can break down with use or acid exposure; washable

Two-ply style durability is not established, three-ply more durable; washable/dry cleanable

Disposable; washable to limited extent if thicker grade is used

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Table 10.2
Clean-Room Garments Required for Various Cleanliness Levels

Class 10,000
Dacron taffeta smock and bouffant cap

Intermediate
Hooded Dacron taffeta smock

Class 1000
Hooded Dacron or Tyvek smock and booties

Intermediate
Hooded Dacron or Tyvek jumpsuit and booties

Class 100
Hooded Dacron jumpsuit with booties, face mask, and gloves

Intermediate

Hooded Tyvek or expanded PTFE laminate jumpsuit with face mask and gloves

Class 10

Hooded expanded PTFE laminate jumpsuit with face mask, gloves, and eye protection

is the same as a breeze creating a negative pressure in a chimney. The wafer is drawn into the negative pressure region. When using a Bernoulli pickup, the wafer floats in the nitrogen, making no physical contact with the pickup. Care must be exercised to insure that the nitrogen flow does not blow contamination on nearby wafers.

Unless they are properly trained, production operators can damage the product by improper handling; techniques that may be perfectly sound in a hobby show or sewing room are absolutely taboo in the clean room. The operators must realize how critical it is to protect the product at all times from contamination, and they must know how to do this. It is important to establish clean-room guidelines and to insist that everyone, regardless of rank, follow them. Current employees must be retrained; incoming employees and visitors should not be admitted until they clearly understand these guidelines. All service and support personnel must also be dedicated to following the clean-room guidelines.

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Figure 10.1
Clean-room garments with self-contained air filtration circulation systems. A
particle-control fuse shield system, using a battery-powered HEPA air filtration system,
isolates the wearer's breath with a solid lens.

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Figure 10.2
(a) A clean-room garment made of a laminate membrane of nonlinting expanded PTFE
bonded to a knit fabric for use in Class 100 and 10 clean rooms. (b) Inherently
static (ESD) dissipative clean-room garments made of multiple-filament polyester.

Reference

1. E. W. Moore, Contamination of technological components by human dust, Microcontamination, September 1985.

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11
IC Processing Contamination

Contamination in IC manufacturing can be traced to a number of sources, including foreign particles, trace metals, organic films and residues, hydrogen, halogens, and other interfering substances. Table 11.1 shows a recently prepared list of device manufacturing processes and equipment considered to be sources of such contamination. The largest single source of particles in a typical fabrication facility is that generated by the process equipment (Fig. 11.1). Examples of particulate contamination in semiconductor equipment are listed in Table 11.2. The materials used to manufacture this equipment outgas, contaminating wafers. According to the National Institute of Standards and Technology (NIST), particle formation resulting from chemical and physical processes inside CVD reactors is the primary source of particle contamination in semiconductor manufacturing.

Most wafer processing equipment actually degrades the clean-room environment during operation. Equipment-induced contamination is generally caused by either dynamic or static interactions between wafers and surrounding objects. The dynamic transfer of impurities results from movement in the process environment. Frictional movement, like the rotation of a photoresist spinner,

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Table 11.1 Contamination Ranking of Processes and Equipment

Rank

Process/equipment

Types of contamination

1
Resist strip
Partcles, metals, organics

2
Wet etching and cleaning

Metals, particles, organics, oxides, residues

3
Chemical vapor deposition

Particles, metals, organics, hydrogen, halogens

4
Sputter deposition
Particles, metals

5
Reactive ion etching
Metals, particles, organics, halogens

6
Ion implantation
Particles, metals

7
Oxidation and diffusion
Particles, metals

may add metallic impurities to the process environment; even the activation of a solenoid can release contact metals. Static interactions are more subtle. For example, volatile pigments used to color plastics can oxidize and release minute traces of titanium and aluminum into the air.

Wafer-processing equipment may also be responsible for intangible forms of contamination. For example, light bulbs in the stepper will eventually dim and fail to thoroughly expose all of the photoresist. Unexposed photoresist may remain on the wafer after etching and foul any subsequent fabricat ion steps.

Progress also is being made in developing mechanical equipment that does not generate contaminants during operation, such as low-particle-generation automated robotic systems.

Figure 11.1
Sources of contamination in a fabrication facility.

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Table 11.2 Sources of Particulate Contamination in IC Process Equipment

Process

Sources of Contamination

Flow distribution

Filters, valves, seals, welds, mass-flow controllers, pressure regulators.

Photolithography

Loaders/handlers, resist spinners, chemicals, pumps, spin dryers; particles on photomask prior to development may create pinholes or islands.

Ion implantation

Loaders/handlers, vacuum vent cycles (high turbulence), beam-induced sputtering; resist chips may block implants.

Chemical vapor deposition

Loaders/handlers, quartz tube, gas-phase reactions, spalling from reactor-chamber walls, vacuum cycles: particles may form breaks or shorts in polysilicon interconnections; holes in passivation layers due to particles may cause premature device failure.

Sputtering, evaporation

Loaders/handlers, spalling from reactor-chamber walls, vacuum cycles: particles may from breaks or shorts in metal interconnections.

Epitaxy

Loaders/handlers, quartz reaction chamber, gas-phase reactions: particles may cause stacking faults or spikes to form.

Diffusion

Loaders/handlers, quartz diffusion tube: particles may inhibit or enhance the doping process.

Oxidation

Loaders/handlers, quartz diffusion tube: particles are considered to be the leading cause of gate-oxide failure.

Particles generated within process equipment contribute to wafer contamination either by surface migration or by aerosol deposition. Surface-migrational effects are prevalent in processes that involve a large number of moving parts, with particles being transferred from one surface to another as adjoining surfaces come into contact. Wafer-handling systems often contribute particles to wafer surfaces in this way.

Aerosol deposition is a primary mode of particulate contamination in the microelectronics industry. Particles generated within equipment become entrained in process flows and are transferred to wafer surfaces through the following aerosol-deposition mechanisms: inertial impaction, boundary-layer interception, gravitational settling, Brownian diffusion, and triboelectric effects. Binding forces that act between individual particles (or agglomerates) and the wafer surface may cause particles to adhere strongly to wafer surfaces.

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Much of the focus in IC processing is directed toward solid particulates such as dust, silicon particles, resist debris, lint, skin flakes, cosmetics, etc. Such particulates impact device patterning, eit her by shadowing the photoprocess or by embedding in deposited surface layers. In contrast, heavy metal contamination interacts atomically and electrically with the semiconductor. If it diffuses into the bulk, it becomes a highly efficient minority-carrier recombination center; if it migrates to an oxide interface, it produces a localized charge region. In these events, the electrical operation of the IC is impacted by the charge state of the contaminant, rather than by geometrical distortions. In addition, heavy metals can form silicide precipitates when contaminated wafers are cooled from high temperature. Such defects form localized highfield regions in oxides or at p-n junctions, causing premature breakdown under voltage application.

Ion implantation, plasma etch, and resist ashing introduce the largest concentrations of the heavy metals Fe, Cu, Ni, and Cr (see Ref. 1 for details).

Photomasking and Photoresist Defects*

The essence of a high-quality photomask resides in its ability to generate devices of high reliability at economically viable yield rates.

As integrated circuit design entered the submicrometer region and devices included more and more circuitry, defects that were once tolerable became significant problems. For example, single mask anomalies, which once killed individual dice in contact and proximity printing, became costly repeating defects in stepper technology. Thus, defects that occur during the photoresist and photomask operations significantly impact finished device quality, yield, and reliability.

Mask Defects

Mask defects include pinholes, spots, intrusions, protusions, bridges, breaks, missing geometry, and glass fracture. These are illustrated in Fig. 11.2 and defined next. Such defects are a function of the quality control exercised by the mask maker, as well as the care taken in using the starting materials.

Pinspot. A small chrome spot that can normally be repaired by vaporizing the chrome with a laser. These are usually caused from contamination during mask making.

Protrusion. An extension of chrome from the edge of a geometry, which can often be removed with a laser, although it is not as critical as other defects. These are usually caused from contamination during mask making.

*Portions of this section used with permission from Ref. 2.

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Figure 11.2
Common photomask defects.

Bridge. A chrome link between two geometries. This can be removed by laser.

Opaque spot. Due to their position, some opaque spots cannot be repaired. In this case, they must be scrapped.

Pinhole. This type of defect will affect the area of the die if not repaired. They are usually caused either by process problems in mask making, or by the raw material used.

Intrusion. The opposite of an extension, this is seen as a nick in a geometry. This can be repaired with a hole plugger.

Break. A broken geometry, which can be repaired, again caused by process problems or raw materials.

Missing geometry. Any defect in this category will require the mask to be placed on hold for review by quality control engineering.

Glass damage. Glass chips, scratches, or seeds caused by process problems, equipment problems, or mishandling can cause printing errors.

Solvent spot. Water and chemical stains, photoresist, fingerprints, etc. If contamination is excessive or is not removable by ordinary cleaning procedures, the mask must be held for review.

Unknown. It is possible that automated inspection systems signal a defect where there is none, requiring careful visual inspection.

Extreme cleanliness is required during the fabrication of reticle masks, and a detailed examination of each exposed mask is essential before it can be replicated. A number of different methods are used for mask inspection. The

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simplest approach is to directly compare one die pattern with another on the same mask. This is done by first optically overlaying these patterns and then following with visual inspection. A second approach is to compare a die with a defect-free pattern that is stored in digital form in a computer. This approach has the advantage that it can be carried out automatically.

A somewhat similar approach is to scan two dies by a dual-beam flying-spot scanner and compare the signals by electronic means. Spatial filtering techniques have also been used for this inspection purpose.

Dimensional errors can also occur during mask making. These can only be determined by both line-width and run-out measurements on the mask. Some visual defects can be repaired, while other defects, primarily dimensional errors, require that the mask be redone. The following sections specifically address mask defects as related to substrates, chrome masks, and resists.

Substrates

Glass substrates must be extremely clean. In addition to meticulous grinding, polishing, and washing, many vendors irradiate and vibrate their substrates in various environments to achieve cleanliness. Still others coat masks with proprietary materials to reduce or deactivate defects and enhance chrome adhesion, but which must be removed prior to loading in the mask equipment. The potential for substrate-generated defects has been nearly eliminated by the better quality photomask vendors.

Physical substrate defects such as scratches and particulates can be detected to some degree by microscopic examination. Scratches in the glass surface produce nonuniform etching in localized areas, particularly at geometry edges. Figure 11.3 illustrates some typical defects. Glass pits inhibit chrome adhesion, producing pinholes and intrusions. Fractures inhibit chrome adhesion and can also be imaged, resulting in additional defects. Improper polishing or cleaning of the substrate will also result in poor chrome adhesion, and thus produce subsequent defects such as mousenips.

It should be noted that quartz substrates tend to be less subject to defects and also show a marked increase in adhesion to chrome.

Chrome Masks

The majority of photomasks currently in use employ chromium deposited by either evaporation or sputtering onto the glass substrate. Chrome defects include

1. Particulate inclusions which cause pinholes in process

2. Pinholes or voids in the chrome surface

3. Nonuniform coating, which results in uneven etching

4. Poor adhesion to the glass substrate, causing pinholes or voids

5. Invisible or chemical anomalies such as nitrides or carbides, which

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Figure 11.3
Typical defects found in glass, chrome, and photoresist. (a) Edge problems
result from scratches in glass surface, producing nonuniform etching in localized areas.
(b)Chrome adhesion can produce bridging. (c,d) Chrome spots and pinholes caused
by resist defects.

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erratically affect local etching and/or create undesired patterns of unique morphology

The defects shown in Fig. 11.3ad can be detected by microscopic examination, thickness measurements, or destructive tests. They are often visually detected in the finished mask.

Invisible defects can be detected only by surface analytical techniques such as scanning auger microanalysis (SAM) and electron spectroscopy for chemical analysis (ESCA).

Resists

Resist defects include voids that produce pinholes, and particulate inclusions that may result in pinholes or chrome spots (Fig. 11.3) depending on location and process. Common photoresist contaminants manifest themselves as colloids, gels, and insoluble constituents and may affect resist solubility locally. Unevenness produces image irregularities, especially near the edges of the photomask. Finally, surface particulates can obscure the imaging radiation, creating chrome spots of similar structure.

Sources of the contamination can be traced to manufacturing, shipping, handling, poor storage and application, as well as being a direct result of usage relative to the type and control of spinner track cleanliness and preventive maintenance to the dispense pump and associated process plumbing. Point-of-use photoresist filtration can overcome these sources of contamination, resulting in low levels of photoresist particulates.

Residues of photoresist, due to incomplete or improper cleaning, on an oxide, can cause contamination problems that, when the metal is sputtered, leave voids between the oxide and metal, allowing moisture penetration and thus corrosion. The photoresist residues, being organic, can penetrate the oxide layer. Residues of photoresist on top of the metallization can cause wire bond problems by not allowing adhesion of the bond to the aluminum. Thus, plasma cleaning should be used prior to assembly.

Table 11.3 summarizes some common reject causes that occur during the photolithographic-photoresist processing sequence. It is important to note that a single cause of reject can come from a number of different processing steps, thus a root-cause analysis must be performed. Furthermore, most resist defects can be detected by visual or mechanical methods.

Printing and Engraving Defects

A number of problems may be encountered during the opening of windows in the masking film. Some result in defective circuits that are rejected. More serious, however, are problems that result in an advertent spread of device parameters,

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which may impair the reliability of the IC and degrade its performance. Some of these defects are now discussed.

Undercutting of the Resist

If the resist adheres poorly to the masking film, undercutting may occur during the etching process, resulting in a larger window and changes in the associated device parameters after diffusion. In extreme cases, a defective circuit can result by short-circuiting adjacent regions. Undercutting of the photoresist results from capillary action of the (wet) chemicals that are used during the etching process. This problem is greatly reduced when plasma etching techniques are used.

Dimensional Variations

Dimensional variations may occur in the width of cuts in the masking film because of limitations of the photographic process. These, too, result in changing the effective area of the masked regions. The problem is especially severe when long, very narrow cuts are required and may lead to breaks in the metallization. These variations can also occur because of swelling of the resist during development. Positive resists are less susceptible to this problem than negative ones; therefore, they are preferred in VLSI applications.

Drafting errors should be considered in those cases where the mask is drawn × 250 prior to photoreduction. Here errors of 25 mm on the drawing are translated into 0.1-mm variations in the final circuit. Thus, dimensional variations due to these errors can usually be neglected.

Lack of Registration

Lack of registration occurs either because of mask alignment errors or cumulative errors in the step-and-repeat process. It can lead to altered device configurations. Here, too, defective circuits can result in extreme cases. In some situations, misregistration may result in exposing a projected junction edge, thus degrading its characteristics.

Registration problems have become increasingly important for high-density VLSI structures and large wafer sizes. At present a misalignment error of about 0.25 mm is generally achieved in printing systems operating at the 1-mm level.

Pinholes

Pinholes may be present in the resist and result in the inadvertent opening of a small window in the underlying mask film. Their effect is a function of their specific location. The severity of this problem increases with component packing density.

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Dust Particles

Dust particles present a serious problem during the delineation of patterns in mask films. Some dust, such as carbon or metallic particles, is opaque, and its presence on the clear parts of a mask will prevent exposure of the underlying resist. This will cause holes in a negative resist after exposure and development, and consequently, holes in the mask film. The effect with positive resists is to not completely clear an opening in the underlying mask. This latter effect is usually less serious than the former.

Most dust particles are transparent and cause diffraction effects, having the same effect as opaque particles; often, however, the effect covers a wider area due to the diffraction pattern. In either case, the problems of dust are minimized by the use of good clean-room techniques and by careful visual inspection of the masks prior to alignment and exposure.

Scratches and Tears

The printing of metallization patterns is a particularly difficult task because of the delicate nature of the film. Here scratches are by far the most common type of defect.

Scratches greatly increase the current density in their vicinity, giving rise to the formation of hot spots and the premature onset of electromigration. Thus, although the circuit operation is unchanged, its reliability may be greatly impaired in this manner. In extreme cases, scratches result in defective circuits by breaking the metallization path.

Tearing of the metallization may occur during the removal of the photoresist. This is often due to dimensional changes and damage to the photoresist during the alloying step. This defect also reduces the effective area of the current path or produces an open circuit in extreme cases. The two-level lift-off technique is extremely important in controlling this problem.

Step Coverage

Step coverage problems can occur when an excessively thin layer of resist goes over a step in an oxide, giving rise to a failure of the resist during the subsequent etching process. The problem is especially severe with negative resists, since they are applied in much thinner layers than positive resists. Here, too, the use of two (or more) levels of resist can alleviate this problem.

Problems of step coverage can also be reduced by the use of planarization techniques as covered earlier.

Effect of Printing Techniques

All photomask anomalies do not necessarily become mask defects. The type of defect produced, its proximity to the circuitry, field polarity, size, and the

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reproduction technology employed determine a defect's final significance. An ongoing evaluation of mask defects and their causes is essential to improve yield.

Increasing use of stepper and projection printing technology furnishes several benefits. The 10× reduction employed in earlier systems effectively rendered many defects invisible by the simple expedient of reduction.

The 5× systems also enjoy this benefit, but to a lesser extent. However, 1× systems offer little opportunity for defect reduction. The reticles, however, are generally produced with much greater care to avoid repeating defects and are usually protected by pellicles.

Steppers eliminate the contact between master (reticle) and wafer, and thus the problems of resist pulling and reformation. Particulate transfer from mask to wafer also disappears. Defects occurring on stepper reticles become repeating defects, howevera decidedly negative aspect.

Stepping also furnishes an incidental side benefit through the use of resist developers containing sodium. These developers tend to produce higher resolution images on the mask and can be employed where there is no contact between mask and wafer.

Different types and sizes of mask defects have demonstrably different effects on the reliability and yield when transferred to the die (Fig. 11.4). In 3-mm projection alignment with positive photoresist, the system is sensitive to nearly all types of defects except pin dots.

Two-micrometer stepper technology (Fig. 11.5) with positive resist is not

Figure 11.4
In 3-mm projection, alignment system is
sensitive to nearly all types of defects except
pindots [2].

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Figure 11.5
Nicks cause problems in 2-mm stepper
technology with positive resist [2].

seriously affected by any defects except nicks, which can cause serious electrical problems.

Etch

Etch relies on the use of corrosive chemicals, such as bromine and iodine, due to self side-wall passivation and increased selectivity. For metallization with greater than 12% Cu, the nonvolatile copper leaves residues when etched with HBr, Br₂, HI, or I₂. If wafers are not properly cleaned and rinsed following etch, residue contaminants can be left on the wafer surfaces, leading to device degradation and finally to corrosion resulting in catastrophic failure. The etch equipment must be thoroughly cleaned as well, since the corrosive etchants can both contaminate the reactor chamber, leading to wafer contamination, and eat the reactor components themselves. Low-pressure plasma etchers are used to reduce etch damage.

Dry Processing

The use of dry processing techniques (gas plasma or ions) in lieu of wet (chemical) processing is increasing rapidly because of the elimination of many deleterious contamination- and fabrication-related problems. However, the gas plasma technique is not without its own set of problems: radiation damage and other problems caused by the plasma itself. Radiation damage induced by early dry-processing plasma systems has several effects. Dielectric breakdown caused by electrostatic discharge and sputtering contamination from chamber materials

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are potential hazards. Threshold shifts on transistors are among the undersired results.

Newer methods of dry, plasma-based wafer-processing system strippers, chemical vapor deposition systems, and even etchers using remote plasma processing have been developed. Rather than creating the volatile plasma in the process chamber and subjecting the delicate wafer to ion bombardment and other hazards, the new methodology generates the plasma in an upstream location. Then the plasma's less caustic afterglow, consisting of gases in a less excited state, can do the stripping, etching, or deposition.

Etching, however, presents a formidable challenge because of the demands for smaller and smaller feature sizes and such difficult-to-etch features as trenched capacitors. Controlling the free radical gas molecules in an afterglow system will be a different task.

In submicrometer technology all defects must be analyzed on the basis of their size, location, and ability to reproduce.

High-Temperature Processes*

High-temperature diffusion, chemical vapor deposition (CVD), and metal deposition are the steps at which wafers are most susceptible to process contamination.

Diffusion

For diffusion, the two common forms of n- and p-type dopant are deposited at the silicon oxide surface as P₂O₅ and as B₂O₃. Although both can be deposited from either gases, solids, or liquids, the results differ depending upon the source. For example, the gas system phosphine (PH₃) and the liquid system phosphorus oxychloride (POCl₃) produce different by-products:

(1)

(2)

Both reactions produce P₂O₅, which deposits on the wafer surface. The phosphine reaction (Eq. 1) generates three molecules of water, which can accelerate oxidation of the exposed wafer surface, thus interfering with doping uniformity.

Conversely, the liquid POCI₃ (Eq. 2), which produces no water, generates chlorine (Cl₂) which can act as a getter for noble metals and sodium.

Another liquid phosphorus source, phosphorus tribromide (PBr₃), is also used to generate P₂O₅. In this system, the chemical reaction is:

*Portions of this section used with permission from Ref. 3.

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(3)

As a result of its generation of Br₂, this liquid dopant exhibits high alkali and noble metal gettering efficiency. It can also provide tight control of sheet resistance, and produces low surface damage.

Because of its high density and low, flat vapor-pressure curve, PBr₃ provides good mass flow control for precise doping levels. A similar comparison can be made between the gas diborane and liquid boron tribromide:

(4)

(5)

Again, since BBr₃ (like PBr₃) is a halogenated molecule, it exhibits superior gettering properties. And, like PBr₃, it can achieve uniform high concentration with low surface damage.

The concerns for safety when using the gases phosphine and diborane are well known. Liquid sources, by comparison, are much less hazardous.

Boron trichloride (BCl₃) is also used as a dopant source. Because it is handled as a liquid under pressure, it is shipped in steel cylinders that contribute to the uncertainty concerning its purity, because of possible metallic contamination from the cylinder. The chemical reaction for BCl₃ is

(6)

In this reaction Cl₂ is available as a getter. However, temperature control is more difficult than it is for BBr₃, resulting in reduced process stability. Moreover, the oxidation rate of BCl₃ is slower than that of BBr₃, with resulting reduced uniformity across the wafer boat. To overcome this problem some process engineers introduce hydrogen with the oxygen to produce water, thereby accelerating the BCl₃ reaction. It is believed that in this particular situation, the HCl that is generated could produce unwanted effects on the doped wafer surfaces.

Compared with liquids and gases, solid diffusion sources exhibit some process control disadvantages. In planar sources, these disadvantages may include a general inability to backside getter, possible formation of undesirable compounds and silicides on the wafer surface, nonuniformity, and variability as a function of time as the source becomes depleted. When solid sources are employed to produce burried layers, the use of high-purity Sb₂O₃ is recommended.

The purity of a material such as a dopant source is a major consideration in process control and the realization of high device yield. Contamination from material containers or plumbing will result in degradation of the glass or dopant source. Metals picked up in the delivery system will be deposited on the wafer, where they diffuse to deteriorate carrier lifetimes and device uniformity. They

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can also catalyze reactions that result in nonuniform electrical properties and the nonuniform growth of glass films.

Water acquired in the delivery system can also react with the source material to form acids, whose presence produces variable reaction rates and variations in sheet resistance. Water in the glass source material creates the additional problem of causing wafer-to-wafer variation in glass thickness. In the case of tetroethoxysilane (TEOS), water reacts with the material to form by-products that cause nonuniform film growth.

The material source should be specified in terms of percent of available pure dopant and metals content. To guarantee its integrity, it should be packaged hermetically in an inert container such as quartz, and should be used in an inert, clean, and leak-tight delivery system, using Teflon valves isolated from the source materials by quartz breakseals, for example.

A furnace tube used for CVD should be cleaned periodically to assure process integrity. This cleaning operation is particularly important for low-resistivity doping or gate oxide processes.

Rapid Thermal Processing

Rapid thermal processing (RTP) is a method used for both silicon and GaAs technologies that uniformly heats and cools wafers in seconds. Since the process heats the whole wafer, the heating and cooling are limited by the thermal mass of the wafer and the heat transfer mechanism operating on the wafer. RTP is accomplished by heating a wafer up to 8001200°C in 34 s, holding the set temperature for 110 s, then allowing the wafer to cool. The RTP process is fast and minimizes dopant diffusion, thus allowing shallower junction depth, which leads to faster device speeds.

The main reason for using RTP is to obtain improved dopant activation of implanted layers (due to the high wafer temperatures used) while minimizing dopant redistribution (due to short processing times at high temperatures). This unique combination of high activation temperature and short processing time provides a degree of control over the thermal processing of wafers not available with standard diffusion furnaces, and thus allows full activation of the dopant introduced by ion implantation without junction motion. Additionally, aluminum contact alloying using RTP sintering produces contact resistances comparable to furnace-alloyed contacts with the total elimination of hillocks and a 50% reduction in spiking.

Because of this improved level of contact over implant activation and dopant redistribution, several other important RTP applications include implant damage repair, PSG (glass reflow), silicide and salicide formation and processing, enhanced diffusion, polysilicon processing-polysilicon annealing, and drive-in doping from polysilicon for gate interconnects and resistors and for controlled diffusion, contact sintering, film growth, and thin oxide formation.

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RTP has been adopted at a faster pace for GaAs wafers than it has for silicon wafers because of the electrical and physical instability of GaAs materials at high temperatures, the need for sharply defined impurity profiles, high peak electron mobility, and the complex stoichiometric processes inherent in the formation of ohmic contacts.

The principal applications of RTP in GaAs device processing are implant activation and ohmic contact alloying.

One of the requirements in the production of GaAs ICs, especially MESFETs, is the need to limit the outdiffusion and redistribution of impurities in the GaAs semi-insulating substrate, which leads to undesirable shifts in carrier concentrations in the active layers. Transient annealing, with its greatly reduced steady-state elevated temperature periods, has produced very high carrier concentrations without significant out-diffusion of implanted dopants and substrate thermal conversion.

The greatest advantage of RTP over furnace annealing with regard to active layer formation is that RTP produces higher activation and mobilities, as well as tighter spreads in carrier profiles. These result in much higher device transconductance as well as higher and more uniform gateless FET transistor saturation currents.

In addition, GaAs capping technology can affect the percentage of activation of implanted impurities such as Si, which is used as an n-type dopant. Device fabrication experience has shown that rapid thermal annealing (RTA) allows more latitude in capping processes than furnace annealing with respect to obtaining high activation.

One of the primary problems all GaAs IC suppliers must contend with is the lack of uniformity and standardization of the substrate materials provided by vendors, which results in electrical characteristic variation from lot to lot. RTP is used to adjust pinch-off voltage on a lot-by-lot basis.

In the production of GaAs ohmic contacts, RTP results in better contact morphology and lower resistance than furnace processing. Rapid thermal alloying is capable of producing smooth postalloy surfaces at the source/drain contacts, allowing for excellent gate definition during lithography. The second-by-second control afforded by RTP allows for extremely accurate control of the ohmic contact formation process, which is quite complex in GaAs devices.

By its nature, high-temperature processing poses problems of slip and arsenic outgasing and places some stringent requirements on both the heat source and control system:

1. The energy must be uniformly applied to the surface of the wafer.

2. Each wafer must be properly supported such that uniformity of heating or conduction of heat from the wafer will occur.

3. The temperature of each wafer must be accurately controlled.

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4. The environment of each wafer must be controlled to prevent contamination of the wafer surface (each process requires its own particular gas environment).

Slip is probably the most important single issue of concern to device suppliers who use RTP. Slip is caused by wafer temperature nonuniformity, plastic deformation of the wafer, and/or oxygen concentration in the wafer. The primary task of IC suppliers is to find ways to first baseline and then compensate for the varying stresses on a wafer during thermal processing, which gets worse as the wafer size increases. The problemcommonly attributed to stress created by fast rampingis complex and involves the interplay of at least three elements: the intrinsic stress in the material as delivered by the producers of bulk silicon and GaAs; the stress created by the various layers applied to the wafer during fabrication (silicon dioxide and silicon nitride capping layers inherently create stresses of their own and must be counterbalanced with stresses created in the substratethe same can be said for passivation layers); and the ramping rate during the temperature excursion.

While most RTP equipment manufacturers concentrate on providing the fastest ramping speed possible for high-temperature silicon processing applications, GaAs device producers require much slower ramping rates to reduce slip in GaAs substrates. Good temperature control is required at heating and cooling rates as slow as 5°C/s. Obtaining the required temperature control in a rapid thermal processing heating chamber where there is no thermal equilibrium between the heating source, the quartzware, and the wafer is difficult to achieve.

For the temperatures of interest in RTP, radiation heat transfer dominates all other heat transfer mechanisms. As such, temperature measurement is one of the thorniest issues surrounding the use of RTP for IC processing. Temperature measurement of the wafer is generally done by using thermocouples or optical pyrometry, both of which can cause inaccurate reading if not properly compensated. Research has shown that current methods of measuring silicon wafer temperature are not accurate enough for GaAs processing needs. The difficulty of obtaining consistently accurate temperature measurements is compounded by the variations in substrate materials available to device suppliers. Rapid processors developed for GaAs production must therefore provide a thermocouple option or a pyrometer specifically designed for accurate GaAs temperature measurement in the 350975°C range.

Wafer temperature uniformity is very important if good device yields are to be obtained. Sheet resistivity uniformity, oxide thickness, and diode leakage current have been used to measure uniformity, and to date no fully satisfactory temperature uniformity tool exists.

When subjected to high temperatures, about 800°C, GaAs wafers outgas arsenic, thus changing the electrical properties of the surface region. This problem

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can be avoided by covering the wafer surface with a dense cap such as Si₃N₄ or by annealing in an arsenic overpressure environment. Capped annealing is the only effective approach that can be used in conjunction with RTP, because outgassed arsenic quickly permeates the quartzware and/or lamps used in rapid thermal processors. With arsenic coating the heating source and/or quartzware, light emission is reduced and becomes nonuniform, thus leading to poor repeatibility.

GaAs wafers will sag if not fully supported. IC suppliers need to balance the requirement for minimal-contact support points inside the heating chamber (to reduce slip and increase temperature uniformity) with the need to provide sufficient center support to prevent sagging.

Because of its fragility, GaAs material must be handled with extreme delicacy. Wafer handling and transport systems for automation must be very gentle and nonabrasive. A vacuum-assisted robot is ideal for transporting wafers to and from the processing chamber.

There are three types of contamination that emanate from diffusion and RTP equipment: heavy metal ions, hydrocarbons, and unwanted active gases in the heating environment.

Sources of metal ions may include the heating source itself (lamp filament, electrode, graphite heating strip, etc.) and the exposed metals inside the heating chamber (iron, gold, chrome, copper, etc.). Metal ion contamination can be reduced significantly by placing the wafer in a quartz envelope or tube. Care must be taken, however, to keep this tube cool. Above 900°C, quartz becomes transparent to metal ions, which can then travel through it with great ease. A tube cooling system can be used to carry away residual heat that is normally transferred from the processed wafers to the quartz tube. Protection from metal ion contamination can be achieved by cold-wall processing.

In most systems, contamination caused by wafer handling is reduced through the use of cassette-to-cassette processing. Quartz contact surfaces and vacuum-assisted transport are also incorporated into most products on the market.

Active gas contamination must be dealt with by clearing the heating chamber of these gases. Manufacturers use purge gas systems to flush the heating chamber and maintain an overpressure during the heat cycle. Stainless-steel tubing and adequate filters should be included to eliminate purge gas as a contamination source.

Recent process development research points to the benefits of providing gas access to the heating chamber and a hermetically sealed quartz isolation tube. Processes such as oxidation, nitridation, and glass reflow take advantage of gas-handling systems to deliver forming gas, steam, and reactive gases to the heating environment.

Lasers, electron beams, flashlamps, and arc lamps have been used for rapid thermal processing. For production applications RTP machines must also

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demonstrate process uniformity and reproducibility (e.g., wafer temperature uniformity across the wafer). The type of thermal processor that has been successfully used for semiconductors consists of (1) single or multiple heat sources that couple heat uniformly, usually by radiation, to the low thermal mass wafer, (2) a low thermal mass method for holding the wafer, (3) a method for transporting the wafer in and out of the processor, and (4) a controlled environment to allow wafer cooling.

Oxide Defects

The quality and integrity of the oxide layer are important for the proper functioning of ICs. They are especially critical for the functioning of MOS ICs in which the majority of elemental device (transistor) operation occurs in this layer. In fact, the majority of MOS IC failures are due to oxide defects (breakdown of oxide; charge trapping and hot electron effects due to ionic contamination and threshold shiftsthis is discussed in depth in Part IV). Thus the purity (lack of contamination) of the oxide must be carefully controlled.

Figure 11.6 shows the variation of the defect density (resulting in short circuits) with the oxide deposition method used. In this case a two-level metal sandwich consisting of 2000 Å of titanium-tungsten on top of 7500 Å of aluminum-copper was sputtered over three different oxides: a thermally grown field oxide, a plasma-enhanced chemical vapor deposition oxide, and a double deposition that included a spacer etch before the second oxide deposition.

Figure 11.6
Variation of defect density with oxide deposition method
used and feature size.

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The density of metal shorts shows a surprising increase of about a factor of three across all feature sizes, caused by the presence of deposited oxide below the metal. For example, the multistep oxide process has a much higher defect density than thermal oxide of plasma-enhanced CVD oxide.

Furthermore, measurements of the defect sources of the metal over thermal oxide revealed that the percentage of lithographic defects is small while contaminant particles introduced during processing predominate, as is shown in Fig. 11.7.

Epitaxial Layers

There are several places in the epitaxial deposition process where manufacturing faults can occur. Especially important to the epitaxial process are cleanliness, deposition temperature, film quality, and process control.

Extremely clean wafer surfaces and contamination-free systems are necessary in achieving high-quality epitaxial films. Surface problems such as particles, haze, stains, and crystal irregularities could cause device failures. Particles and stains stem primarily from poor wafer cleaning and system housekeeping. Also, particular care must be taken during spin-rinse-drying steps to insure that particulates resulting from the wafers shaving the Teflon boats do not get on

Figure 11.7
Listing of defect sources in multilevel metal
structure resulting in interlevel shorts.

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the wafers. Haze, which may arise from a number of sources associated with growth rate, results primarily from oxygen leaks in the system. Small amounts from the tiniest leak can cause major surface disruption.

Surface contamination due to electrostatic attraction of particles and gravity effects has posed a major problem to IC suppliers. Traditional ways of eliminating these sources of contamination have been to search out and eliminate the sources of particles in the fabrication equipment, and the use of ionization systems, which produce streams of negative and positive ions that ultimately combine with free ions to reduce static. Another method uses infrared lamps in conjunction with the vertical orientation of wafers to reduce static attraction of particulate contaminants prior to deposition to produce ultralow-defect epitaxy layers.

Deposition temperature influences the deposition (or film growth) rate, the formulation of crystal defects, energy consumption, and autodoping. Any dopant from either the wafer itself or a diffused region will out diffuse during epitaxy growth and will recombine in the growing epitaxy layer, changing its resistivity. Thus, the epitaxy thickness and the doping level (resistivity) are critical device parameters.

Growth rate is critical in the maintenance of single-crystal growth and the prevention of pattern shift. If the growth rate is too fast (due to high temperature, for example) the epitaxy will grow at an angle to the wafer surface. The lowest temperature consistent with other film requirements is most desirable.

Crystal irregularities are due to poor surface cleaning or poorly defined growth rates. A highly accelerated growth over wafer surface spots, which results in film surface spikes, is the most common irregularity. These spikes can grow to several times the film thickness.

Other crystal defects are slip of the crystal planes and stacking faults. Slips are hairline crystalline shear-displacement defects that usually form at the edge of a wafer as a result of thermal gradients. IC suppliers try to direct large amounts of energy toward the edges of the wafer to compensate for edge loss. A poor or dirty wafer surface can cause a stacking fault to occur. A stacking fault is a disruption of the crystal that originates at the wafer surface, resulting in triangular-shaped faults in (111) wafers and rectangular faults in (100) wafers.

Thus, aside from any equipment-induced film-growth problems, the condition of the substrate and its surface prior to film growth, as well as dopant-source material purity and mass flow control, are key factors in determining film quality. Using high-purity materials, pre-epitaxy etching and cleaning are critical, as is a pure, precise, oxygen-free growth/doping delivery system.

Metallization

Step coverage can be enhanced by depositing aluminum or aluminum-silicon in a series of thin layers (20 nm or less thick), and allowing time for surface diffusion

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to take place between layer depositions. The time needed for diffusion decreases with increasing substrate temperature. Figure 11.8 shows the step-coverage profiles observed at several deposition temperatures. It is apparent that although the profile becomes smoother at higher temperature, step coverage can actually be degraded by too high a temperature. The optimum temperature, which is dependent on the particular step topography, would be determined as part of the process characterization.

Sputtering

The mechanical configuration of a sputtering system, including its maintainability, must be considered in the context of the total fabrication process. The wafer-handling architecture is important, since the manner in which wafers are handled, transported, and held during processing affects the mechanical complexity of the system. A less complex system is inherently more reliable, requires less frequent maintenance, and generates less particulate contamination. Wafers should not slide or rotate on surfaces that could produce particles, must not be touched or handled on their active circuit face, andpreferablyshould be removed from and returned to a Semiconductor Equipment and Materials Institute (SEMI) standard cassette so that wafer transfer to special cassettes is not required. The rationale here is that any wafer motion or handling comprises a potential source of particulate contamination, and must therefore be minimized.

The spatial orientation of the sputtering processup, down, or sidewaysin a clean, well-maintained system is normally irrelevant, because charged, micrometer-sized particles are directed by electricnot gravitationalfields. However, because some processes, such as a dedicated titanium-tungsten deposition, may produce large flakes, they should be performed in a vertical wafer orientation system. Other processes, such as aluminum alloy deposition, produce very adherent films, and sputter down is preferred because of its mechanical simplicity. Even a Ti-W-Al process can be performed in a sputter-down system if the Ti-W film is overcoated with Al after each deposition cycle.

The choice of pumping systems for sputtering is particularly important in aluminum-silicon deposition. A glow discharge comprises a chemical factory that converts an inocuous gas such as water vapor into hydrogen and oxygenwhich are known to degrade A1-Si films by causing hillock growth, increased resistivity, and increased film hardness. Hardness causes problems in automatic lead bonding. Even a low (e.g., 2 × 10⁻⁷ torr) partial pressure of nitrogen from tiny real or virtual leaks can result in cloudy films, increased chance of microcracking, and degraded step coverage.

Transport of wafers into and out of the process chamber must be accomplished in such a manner that the process gas quality is not degraded during deposition by injection of atmospheric gases from the loadlock. In this sense, batch processing facilitates maintenance of the highest vacuum integrity, because

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Figure 11.8
Typical sputtered-film step-coverage profiles for
films deposited at (a) low, (b) medium, and (c)
high temperature, achieved during multipass,
pulsed deposition, illustrating the effects of
surface diffusion.

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no processing takes place during wafer batch transfer, and recovery to a high-vacuum condition can be accomplished before the next deposition cycle begins.

Defects that occur during the metal deposition processing (sputtering) step must be prevented because most of the value has already been added to the wafers (and thus the die)the wafers are in the final stages of their processing. The primary method used to prevent such defects from reaching unacceptable levels is to monitor particle levels during metallization so that when the particle levels become excessive, processing can be stopped and the chamber cleaned. An example of this particle monitoring is shown in Fig. 11.9. Reference 5 discusses this in greater detail.

Planarization

In multilevel VLSI circuits CVD oxides are most often used for the interlayer dielectric. However, these oxides provide a conformal coating over the underlying topography that results in an even more rugged surface on top of the oxide. It is over this CVD oxide that the second-layer metals must be

Figure 11.9
(a) Load-lock particle data; (b) sputter chamber particle data.

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deposited, and step coverage then becomes a significant problem. If the top surface of the CVD oxide can be made more planar (see Planarization and Typical Metallization System in Chapters 2 and 6), the second-layer metal thickness uniformity and integrity is significantly improved, resulting in higher yields and improved device reliability. Spin-on-glass films are one means used for planarizing the interlayer dielectrics.

There are two basic spin-on-glass (SOG) processes. The first uses a sacrificial layer in an etch-back process instead of photoresist. The advantage is that it etches with the same dry etch gases as the CVD oxide, which results in higher throughput rates compared to a photoresist erosion process using a mix of O₂ and CF₄. The second process uses an SOG film in combination with a CVD oxide. The SOG film is applied either under the CVD film or on top of it. In both cases, the result is a smooth dielectric surface over which the second-layer metal can be deposited.

However, there are some problems. Particles are a severe problem in SOG processing due to the nature of the material. The SOG solution goes through catalytic reaction to form SiO₂, which, once formed, is no longer soluble in the carrier solvent. As a result, large numbers of SiO₂ crystals form in the process cup and, if not properly cleared away, tend to build up and redeposit on wafers in process. Also, process control and repeatability are critical to a successful SOG process.

Thermal processing is also critical to insure proper film characteristics. While the first SOG films were baked in batch convection ovens and diffusion tubes, current techniques make use of high-precision cassette-to-cassette hotplate oven modules that provide uniform wafer heating from the substrate outward. The totally enclosed oven module provides controlled baking ambients, specifically nitrogen, that are critical for proper film processing.

Ion Implantation

Control of the dopant distribution in an IC fabricated with ion implantation requires addressing issues such as ion channeling, dopant uniformity control across a wafer (on a micrometer scale), and shadowing (which can occur at the edges of implanted areas due to abnormal beam incidence angles on patterning layers with high-aspect ratios).

Addressing dopant distribution, manufacturers of ion implanters have incorporated features such as wafer orienters that achieve a desired crystal azimuthal angle control of planar channeling on low- to medium-dose implants. They have also improved electrostatic scanning to interlace scan patterns and to eliminate nonlinearity with scan waveforms.

Channeling can also be controlled through preamorphitizing the surface with silicon or germanium implants. This disrupts the order in the silicon crystal

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lattice, thus randomizing the trajectory of the incoming ions as they are implanted and eliminating any excessively deep distribution of channeled ions.

A major emphasis with ion implantation is the control of contamination from particles and the prevention of damage from wafer surface charging. With ion implantation, particles affect the ultimate functionality of an IC when they mask the area of the circuit where they lie during the implant process. For example, a particle diameter of 1 mm is 10 times wider than the range (penetrating depth) of some implants.

Particle control in ion implantation is closely related to process conditions such as the use of resist. Finding the source of particles in an ion implanter is a major effort. One has to look everywhere for the sources of particles and reduce or eliminate them one by one; there is no single source. Much of the attention of implanter manufacturers has been directed at improvements in the design of the implant chamber and wafer handling to eliminate sources and redistribution of particles.

It has been found that air turbulence at the surface of the wafer, even when loading in HEPA-filtered air, is a significant source of particles (other sources are due to electrostatics and direct contact). Thus, loading in a vacuum eliminates one whole contamination mechanismparticle contamination due to turbulence.

Another feature that addresses particle control is the addition of clampless wafer handling to ion implanters. Clamping is done on a flat pedestal that creates surface forces between the wafer and the mounting fixture.

By eliminating the conventional use of clamps on the front surface of the wafers, more wafer surface area is exposed to the ion beam, clamping-induced particles are eliminated, and wafer stress is reduced. Channeling and shadowing are also significantly reduced; the flat surface of the pedestal presents a wafer with a constant implant angle to the ion beam.

Conventional methods of clamping wafers over a domed heat sink have proven to be a source of silicon and photoresist particles during the clamping process, as well as a source of cross-contamination of the wafer by sputtering from the clamps. In addition, conventional clamping increases the chance for scan-angle errors and nonuniform implants as larger diameter wafers are implanted.

Damage from surface charging during ion implantation can reduce yields as IC dimensions and thin film thicknesses decrease; wafer-surface voltages caused by a charge buildup from the ion beam can easily become high enough to cause damage. This will likely become a problem with all equipment that uses plasma. In addition, a charge buildup may produce a degradation in implant uniformity as a result of a complex interaction between the surface charge on the wafer, the space charge on the wafer, and the space charge of the beam.

Advanced ion implanters neutralize this positive surface charge by spraying the wafers with electrons (negative charges).

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Equipment Contamination

From a processing point of view, particles below 1 mm tend to react with wafers rather than merely settling upon them; both chemical and electrochemical adhesive forces come into play. Conventional methods of cleaning, for example, degreasing and washing, no longer work well. New methods are needed.

In addition, both the source and type of contaminants are changing. Previously, people were the dominant source of contamination (biological origin). Today, bunny suits and wafer transport systems have largely removed these human sources of contaminants. The biological contaminants have been replaced with metal elements, metallic compounds, and plastics; process equipment is the main source of this contamination.

Equipment contamination is one of the most critical sources of defects as shown by the Pareto chart of Fig. 11.10, in which various sources of particulates are compared. Manufacturers are being instructed to build wafer processing equipment in a clean room, despite the fact that the atmosphere in which the equipment is manufactured is not the problem. The mere insertion of a #10 bolt into a nut creates 10,000 micrometer-sized particles. Even routine cleaning in a facility can generate more particles than are cleaned. In order to reduce particulate contamination, process equipment must be redesigned and new improved materials used. For example, the use of Tuffram fasteners and bearings

Figure 11.10
Front-end particulate analysis. (Courtesy of Texas Instruments,
Dallas, Texas.)

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(General Magnaplate, Linden, NJ) has been reported to substantially reduce particulate generation. Tuffram is produced by expanding the pores of aluminum and injecting a fluoropolymer, which causes the aluminum to act as a self-lubricant.

The semiconductor industry has worked to clean up all sources of contamination (especially people and the clean-room environment) such that process equipment is currently the major source of contamination. What has been accomplished (on a large scale) is building clean rooms around people. This must change. A clean environment must be built on a smaller scalearound the wafers themselves in all process and transport stages in order to supply VLSI and ULSI circuits.

Most process equipment is available with cassette-to-cassette handling. Thus the object actually handled by an operator is a cassettethe equipment handles the individual wafers.

The trend in process equipment is toward stand-alone automation; which takes complete control of the wafers through that process step. This trend is also reducing operators in a manual fabrication to the level of human automatons carrying product from one place to another.

With the increased dual requirement for higher-level-of-cleanliness clean rooms and automating the wafer fabrication process, equipment contamination and contamination control is a major issue. The very process of automation has added to equipment contamination problems that must be addressed. The next section does just that.

Wafer Processing Automation

Densely packed VLSI and ULSI submicrometer devices require tighter lithography rules for packing more features closer together, as well as much lower levels of contamination and defects, in both the materials and the processes used.

Only through automation can these critical means of increasing productivity be implemented effectively. Larger wafers are not only difficult to handle manually without damage, but, because of their high circuit densities, are more prone to the impact of contamination; for both reasons, machines are better suited to handle them.

Thus, IC suppliers will have to rely more heavily on computer-integrated manufacturing (CIM) technology for design, fabrication, assembly, and test operations than ever before. Highly, if not totally, automated production is necessary to maintain the levels of cleanliness for submicrometer geometries and to provide the attendant process monitoring and control for an industry that is very dependent on sophisticated chemical and physical technologies. Process

*Portions of this section used with permission from Ref. 6.

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consistency and repeatability become more essential than ever. Only computer-controlled machines can provide the accuracy needed in these increasingly time/temperature/pressure-sensitive processes. Semiconductor production equipment typically is not making product two-thirds of the time. An automated system, which never takes breaks or changes shifts, can significantly increase equipment utilization time. A continuous load/unload sequence can eliminate repeated setup time. Throughput also increases because automated product queueing systems will mean product will be running a high percentage of the time, and more will always be ready to run.

Automation can reduce process cycle timethe time in which a product sits waiting for the next process stepby automatically routing the product to the next step and eliminating returns to the control room between steps. This raises yields by reducing the idle time during which wafers can collect defects. And fewer idle wafers mean lower inventories and thus a lower direct cost of processing the wafer.

The term automation means something different to almost everyone who uses it. Too often its meaning is limited to mechanized product and materials handling systems with cassette-feed and robotics components (Fig. 11.11). Today a typical wafer casette is automatically loaded, processed, and unloaded, but this alone is not automation. Nor should automation be viewed as the hardware interconnection of everything in the factory.

Rather, an automated facility can be defined as an integrated system of a number of subsystems, not only mechanized movement systems but information systems, logistics systems, process control systems, and people, all linked via a computer system that forms its backbone and base.

The fundamental backbone itself is a set of software applications that run various aspects of the manufacturing process. This system exists both internal and external to individual pieces of process equipment. The computer inside each piece of equipment controls the mechanical as well as the electrical and process parameters, and the sequencing of events. The programs associated with these activities are usually incorporated in the equipment at the time it is purchased.

But computers within individual pieces of equipment must talk to other computers, continuously communicating data on machine status, the product being processed, process parameter levels, and so on. And above that level, manufacturers typically provide application-specific programs that handle tasks defined by the user. All of the programs in this hierarchical software system must ultimately work together in an integrated fashion.

The computer system oversees a variety of activities internal and external to the various pieces of equipment. Automatic process control, an internal function, is a critical yet often overlooked area. In the past, an operator has manually set the parameters (e.g., amount of time, temperature, pressure, etc., at which a product is processed) using dials or switches; this can be done far

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Figure 11.11
Automated (robot-operated) wet station. Robot transfers loads of silicon wafers in and out of acid
baths. (Reprinted by Permission of Intel Corporation, copyright 1986. Photograph by Chuck
O'Rear.)

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more reliably and consistently by computer. Today automatic parameter setup is used almost exclusively.

Closed-loop automatic control is another area that is needed, and its use is increasing. If one parameter settingsay temperaturestarts to drift, the computer can automatically adjust for it and generate a warning signal; a human operator might never notice the drifting parameter. Ideally, all the operator should have to do is tell the machine which product it is processing; the computer then selects the correct recipethe combination and sequence of all its parametersand produces a higher-quality process in less time. It does the same thing the same way every time. Repeatability and consistency are achieved, which results in higher yields.

Outside of the individual tools there are logistic systems that keep track of the product location at all times. Increased implementation of the robotic cassette movers is expected to tie tooling systems together. The key to a successful logistics system will be the computer with a master recipe carefully controlling product routing; without this, automated logistics systems will not work.

A company's people and its culture play a vital role in automation. Elements of this culture include the amount of emphasis placed on continually improving yield (at what cost), and the means of implementing such improvements, even the way wafers are processed (singly versus in batches). The compatibility of a new automation system with the company's traditional definition of its people's role in the manufacturing operation will be a key determinant of how well that system will fit in; at an early stage it should be determined how much product will be handled by people, what processing materials (photomasks, photoresist batches, etc.) will be handled by people, what is the operator's role in diagnosing problems, how much control the operator will have to override the computer, whether the machines should be able to run manually, and the like.

Then there is IC design, almost always overlooked as a factor in fab automation. The objective is to design the product to fit within the center of a variable process window, so it can be manufactured reliably and repeatably by the automated system. For example, if a given process runs at a temperature range of 11001500°C, and the product being processed is running in the range of 10501100°C, high yields cannot be expected. Designing the product for a 11201130°C range places it at the middle of the process window, allowing some leeway to take advantage of the automation system's inherent consistency and repeatability.

The ultimate goal of automation is the creation of groups of integrated sectors (e.g., photolithography, diffusion, chemical vapor deposition, ion implantation, metallization, etc.), each incorporating all of the elements just discussed. It is important to recognize, however, that automation does not happen all at once.

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Increased automation offers many advantages, some of which are peculiar to the very delicate and expensive process of wafer fabrication. Among the most prominent are:

1. Reduced contamination. Until recently, workers have been one of the primary sources of particulates in clean-room environments where wafers are processed, accounting for 25% of the contamination that negatively affects processed wafers. The obvious solution to this problem is to remove people from processing areas, and reduce the number of people entering the clean-room processing areas, by switching to robot handling and mechanized wafer transport systems. Although the robotic and automated transport equipment is not yet totally free of contamination, it already is much lower than the contamination generated by workers, and the Japanese suppliers are leading the way in adopting the use of this equipment.

The majority of the other 75% of the contaminants come directly from the process environmentthe machines/processes themselves. Once operator handling of products has been eliminated, two other factors must be considered.

First is air quality of the wafer path itself. The wafer path should be Class 1 or better, and should be effectively enclosed within the tool, to maintain the integrity of the air quality as established at the outset.

Second, since it is the machine/process (and not the clean-room environment) that generates most of the contamination, the objective is to reduce particulates on the wafer, thus reducing defects, increasing yields, and improving reliability. Killer defects are created by particles running half the size of the smallest feature; basic reliability is affected by particles larger than one-tenth of that feature size. The machine/process must be optimized to virtually eliminate contamination. The targets should be guaranteed to contain no more than 0.01 particles per square centimeter, and no particles at all larger than 0.1 mm. The equipment industry has a long way to go to achieve these numbers. Without an all-out cooperative effort between equipment manufacturers and users, low yield limits will be negated by contamination. It has been estimated that 50% reductions in defect levels are readily achievable with automated equipment, resulting in process yield improvement of 10%.

2. Eliminating operator product handling. For efficiency and minimization of defects, it is important that direct operator handling of products be eliminated. The development of two industry standards, one for cassettes and one for cassette carriers, has made this possible by minimizing wafer transfers between nonstandard carriers.

Cassettes are made of different materials such as PTFE, Teflon, aluminum, quartz, and so on, with different machines accommodating/requiring different cassette designs. A number of standards in cassette shape and size have been

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established; the user should make sure the prospective supplier supports the standards the operation requires.

The key to increasing yields on VLSI devices hinges on the cleanliness of wafer transport. Numerous robotic configurations can be used for the transport operation, provided that they are designed for low particle emission or effective particulate containment as well as for meeting requirements of speed, accuracy, machine layout compatability, and cost.

In addition, automated storage of transient wafers or wafer lots should be provided in the line so that the operator need not handle the product during instances of equipment failure.

3. Less breakage. The trend to larger wafers requires consistent automated handling to minimize breakage and assure that processes are repeatable and uniform.

Automation planning must address the issue of processing larger sized wafers. Use of larger wafer size is a quick way to increase capacity. However, most users of 125-mm and 150-mm wafers have experienced difficulties in getting fabrication lines running smoothly.

Yield is the obvious major factor for increasing wafer sizes. The 100-mm to 150-mm jump increases the usable wafer surface area by 78% minimum, and the typical production costs increase at approximately half the rate of area increase. Most IC suppliers are bringing production lines for 200-mm wafers on line. Just how much of the 200-mm production will be automated is not known.

If IC suppliers have not already automated 150-mm (6-in.) wafer processing, it is unlikely that the 200-mm (8-in.) versions will be easier to automate as process modifications seem inevitable. Everything from lithography to applying resists uniformly to etching is more difficult with larger wafer sizes. Large wafers will certainly need modified resist vicosities and different spinning speeds for coating. In addition, more cleaning fluid will be needed and larger ovens required to bake the resists. Problems can arise if 200-mm processing is planned for modified equipment designed for smaller, lighter wafers. Some changes are necessary for diffusion, deposition, ion implantation, oxidation, and etching stages as well. Wafer transport is critical with the fragile, smaller 100- and 150-mm sizes and will be a problem with the heavier 200-mm and larger versions as well.

Automation will have its own set of problems: software and hardware compatibility among equipment, equipment adaptability and flexibility, high equipment reliability levels, minimum level of equipment-induced contaminants, and the like. For example, a six-axis robot arm, which had not been designed for clean-room use, was found to be a source of particulate emission in the fabrication area [7]. The major sources of particle generation were the DC brush-type motors driving each axis; particles were escaping through the joints and openings in the robot's metal covers.

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When the arm was used to transfer cassettes of silicon wafers between a storage box and a process machine, it caused noticeable wafer contamination. Extended testing showed that a 150-mm wafer would acquire about 50 particles during each cassette load/unload cycle.

Fortunately, modifications reduced the particle emission rates dramatically. These modifications included gasketing the metal covers, sealing the motors, opening air passages through some joints, and adding a blower and HEPA exhaust filter for evacuation of the entire structure. Table 11.4 shows aerosol emission counts obtained both prior to and following the modifications.

Table 11.5 lists other commonly used wafer fabrication equipment mechanisms and the particulate emission rates of each. Obviously, without modification some mechanisms were unsuitable for use in clean machines. The DC brush-type gear motor is an example of a successfully modified mechanism: The motor and gear cases were sealed and the high-speed shaft was capped, thus essentially eliminating emission, since the low-speed shaft produces very few particles.

While stepping and other brushless motors initially seemed desirable for use in clean-room automation, testing has shown that the bearings in such motors are often significant sources of particles. Motors with double shafts were found to be worse emission sources than their single-shaft counterparts (but capping an unused shaft reduced emission from the other shaft). It is suspected that the structure of these motors caused air to be pumped through the internal cavities and bearings, carrying particles out.

For ball bearings, open bearings produced more particles than shielded bearings, and higher speeds produced more particles than lower speeds. However, it was found that some bearings from a group emitted particles at a rate of several

Table 11.4 Particle Emission Rates for a Six-Axis Robot Arm

Particle emission rates (particles/min)

Axis

Unmodified

Modified

1

2,000

0

2

3,000

3

3

100

4

4

9,000

0

5

10,000

5

6

1,000

4

Totals

25,100

16

Source: Ref. 7.

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Table 11.5 Examples of Various Equipment Mechanism Particle Emission Rates

Emission rate range (particles/min)

Mechanism
Test velocity (rpm)

Lowest

Highest

Stepping motors

9001200

0

1,000

Brush motors (dc)

30007500

0

30,000

Ball bearings shielded

6001200

0

4,000

Ball bearings open

900

200

2,000

Linear bearing/shaft

1501200

300

10,000

Kerk nut/screwa

50ft/min @ 1200

20

100

Pulley/belt

6001200

4

300

Sprocket/poly chain

6001200

1000

6,000

ROH'LIX/shaftb

1501200

10

200

Ball nut/screw

50 ft/min @ 1200

2000

3,000

Linear bushing/shaft

50

10

2,000

aProduct of Kerk Motion Products, Inc., Hollis, NH.

bProduct of Zero-Max, Barry Wright, Minneapolis, MN.

Source: Ref. 7.

hundred per minute while others from the same group emitted none. Some were observed to emit particles initially but then to stop.

It was suspected that the usual material coming from a ball bearing was a lubricant and that the quantity and type used affect emission rates. Bearing storage may cause settling of the lubricant, which then becomes erratically redistributed during operation, producing variable particle emission rates. Shielded bearings that exhibit no emission may have a continuous film between the shield and the race, preventing emission.

Thus the particle emission rates of equipment intended for use in clean rooms can be significantly reduced by using selected components in the construction of the equipment. For complex machines where this approach is not practical, enclosing and exhausting may be successful.

Another robot, an extended reach monomast robot modified for clean room use, has a very low particle emission count as is shown in Table 11.6. When this robot system was used in a wafer cassette handling and transport application, it was found to result in approximately one-half the number, at one-half the average size, of particles deposited on wafers transported by operators. Furthermore, when a vacuum exhaust system was added to the gantry runway drive system (and containing the bridge drive spline and idle gear), the robot emitted fewer than 10 particles of 0.5 mm or larger diameter per cubic foot per robot

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Table 11.6 Aerosol Particle Count for Robot Joint Actuations

Particle size (mm)a

Robot joint

0.5

0.51.5

>1.5

X, Runway drive
2.10

0.2

0

Y, Bride bellows
5.20

0.3

0

Z, Mast bellows
0.15

0

0

01, Wrist roll
0.02

0

0

02, Wrist pitch
0.01

0

0

03, Wrist yaw
0.01

0

0

End effector
2.20

0.3

0

Total, all joints
9.7

0.8

0

aParticle size distribution per cubic foot of air per robot joint actuation, averaged over 100 actuations in a 4-min period.

Source: Ref. 7.

actuation. This level of contamination is compatible with Class 10 or lower clean-room standards.

Wafer transport automation will not only reduce contamination, but it will reduce product quality variation and increase reliability. Together with greater implementation of process monitoring and control, mechanized transport is much better suited to volume production of differing products.

Wafer transport is generally classified as either (1) interprocess transport between steps such as resist application, lithography, and etching, or (2) intraprocess wafer manipulation within a specific processing station.

Interprocess (station-to-station) transport is generally conveyor-type or automatic guided vehicle (AGV) in nature. Conveyors in IC processing are usually the round belt type, although other variations can be very effective, including chain conveyors, shuttle conveyors, air-jet conveyors, and walking-beam configurations. None are perfect, and all have some drawbacks. Round belt versions are popular as they are reliable and have minimal contact area with the wafers, but they do wear and require replacement. Air conveyors have no physical contact with the wafers and are reliable, but they do require careful balancing of the air jets. Also, air-jet conveyors obviously move existing particles around and some eventually land on the wafer. The walking-beam configurations are reliable, wear less than belts, and typically produce less particle contamination than belts.

The particulates generated during operation are primarily a result of friction from direct physical drive or from the guide rails. Transport speed is a factor, as is whether the operation takes place in a tunnel or an open room.

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In a detailed analysis of automation potential for LSI production equipment by a Japanese wafer transport manufacturer, it was determined that automation did exist or was technically feasible in virtually all wafer fabrication operations. The manufacturer evaluated cassette-to-cassette handling, processing operations, process monitoring, and potential for real-time control, plus individual wafer or batch wafer processing options. Of greater concern than the individual operations was the lack of a unified system of control. Control by a central computer is essential, but adequate common interface standards simply do not exist commercially.

Wafer fabrication automation, for VLSI and future generations of fine line devices, is inevitable and mandatory. Some widespread factors that have slowed acceptance are the lack of comprehensive industry standards and the need for users to both engineer and integrate seemingly incompatible equipment from different vendors. Appropriate automation can dramatically increase process consistency and efficiency, reduce contamination, boost productivity, and improve quality and reliability.

Electrostatic Charge

Integrated circuits are sensitive to static electricity or electrostatic discharge (ESD). As such, electrostatic charge poses a serious threat to the reliability of integrated circuits at all stages in their lives: during fabrication, in handling for assembly and test, in packing and shipping, at the user's facility, or in the field. It is generally acknowledged that during the IC fabrication process electrostatic charge does not pose a problem or have a deleterious effect (i.e., damage the device) until the metallization layer is created. Up to this point the primary problem created by electrostatic charge is the attraction of unacceptable levels of particulates from the air and work surfaces.

Furthermore, devices cannot be damaged by electrostatic charges when assembled in a package if the lead frames [in a dual-in-line package (DIP) or flatpack] are uncut, that is, if all the leads are connected together, or in 8-, 10-, and 12-lead transistor outline (TO) packages if the leads are shorted together. The reason for this is that every lead is at the same potential. For electrostatic charge to have an effect, the leads must be at different potential levels, unconnected as they would be in normal use. Thus, true ESD damage can occur from the time that the metallization is deposited to the time the die is attached to and wirebonded in its package and after the leads have been cut.

This fine distinction between static-related losses and contamination losses has resulted in the establishment of three categories of loss due to static electricity. First are the electronic-related losses: metallization breakdown from direct discharge or related field-induced damage. Then there are production-related losses: machine down-time, extended maintenance schedules. The third loss is

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the environmental contamination-related loss: airborne particles, surface particles, cross-contamination or exchange of those particles, including trapped particles on raw materials and production equipment.

Susceptibility of ICs

The smaller geometries of VLSI devices have increased their susceptibility to the point where some state-of-the-art devices can be degraded or destroyed by electrostatic voltages of as low as 20 V. Table 11.7 lists a range of susceptibility for a number of finished semiconductor structures. Varying degrees of immediate damage occur depending upon the levels of energy and/or voltage involved. Latent failures may also result from a slight, perhaps immeasurable, degree of ESD damage that degrade further with time.

In MOS structures, for instance, ESD exposure could cause subtle damage to the gate oxide, resulting in little or no detectable gate leakage. Depending upon the nature of the subtle physical damage, failure might be triggered by decreased voltage threshold, filamentation, or thermal influences. A severely shorted gate oxide might improve as a result of the initial or subsequent static exposure; however, the reliability of a device that has been cured in this manner is questionable. Most digital ICs have various networks that protect the input circuitry (analog devices do not); however, there is a threshold at which these input protective circuits can become degraded.

Static discharge could cause charge to accumulate in the gate oxide or on the device surface; this change in charge equilibrium would affect the reliability of the device. When the positive-negative junction of bipolar devices is exposed to static, a filamentation may short the junction. This possibility would increase over time.

Table 11.7 Statis Susceptibility of Selected Semiconductor Devices

Device type

Range of susceptibility (V)

MOSFET

20200

J-FET

14010,000

CMOS

2502,000

Schottky diode

3002,500

Schottky TTL

1,0002,500

Bipolar transistors

3807,000

ECL hybrid (PC board level)

500

SCR

6801,000

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The aluminum-silicon transport mechanism that results in alloying and eventual short-circuiting is considered a high-temperature phenomenon. Perhaps the small effective cross-sectional area of an ESD-generated filament could experience localized heating under use conditions resulting in higher leakage and eventual failure. A severely damaged junction with a filament short might also experience a cure during the initial or subsequent static exposure. Such a junction is certainly a candidate for later failure.

Electrostatic discharge can open sites of constriction in integrated circuit metallization lines. Static might further reduce the cross-sectional area of each site, increasing the likelihood of latent open circuits due to electromigration or thermal shock. Figure 11.12 is a SEM (scanning electron microscope) photograph showing a catastrophic ESD-induced gate-oxide short.

Static Electricity

Static electricity is defined as electrical charge at rest. The charge in question is produced by the transfer of electrons (or other charge carriers) within or on the same body (polarization), or from one body to another (conductive charging). The magnitude of the charge is dependent primarily upon the size, shape, composition, and electrical properties of the materials comprising the bodies, and upon the energy (usually mechanical) that generated the charge. Charges on nonconductors (insulators) tend to remain in the localized area where they were generated. Charges on conductors, however, are rapidly distributed over the entire surface, and over the surfaces of any other conductive objects with which they come in contact.

The electrostatic field associated with a charged body is also influenced by the capacitance of the body with respect to other bodies in the vicinity, and to ground. For example, if a polyethylene bag is rubbed, it may acquire a charge for which the corresponding potential may be only a few hundred volts. However, if an operator then picks up the bag and moves it away from the bench, as its capacitance decreases with increasing distance, its potential may increase to several thousand volts.

Although there exist several electrostatic charge buildup mechanisms, the charges generated by the triboelectric effect are particularly harmful to ICs. The static charges are created whenever any two materials come into intimate contact, such as by rubbing, and then are separated. As the materials separate, one of the weaker valence electrons of the one material transfers to the other material. The first material, having lost an electron, is then positively charged. The second material, which gained an electron, is negatively charged. They attract particles that may themselves be ionized. The field is formed irrespective of humidity and ionization systems. The triboelectric series, as presented in Table 11.8, lists materials in the order of their affinity for acquiring a positive charge as a result of the triboelectric effect. Thus, when two materials generate

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Figure 11.12
Example of ESD-induced failure. Specimen has metallization removed so that
damage to the oxide layer can be observed. Overall location is shown in
(a) with 2000× magnification, while (b) shows a closeup of the ESD damage.

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an electrostatic charge by means of friction, the one that is highest in the triboelectric series will acquire a positive charge, and the other a negative charge. Electrostatic charges can also be generated when two pieces of the same materialparticularly most of the synthetic plasticsare in intimate contact and are separated (e.g., when the sides of a plastic bag are separated, or when tape is pulled from a roll).

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Sources of Static Electricity

A number of primary sources of electrostatic charge are listed in Table 11.9. Most of these are insulators, and they are typically synthetic materials. Voltage levels associated with electrostatic charge generated by these insulators can be extremely high because the charge is not readily distributed over the surface or conducted to other materials.

Almost every material used in IC manufacturing, from the floor to the clean-room garments, can create static electricity. Out of necessity, most materials used in device manufacture are plastic, which is particularly susceptible

Table 11.9 Typical Sources of Electrostatic Charge

Object or process

Material or activity

Work surfaces
Waxed, painted or varnished surfaces
Common vinyl or plastics

Floors
Sealed concrete
Waxed, finished wood
Common vinyl tile or sheeting

Clothing
Common clean room smocks
Common synthetic personnel garments
Nonconductive shoes
Virgin cottona

Chairs
Finished wood
Vinyl
Fiberglass

Packaging and handling

Common plastic (bags, wraps, envelopes)
Common bubble pack, foam

Common plastic trays, plastic tote boxes, vials, parts bins

Assembly, cleaning, test, and repair areas

Spray cleaners
Common plastic solder suckers
Soldering irons with ungrounded tips
Solvent brushes (synthetic bristles)
Cleaning or drying by fluid or evaporation
Temperature chambers
Cryogenic sprays
Heat guns and blowers
Sand blasting
Electrostatic copiers

aVirgin cotton can become a source of electrostatic charge at low relative humidities (e.g., RH < 30%).

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to static electricity generation. Any rubbing or handling of these materials, whether they are polypropylene work benches or Teflon fluorocarbon resin wafer carriers, will create static.

Another area of critical importance is electrostatic attraction. Wafers quickly acquire charges during processing, and the resulting electrostatic attraction of particles is one of the most common transport mechanisms. The static charge clings to the surface of manufacturing equipment and wafers, attracting the particles that clean rooms are designed to help eliminate.

A common occurrence in wafer fabrication, for example, is the triboelectric charge generated when wafers are removed from or inserted into plastic carriers. Although a single occurrence of this situation may not cause a large static charge, static electricity can be cumulative. Therefore, the static charges on the wafers and the carrier can build to in excess of 10 kV. Teflon carriers are also a major source of electrostatic contamination in wafer fabrication areas. However, the use of metal carriers as a replacement only creates metallic contamination. The best solution lies in making electrostatic charges work for the fabrication manager in unique ways rather than against him. For example, some Japanese semiconductor suppliers are already using solar cells in their equipment to remove airborne particles from systems. In steppers, for example, a solar-cell reticle is placed in the reticle holder. The cell is charged to attract particles and then removed, thus cleansing the chamber of any airborne particles.

Static charge buildup on plastic and other surfaces commonly occurs from air movement in wafer fabrication areas from such sources as laminar flow, blow-off guns, rinser dryers, and ovens. A particular problem is the charge generated by moving air or nitrogen, such as in vertical laminar flow hoods, and the rapid return of the charge after it is drained off.

Friction caused by moving parts in the fabrication equipment is a major source of static charge: resist spinners; conveyors or belts moving across pulleys in wafer transport systems or dispense pumps; fluids or gases moving through plumbing or nozzles; or wafers sliding or rotating across surfaces such as in sputtering equipment. Friction can also cause problems during the final assembly and electrical test steps. For example, high-speed automatic handlers that interface with automatic test equipment for making rapid electrical measurements generate static electricity and must be controlled. The IC sliding down the rail generates static electricity, as does the operation of the shuttle mechanism. Bowl feed handlers generate static electricity due to the rotation of the parts in the bowl. The handler must be grounded at proper locations, as well as at the shuttle mechanism.

Again, depending on at what point in the fabrication process this occurs, the end result could be process contamination, no device damage, partial degradation, or catastrophic failure.

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Controlling Static

Solving the problem of static generation first requires a thorough process of problem evaluation. This involves a clear idea of what is to be accomplished, what needs to be protected, and a knowledge of any potential weak spots in the protective system. In effect, management must first step back and examine its clean-room assembly, test, and shipping processes and handling methods. It must look at its clean-room material selection, training and orientation methods, production needs, and packaging materials.

Next comes personnel training. Most IC suppliers agree that static control hardware is of little value if clean-room, assembly, and test personnel are not properly trained. The development of a training program is a critical factor (the key) in controlling static generation. Training should be given for all operations personnel within a controlled area, and documented for certification purposes. Recertification should be accomplished annually. A static control coordinator should be appointed and trained in the details of the prevention program. He or she may then ensure that all preventive measures are complied with daily.

There are two approaches to static control: (1) prevent static buildup, and (2) utilize static discharge methods (remove all preexisting charges). Since all areas involved in IC manufacturing (fabrication, assembly, test and shipping are susceptible to ESD) they must be equipped with electrostatic preventive and handling measures, and be subject to audits.

A broad spectrum of commercially available materials, components, supplies, and equipment intended for or useful in controlling electrostatic charge is available.

Traditionally, the method of reducing clean-room, assembly, test, and shipping static damage has involved making all surfaces near the IC conductive and connecting all of them to a common (earth) ground. This method generally involves the use of static-controlled floor mats and wrist straps, antistatic wafer carriers, static-controlled suits (garments), and static-controlled table tops. Using this method, static charges are conducted to ground before they can build up to dangerous levels. This technique has frequently been adopted for wafer fabrication facilities and sometimes includes the use of localized ionization systems, such as ionizing air guns and localized air blowers.

The system creates small islands of protection around individual work stations, thereby ensuring that electrostatic charges are bled off before they get to the wafer and damage the individual devices. Because the method treats each station individually, rather than attempting to treat the entire room, it is less expensive. The disadvantage of this system of static control is that it cannot be used for mobile personnel, since the grounding straps have limited range.

One alternative to this method is to use conductive tile flooring instead of the conductive floor mats, thus allowing clean room personnel more mobility.

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The disadvantage of this system, however, is that it is more expensive than the conductive floor mats.

Another approach to static control is the use of air ionizers to generate positive and negative ions in the surrounding atmosphere. The systems work by allowing ions to combine with oppositely charged surfaces nearby. When the ion strikes that surface, the ion and the surface are both neutralized. As mentioned before, the moving air in vertical laminar flow hoods and that in nitrogen blow-offs are two primary sources of static. Placing air ionizers in the path of the moving air or nitrogen effectively neutralizes the charge built up in the gas.

For room ionization systems to work efficiently, ions must be propelled away from the system itself. For that reason, many room ionization systems depend upon previously installed air conditioning units to move the ions into the room. Another method of propelling the ions is to install the ionization grids in laminar flow hoods. Laminar air flow blows the ions into the work area, increasing the range of the ionizer. Another method of distributing the ions is to install the grids into clean-room ceilings. This method allows the ions to distribute evenly by the time they reach the floor. Three types of large area ionization systems are available: conventional AC, bipolar DC, and low-frequency AC or pulsed DC.

Another method of ionization involves the use of localized ionizing air guns. The guns use an in-line air ionizer, which may be electrically powered or may use a nuclear source. The nuclear systems require no maintenance and cannot suffer from the potential hazards of ozone or electromagnetic interference (EMI), hazards that are sometimes present in electrical systems. The nuclear systems also generate a balanced stream of negative and positive ions, but do not generate as many ions as electrical systems.

Use of air guns in the clean room has met with a mixed reaction. While some say that the air guns blow contaminants around the room, others say the guns are the only method for removal of charged particles from work surfaces.

Use of antistatic solutions is another method designed to heighten conductivity, although the antistat itself does not make the surface conductive. Instead, the antistat adsorbs moisture from the air and thereby provides conductivity.

The Work Area

A typical electrostatic-safe workbench is shown in Fig. 11.13. Note that the work surface is conductive, and is connected to earth ground through a 1-MW resistor that provides current limiting to protect workers from electrical shock hazards caused by ground faults. Ground points must be provided for equipment and personnel. A nonconductive bench top may be covered with a conductive mat.

A conductive wrist strap must be provided to assure that the worker is at ground potential. A 1-MW resistor is again required for safety. Conductive

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Figure 11.13
Typical electrostatically controlled workbench, intended to drain or neutralize
electrostatic charge as fast as it is generated, thereby preventing its accumulation in
potentially damaging amounts.

footwear or a conductive strap on conventional footwear offers additional protection. Finger cots should be used only in an ionized air environment. Because some fabrics can generate static electricity, when practical, workers should wear overgarments that dissipate charges. Five generic fabrics are presently available for this purpose:

Cotton

Polyester

Cotton/polyester blend

Tyvek (spunbound olefin)

Cotton/polyester blend with additional stainless-steel threads

Cabinets should be made of conductive materials (e.g., steel), and should be grounded through a 1-MW resistor. Containers used to store or transport sensitive devices must be made of conductive material. Treated cardboard and plastics are also acceptable. Containers holding devices should be stored only on conductive, grounded surfaces.

Carts should also be conductive. A conductive strap or brush affixed to the cart, in contact with the conductive floor, provides additional protection. Only antistatic packing material should be allowed in the work area. All electrical equipment should be earth grounded. Plastic surfaces, such as CRT covers and terminals, should be treated with a topical antistat at regular intervals.

Handling Guidelines

Operations that require human handling should be minimized. Personnel should always be grounded prior to removing sensitive items from protective packaging. Tools and test equipment used in protected areas should be properly

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grounded. Hand tools should not use insulation on the handles. If plastic-handled tools must be used, they should be treated with a topical antistat.

Assure that all containers, tools, test equipment, and fixtures used in protected areas are grounded before and during useeither directly, or by contact with a grounded surface. Grounding of electrical equipment should be via a grounded plugnever through the conductive surface of the grounded work station. Work instructions, drawings, and similar documents used in a protected area should not be covered in common plastic sheeting or containers. Workers' clothing should never make contact with the devices, and workers should avoid friction-producing activities in the vicinity of the work station, including putting on and taking off of smocks, wiping feet, rubbing of hands, etc. Workers should avoid touching device leads or contacts, and should handle parts only by the case.

When devices are removed from protective containers or packaging, they should be kept either pin-down on a conductive surface, or in a conductive container with pins in contact with the surface, or all leads shorted together.

Caution should be observed in using solvents such as acetone and alcohol or other cleaning agents for cleaning ESD protective materials. Additionally, all static-generating material should be removed from the work area.

Humidity

Then there is the topic of humidity control. Some IC suppliers believe that humidity control is important to controlling static generation, keeping the humidity level as high as 60%. However, a 60% humidity level makes it very uncomfortable in a clean-room bunny suit and results in much wasted time until one feels comfortable enough to work. Additionally, high humidity levels could result in corrosion mechanisms being initiated in the IC metallization structure. Instead, industry experts recommend that humidity be maintained at a level comfortable for people in the general plant, around 40%. Below 40%, static problems increase dramatically. Even if it were possible or desirable to maintain a high level of humidity (e.g., 90%), static problems would still exist.

Humidity is just a temporary preventer of static. High humidity might work well in a place where there is not a lot of movement, like a storeroom. But it does not work in a place where there is a lot of movement.

Controlling electrostatic charge involves controlling the environment, people, and materials. Table 11.10 summarizes the primary factors from the previous discussion involved in controlling these three areas.

Equipment Considerations that could Produce Errors at Wafer Probe

Wafer probing may be performed with manual, semiautomatic, or fully automatic probers that interface with testers intended to measure specific electrical

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Table 11.10 Primary Factors Involved in Controlling Static

Environment

People

Materials

Floors

Body charge control (body mass, body capacitance, footware)

Raw materials (everything that is part of the finished product)

Work surfaces
Clean-room clothing

Production aids (solvet, tape, tools)

Equipment (chairs, carts, conveyors)

Produres (training, orientation, job engineering, feedback)

Packaging materials

Work area options (walls, ceilings, ventilation grids)

characteristics of the chip under test. The type of prober chosen for a specific circuit implementation is determined by such items as the test environment (laboratory or production), the test speed as determined by device type and tester (e.g., memory versus logic), step-and-repeat table speed, EMI generation, X-, Y-, and Z-axis positioning accuracy requirements, prober/tester interface capabilities, and wafer-mapping capability.

The physical forces that affect the contact interface between tester and device under test (IC) are very critical to ensure accurate wafer probe testing. Significant effort is expended in controlling this interface. Some of the critical items that affect the viability of the interface are probe cards, probe tip material/contamination, contact resistance, probe contact force, and overdrive. Some of these items are discussed below.

Very brittle semiconductor materials, such as gallium arsenide, as well as very thin silicon wafers, require a light contact force at the test pads. Contact resistance and probe scrub-mark characteristics of length, width, and depth have been correlated with contact forces, probe-tip alloys, and yields. Changes in probe overtravel resulting from a lack of system planarization control or from wafer thickness variations may result in dramatic yield swings.

Proper alignment of wafer chuck and probe card holder in the X-Y-Z plane (i.e., planarization) that provides effective contact repeatability to the device under test (DUT) is extremely important. If the chuck or card holder or both are out of planarity, the measurements obtained will be inaccurate and erroneous, leading to rejection of good die.

Wafer-probe yield, probe contact resistance, potential for pad damage, and overall probe life are all affected by the selection of probe-tip material. Poor probe planarity and high contact resistance cards are often the cause of continuity

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failures, high or low input voltage (Ein), loss of Vcc operating range, and functional failures. Probe-tip selection and effective probe-card maintenance can affect probe yields by as much as 15%.

The probe-tip material most frequently selected is tungsten, which wears well due to its extreme hardness. Because it is also resistant to fatigue, it consistently provides repeatable contact force. Given the same contact force, tungsten tips will last longer than either beryllium-copper or palladium.

Tungsten, however, has a major disadvantage in some probing applications; it exhibits high, inconsistent, unrepeatable contact resistance. Although clean tungsten probe tips exhibit about 250 mW of contact resistance, this value increases dramatically with the accumulation of contamination. Aluminum oxide (from bonding pads) and other contaminants tend to accumulate on the probe tip, where they are impacted between nodules of hard tungsten strands. (This grain structure is formed when the tungsten wire is manufactured under high temperature and pressure.) Contact resistance may vary from probe to probe by more than 5 W. Some probe tips have been known to exceed 50 W contact resistance, and even to present an open circuit at the specified value of overdrive, due to the accumulation of contamination.

Clearly, wafer probe-yield correlation problems and actual yield loss may result from inconsistent contact resistance. Contact-repeatability problems are even more prevalent between tungsten and gold, where an electrochemical reaction occurs that degrades conductivity and very rapidly causes contact resistance to increase. It is especially important to avoid tungsten-gold contact when the measurements being made can be affected by unstable contact resistance.

When probing gold with beryllium copper (BeCu), contact resistance is typically 100 mW. It is 200 mW when probing aluminum. With BeCu tips, a self-cleaning action maintains contact resistance at the nominal low values, thus providing stable, repeatable measurements. However, given the same contact force, BeCu probe tips wear faster than tungsten because BeCu is softer than tungsten. Since BeCu contact resistance is lower and more stable than that of tungsten, less prober overdrive is required for good repeatable contact.

The contact force best suited to the device under test will minimize contact resistance, minimize potential for pad damage, and optimize probe-yield repeatability. With the wide variety of proprietary test-pad alloys that are used in the various ICs being produced, it is necessary to select the particular tip that is best suited to the specific device under test. The probe contact force selected for a particular probing application will be derived from an optimum mix of the following factors:

Prober overdrive/system planarization

Probe-tip material

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Tip-shank diameter (needle material shank diameter)

Tip-point diameter (point of needle)

Beam length (distance from tip point to solder joint wall of bending beam)

Contact resistance and overdrive are inversely related. Excessive overdrive can damage the device under test, whereas too little pressure may result in poor contact and increased contact resistance. For a given probe tip, as overdrive is increased, contact resistance decreases. There is a point, however, at which overdrive becomes excessive for a particular application. Probes scrub (i.e., slide laterally) approximately 0.1 mil per mil of prober overdrive. Thus, excessive overdrive may scrub them completely off the test pad. Other results of excessive overdrive include

Contact degradation of tungsten probes, which may build up aluminumoxide tip contamination more quickly.

Decreased probe life, due to increased fatigue and tip wear.

Potential damage to pads, with microcracking of the underlying silicon oxide layer, excessive scrubbing of metallization (making pads unbondable), or even punchthrough, with subsequent damage to underlying circuitry.

With BeCu probes, low overdrive can be used for effective control, assuming good card maintenance and good system planarization. Probe life, as well as repeatability of measurements, will increase with reduced overdrive. Pad damage will also be minimized, and probe yield maximized.

Contamination During Bonding and Packaging Operations

Wire Bonding

To create a reliable bond, the bonding materials must be brought into intimate contact; anything that interferes with this contact will adversely affect the eventual bond strength. Therefore the surfaces must be as clean as possible and free of oxides, oils, or other contaminants.

In the case of aluminum wire bonds, the bond is created between two identical materials. The adhesive strength is a function of the extent of intimate contact between the wire and die metallization. The surface of both materials is deformed during bonding and some surface contamination can be displaced or absorbed by the ultrasonic motion of the wire. As long as the surface contaminant is not too thick and does not act as a lubricant to prevent surface friction, the wire material will contact the die metal and a bond will form. The resultant bond strength will be a combination of van der Waals forces and some chemical

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bonding, which combine, on a molecular scale, the two surfaces. As long as a good percentage of the footprint area is so combined, an adequate bond is formed.

Gold wire, on the other hand, is dissimilar to aluminum metallization, and this represents a different bonding reaction. As in the case of aluminum wire, gold also requires clean surfaces, and in fact requires a cleaner surface than aluminum wire bonding. To create a bond, the gold must contact aluminum and deform the microscopic surface to a point where the two materials diffuse. This diffusion of gold and aluminum creates a variety of intermetallic compounds, which provide the adhesive strength of the bond. The formation of intermetallic compounds is greatly influenced by impurities, which can affect the diffusion rates of the two materials and create microscopic voids in the intermetallic formation. These voids, known as Kirkendall voids, occur when the diffusion rates are accelerated and vacancies occur that cannot be filled by the diffusing materials. As a rule, these voids will occur at the gold/gold-rich phase of the intermetallic and the bond will fail due to a cohesive failure of the intermetallic. Unfortunately, these bond failures require time and temperature to become apparent and may pass initial bondability tests. During initial bondability tests, the lack of adhesion of the two materials is the only parameter than can be assessed.

As stated before, aluminum wire bonding utilizes ultrasonic, while gold utilizes thermocompression or thermosonic techniques. Aluminum wire bonding takes place at ambient temperatures and the bond is created by ultrasonic agitation and mechanical pressure. Gold wire bonding, on the other hand, is performed with mechanical pressure and elevated temperature to aid in diffusion. The elevated temperature is achieved by heating the sample and capillary of the bonder. Thermosonic bonding, however, is performed at lower temperatures than thermocompression with the assistance of ultrasonic agitation of the capillary tip. This ultrasonic agitation aids in the displacement of surface impurities, but also makes thermosonic bonding more susceptible to adhesive failures with contaminants, which may act as a lubricant at the interface.

Table 11.11 lists some typical bondability anomalies and their possible causes.

The effects of ionic and organic contamination on wire bonding, from a process and reliability standpoint, can be very detrimental. Contamination may be divided into two types, organic films on the surface of a chip or substrate and ionic solutions or residues.

Organic contamination usually occurs in the form of an invisible film, rendering the bonding pad surfaces hydrophobic (nonwater wettable). With these films present, bondability can be degraded substantially, especially with higher ambient humidity.

Ionic contamination, on the other hand, generally causes visible corrosion on bonding pads. This corrosion may appear as brown stains or, when the

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Table 11.11 Bondability Problems

Anomaly

Cause

Bond pad opening not visible
Glassivation not adequately removed

Bond pad clear, but no imprint from bond; wire, however, is deformed

Bondability should be repeated with harder wire

Bond pad clear, noticeable imprint from bond; imprint clean of wire material

Possible thin film contaminant; possible inadequate ultrasonic vibration or temperature on bonder

Bond pad clear, noticeable imprint from bond; imprint has residue of wire material

Possible thin film contaminant

Bond pad stained or discolored; no imprint from bond.

Possible overetch or contaminant; use harder wire

Bond pad stained or discolored; noticeable imprint from bond; imprint clean of wire material

Possible overetch or contaminant; use harder wire

Spotty stain; imprint from bond present only on clean areas

Possible underetch of passivation

Spotty stains, imprint noticeable on stains as well as clean area

Possible chemical or rinse residue; clean with acetone and repeat bondability

aluminum is missing completely, as blackened areas. Three conditions are known to promote corrosion: (1) the presence of an ionic contaminant; (2) the presence of dissimilar metals in the area, setting up a galvanic cell due to different electrochemical potentials; and (3) the presence of moisture.

The three primary sources of ionic contamination that may reside on the IC die, in decreasing order of importance, are

1. Postfabrication and presealing die-handling operations. The chip has its highest vulnerability to an uncontrolled environment during mechanical and human handling, especially during the die-attach and package-assembly processes.

2. Wafer fabrication. Sources of ionic contamination abound in the factory. It may come from etch solutions and photoresist solutions in

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the wafer fabrication area, from contaminated solvents and water, or from fingerprints and even dust. Inadequate cleaning and rinsing of wafers can leave contaminants as well.

3. Package hermeticity failure, allowing the ingress of ions from external sources along with moisture. During subsystem and system assembly, many parts receive detergent washes and/or conformal coatings at the PC board level. Many of these materials are notorious sources of both positive and negative ions.

As mentioned previously, an ever-present ionic contaminant source is the human body. Body effluvia from coughs, sneezes, perspiration, and skin oil secretions are rich in both alkali ions and chlorides. Sloughed-off skin cells (e.g., dandruff) can be the source of entrapped particle problems as well as a source of ions (by leaching, if moisture condensate contacts the cells). The need for protection from such contaminant sources has been well recognized in wafer fabrication. However, it has received inadequate attention in wafer sawing, dice sorting, chip mounting, wire bonding, and package-sealing operations where dice are extensively handled by machines and humans in environments of less-than-optimum cleanliness; that is, assembly areas are not clean-room environments.

Ionic contamination and the corrosion that often accompanies it is not a reversible process, so it is essential that the sources of ionic contamination be eliminated to prevent their deleterious effects.

Surface contamination results in poor-strength thermocompression bonds. As such, a cleaning process is normally used to remove any contaminants that might be present as a result of storage, transportation, and handling after metallization. A typical cleaning process would entail removing handling soils by means of an oxidizing 10% hydrogen peroxide-deionized (DI) water solution made from 30% hydrogen peroxide. The process consists of a Freon TA vapor degrease followed by two 10-min immersions in a 10% hydrogen peroxide-DI water solution heated to 70°C. This is followed by a 1-min, three-stage cascade rinse in DI water at room temperature and a four-sequence hot DI water rinse for 20 min. The DI water is maintained at a level exceeding 110 MW.

The wafer cleaning process, if not carefully controlled, can cause contamination problems. The following actual lessons learned example illustrates this point. During the IC assembly process it was found that a thermocompression bond adhesion problem existed. The source of this problem was a thin layer of tin contamination on the bonding pad that was traced to the hydrogen peroxide cleaning process. It was determined that tin was being deposited during its elevated temperature hydrogen peroxide immersion. Variation of tin from one manufacturer to another was found; however, similar variation appears to exist within different lots from the same manufacturer. This tin variation may be linked to the quantities of other elements in the hydrogen peroxide, since the purpose

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of the sodium stannate addition is to deter the possible decomposition of the hydrogen peroxide by these elements. The solution to this problem was to change to an ultrapure grade of hydrogen peroxide, resulting in no residual surface contamination. This case example demonstrates how an inocuous procedure such as surface cleaning can cause a significant quality problem.

The removal of organic contaminants will insure bondability. One of the most effective methods for removing surface organic contaminants is by means of a plasma etcher (argon or oxygen). Even for grossly contaminated surfaces, plasma cleaning can render the surface bondable again. Furthermore, the coupling of the wire to the pad interface is greater with plasma-cleaned surfaces, as evidenced by higher sheer strengths. This means that lower ultrasonic energy can likely be used to effect the bond, a definite advantage for sensitive surfaces such as GaAs.

Corrosion Mechanisms*

The corrosion of metallized ICs historically has been and continues to be a major reliability concern, especially in view of the use of smaller circuit geometries and multilevel metal structures, the expanded use of organics in packaging (especially hybrids), and the importance of product quality and consistency. Controlling the access of moisture to and ionic contamination of IC chips has been the chief means of minimizing corrosion as a circuit failure mode. Advances in both hermetic packaging and plastic materials improvements have improved moisture control.

The presence of water, a necessary condition for corrosion, is always a consequence of the materials and processes used for packaging IC chips. Water vapor may be entrapped within the cavity of hermetic parts at sealing. It may also be released by package materials after sealing. At a constant temperature, most truly hermetic package cavities will contain a moisture level in equilibrium with the cavity walls. Temperature excursions will shift the equilibrium. In particular, an extreme drop in temperature will cause the sealed cavity to attain its dew point, and condensation will form on inner surfaces of the cavity, including the IC chip. Sources of water in hermetic parts are piece parts (e.g., ceramic, metal), sealing materials (e.g., glass, braze), auxiliary materials (e.g., die attaches, getters), sealing ambient (the gas species present in the equipment where parts are actually sealed), human effluvia (spittle), and package leak rate.

Integrated circuits encapsulated in a plastic molding compound are more susceptible to corrosion than hermetically sealed circuits, since all plastic molding compounds offer poor resistance to moisture ingress from the outside environment.

The two primary corrosion mechanisms of metallic IC structures are the

*Portions of this section excerpted with permission from Ref. 8.

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interconnect segments and bond pads. The corrosion of these structures can be quite different, since different amounts of metal are involved. Additionally, interconnect segments are typically passivated, while bond pads are exposed.

Aluminum, typically alloyed with small amounts of silicon and/or copper, remains the principal component of IC metallization. Mechanisms discussed herein address corrosion of aluminum from a fundamental chemical point of view. Aluminum corrosion can be highly individualistic and affected by a diversity of on-chip conditions.

The wide diversity of materials, gases, and chemicals used to fabricate ICs presents much opportunity for chemical corrosion to occur. Table 11.12 lists some of the possible chemical reactions by which aluminum can corrode. All except perhaps Eq. 12 could conceivably affect metallized ICs. Equation 11 demonstrates the special danger posed by moisture when copper-doped aluminum comprises metallized ICs. This is especially important in view of the increasing use of copper-doped aluminum for VLSI circuits. Equation 10 shows that chloride-containing residues in combination with water pit the metal.

The effects of aqueous solutions on aluminum depend on the pH of the solution. Within the pH range of approximately 4.08.5, aluminum is actually passivated by water since a thin film of aluminum oxide forms in accordance with Eq. 7. As long as the pH level remains between 4.0 and 8.5, the aluminum

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will remain beneficially passivated and will not corrode. Outside this range, corrosion rates rise exponentially due to the small amounts of aluminum on typical IC metal structures (Table 11.13).

Simple condensation of pure water cannot produce solutions in the dangerous pH range. It has a pH within the range of beneficial passivation. Thus, water condensate, by itself, is therefore not a corrosive agent, even when it is in direct contact with an IC chip.

The following situations address possible chemical mechanisms that could shift the equilibrium of aqueous solutions into the acidic or basic pH ranges, resulting in corrosive conditions.

If M⁺ in Eq. 8 of Table 11.12 is the infamous sodium ion, this equation now becomes

(15)

Solving this equation by taking pH = 8.0 as the threshold for basic corrosion, it is found that an aqueous solution containing 1.0 10⁻⁶ moles of sodium ion per liter of liquid water can have a pH of 8.0 and will provide the threshold at which aluminum will corrode. Next, extending this concept to the real environment of a hermetic IC package with an internal cavity volume of0.1 cm³ and containing 5000 ppm of water vapor and assuming the physically impossible event that all the moisture is localized on the chip surface, then only 3.0 10¹¹ atoms of sodium need be present to approach the alkaline corrosion threshold. In the more likely event that only, say, 1% of the available moisture condensed on the chip, then only 3.0 10⁹ atoms of sodium need be present to approach the alkaline corrosion threshold. The point is that these quantities of sodium atoms represent almost vanishingly small amounts of surface impurity. Given the ubiquitous nature of the alkali ion species, wafer and chip surfaces easily contaminated by them can be very susceptible to corrosion if moisture condensation occurs.

Table 11.13 Amount of Aluminum Present on Metallized Integrated Circuit Structures (mdd = milligrams per square decimeters per day)

Feature

Metal mass

Time to corrodec

Bond pada

2.8 × 10⁴ pg

67 hr

Interconnect segmentb

6.8 × 10¹ pg

10 min

aBond pad, 4 mils × 4 mils × 10,000 Å thick.

bInterconnect segment, 5 mm wide × 5 mm long × 10,000 Å thick.

cAssumes a corrosion rate of 1.0 × 10⁷ pg at 10⁻⁵ mdd and 70°C.

Source: Ref. 8.

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The need for clean wafer fabrication and assembly processing is thus emphasized. This is especially true for unpassivated bond pad structures, which not only are exposed but also serve as sinks for both contaminant and condensate collection. For these reasons, it is suggested that bond pad corrosion not clearly attributable to other mechanisms (e.g., corrosion due to chloride ion contamination per Eq. 10) is predominantly due to basic chemical corrosion.

Acid-forming species that could attack aluminum by the chemistry of Eq. 9 are present in all the mineral acids commonly used in IC processing. The A⁻ in Eq. 9 could represent any one of the following anion species from these mineral acids: NO⁻³, nitric acid (HNO3); SO2-4, sulfuric acid (H2SO4); PO3-4, phosphoric acid (H3PO4); F-, hydrofluoric acid (HF); Cl⁻, hydrochloric acid (HCl⁻). (The attack of HCl on aluminum is more properly described by the pitting phenomenon of Eq. 10.)

It is not generally expected that these materials themselves contribute to corrosion. All the acids are quite soluble in the abundant amounts of deionized water used for rinsing devices in processing. Anion residues as a direct consequence of wet chemical processing will occur only as a result of inadequate process execution.

There is, however, one aspect of dry device processing that can leave an acid-forming residue. Plasma process procedures using fluorocarbon reactant gases (CF₄ and others) impart significant amounts of fluoride ion to delineated aluminum. Corrosion has been observed where water presumably combined with fluoride ions from such residues, forming hydrofluoric acid; with time and perhaps bias, the acid attacked the aluminum, forming an aluminum oxyfluoride corrosion product. Dry IC processes must be carefully engineered to avoid the problem of residual fluoride contamination.

Another type of acidic aluminum corrosion is made possible by the deposition of a protective glass coating containing phosphorus on the IC die. Proper amounts of phosphorus give structural integrity to the glass film and also provide some alkali ion gettering. But phosphosilicate glass exposed to moisture can form phosphoric acid by the reaction

(16)

and aluminum corrosion can occur per Eq. 9. From the previous discussions on pH, it is clear that the localized pH of any phosphoric acid formed must be less than 4.0 for corrosion to occur. It then becomes a matter of local in situ chemistry as to whether phosphoric acid of a sufficiently low pH can form.

Corrosion of devices by the phosphoric acid mechanism is highly individualistic. The mechanism may well account for much single-point conductor stripe corrosion, where on the order of only 10 pg of metal need corrode to cause failure. A single glass defect (crack), reaching to a conductor stripe, could contain the condensate of a very acidic pH if and when phosphorus leaching occurs. The

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mechanism probably accounts for little if any bond pad corrosion, where 10⁴ pg of metal must corrode for failure.

Corrosion can be limited by paying proper attention to and involving the use of the following procedures:

1. Moisture control (keep moisture away from the chip surface).

2. Dry sealing ambients.

3. Careful choice and engineering of packaging materials, especially with regard to cavity organics.

4. Baking.

5. Low leak rates for hermetic packages.

6. Low moisture permeation encapsulants for molded packages.

7. High-integrity die passivation films.

8. Hydrophobic die coatings.

9. Clean wafer processing.

10. Clean die assembly processing (avoid alkali and halide ion contamination as well as residual hydrocarbon contamination that could trap other impurities).

11. Consistent execution of processing, with ongoing attention to all factors. One poorly executed step can adversely affect yield and/or be carried through latently to cause serious problems with part reliability.

Assembly Contamination

Wafer cleanliness is extremely important, even in the assembly areas because even though there is a passivation layer on the wafer, the bond padsbeing the weakest linkmust be protected from ionic contamination. Assembly areas are not clean-room environments, but should be considered as such.

Wire-Bonding Automation

Automatic wire bonding eliminates the human-induced contamination and handling failure mechanisms. However, despite the power and flexibility of today's automatic bonding equipment, the automatic machine is not a panacea that suddenly drops into the production line to cure all ills. On the contrary, successful assembly automation usually requires a degree of process and material consistency and cleanliness beyond that required for manual assembly.

As discerning as any machine vision system is today, there are some problems. It cannot see variations in metallization, vias, or contamination and steer around them on a case-by-case basis as a manual operator often does. Clean, contaminant-free surfaces that are smooth and consistent in location will promote reliable, high-speed, error-free wire bonding. This requires tight control of all of the processes upstream of the wire bonder, including dicing and die bonding. It requires unrelenting effort to maintain control over the process, but yields superior results in throughput, yield, and reliability.

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The greatest success in using automatic equipment is achieved by those who understand the equipment and its functioning thoroughly. Familiarizing everyone with the equipment and providing in-depth technical training for operators and technicians is critical. Automatic equipment is complex; however, it still is only a tool in the hands of the operator.

References

1. Surface Photovoltage Monitoring of Heavy Metal Contamination in IC Manufacturing, Jastrzebski et al, Solid State Technology, December 1992.

2. A. C. Titus, Photomask defects: Causes and solutions, Semiconductor International October (1984).

3. R. E. Howard, Selecting semiconductor dopants for precise process control, product quality and yield, and safety, Microelectronic Manufacturing and Testing December (1985).

4. From Microchip Fabrication-A Practical Guide to Semiconductor Processing (Van Zandt), Semiconductor Services, 1984.

5. J. Hunter et al., In-situ particle monitoring reduces wafer defects, Semiconductor International, November (1993).

6. C. R. Deininger, Specifying a factory automation system, Microelectron. Manufacturing and Testing January (1986).

7. L. G. Bailey and G. G. Rogers, Reducing contamination in automated systems by design, Microcontamination November (1985). Copyright © 1985 Canon Communications.

8. R. K. Lowry, Microcircuit corrosion and moisture control, Microcontamination May (1985). Copyright © 1985 Canon Communications.

Selected Readings

1. P. Burggraaf, Equipment generated particles: Ion implantation, Semiconductor International, September (1991).

2. C. M. Osburn et al., The effects of contamination on semiconductor manufacturing yield, J. Environ. Sci. March/April (1988).

3. O. J. McAteer, Electrostatic Discharge Control, McGraw-Hill, New York, 1990.

4. T. Dangelmayer, ESO Program Management: A Realistic Approach to Continuous Measurable Improvement in Static Control, Van Nostrand Reinhold, New York, 1990.

5. W. Greason, Electrostatic Damage in Electronics: Devices and Systems, John Wiley & Sons, New York, 1987.

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12
Contamination Control

The presence of particulate contamination is determined by direct detection of the particles and is also influenced from the failure of the IC to perform as specified. The most effective control of particulate contamination involves the following items:

1. Identification of the source of the offending particles.

2. Monitoring the manufacturing environment (see Refs. 2 and 3) and process chemicals and gases (including water) for unacceptable levels of particles. Table 12.1 summarizes the IC fabrication cleanliness requirements for air, deionized water, chemicals, gases, and static charge.

3. Elimination of particulate contaminants that appear in the finished product or at some intermediate manufacturing state, despite monitoring procedures.

Control of particulate contaminants that appear despite monitoring procedures can be accomplished by reducing particle emission from all likely sources; however, this strategy is more expensive than that required to control a single

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Table 12.1 Semiconductor Cleanliness Requirements

Source

Specification

Air

Particulates, LSI

Class 100 at 0.5 mm

Particulates, VLSI

Class 10 at 0.3 mm

Particulates, ULSI

Class 1 at <0.1 mm

Humidity

1550%

Temperature

6874°F

Photochemical smog

2 pphm (parts per hundred million)

Deionized water

Resistivity

1518 MW-cm

Particulate

Less than 100 particulates/cm³ after 0.5-mm filtration

Bacteria

Less than 100 colonies/ml sample after 0.5-mm filtration

Chemicals

Metallic impurities

Less than 1 ppm

Filtration

To 0.2 mm

Gases

Purity

Greater than 99.9%

Water vapor

Less than 5 ppm

Filtration

To 0.3 mm

Static charge
Less than 50 V

Source: Ref. 1.

source of contamination. Alternatively, individual sources may be more tightly controlled in series and the results monitored. When the contamination problem disappears, the implication is that the currently (most recently) controlled source is the problem. This method is expensive and time-consuming and may be ineffective in locating an intermittent contaminant source in any reasonable amount of time.

The most cost-effective and efficient method of controlling the source of particulate contamination relies on the identification of the contaminant particles as the first step. Such identification may lead to the conclusion that the particles have a unique source and only this source need be more stringently controlled in order to eliminate the contamination problem. An example of such a case would be the identification of a particulate contaminant such as wear particles of an alloy found in only one machine used in IC manufacture. Even in cases where identification of the particulate contaminant does not indicate a unique source, knowledge of the composition of the contaminant can indicate a small pool of possible sources while eliminating other sources from further consideration. Table 12.2 provides, as an

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Table 12.2 Examples of Particle Types and Sources

Particle type

Source

Crystalline aluminosilicate
Airborne and personnel borne dust

Glasses, ceramincs, metals, polymers

Production equipment

Metal oxide and chloride
Corrosion

Hair, skin cells, chlorine
Personnel

Fiber
Protective garments and marking materials

Exotic crystalline salts
Production chemicals

Table 12.3 Overview of Fabrication ''Contaminants'' and Contamination Control

Source

Type

Detection

Control

Atmosphere
Particulates

Gases (pollution)

Particle counter

Ozone detector

Laminar flow hoods
Clean rooms
Air locks
Positive pressure rooms
N₂ dry boxes
Air conditioning
Charcoal filters

Water vapor
(humidity)
Heat

Humidity meters
Thermometers

Air conditioning
Air conditioning

Water
Other liquids
Heavy metals
Bacteria
Electrolytes
Resistivity meters
Resistivity meters
Culture counts
Resistivity meter
Deionized water
Deionized water
Ultraviolet light
Deionized water

People

Particulates:lint, dandruff, etc.;makeup, hairspray, chemicals (sweat)

Particle counter & visual inspection

L.F. hoods, clean rooms, smocks, hoods, booties, gloves, hoods, and tweezers

Chemicals
Particulates
Metals and sodium
Visual
Chemical analysis
Filtering (vendor and point of use)

Electronic-grade chemicals

Room/work stations

Particulates
Particle counter
Visual
Clean room
V.L.F. hoods
Sealed surfaces

Gases
Particulates
Other gases
Visual
Gas analysis
Line filters
Construction of facility

Source: Ref. 1.

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example, a partial listing of possible particle types and sources. Table 12.3 summarizes various IC contaminants, the means used to detect these contaminants, and the methods of controlling the detected contaminants.

References

1. Van Zandt, Microchip FabricationA Practical Guide to Semiconductor Processing, Semiconductor Services (1984).

2. J. Hunter, et al., In-situ particle monitoring reduces wafer defects, Semiconductor Int. November (1993).

3. L. Jastrzebski et al., Surface photovoltage monitoring of heavy metal contamination in IC manufacturing, Solid State Technol. December (1992).

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13
Computer-Based Sources of Error in Design and Test

Circuit Design Overview

Computer-aided design (CAD), simulation, and manufacturing (CAM) have accelerated the development of new and complex products, increased productivity in manufacturing, and are producing higher quality products.

Design tools have progressed to a very high level of accuracy and sophisticationthey marry the layout with the process (wafer fabrication) specific data. Because of this, first-time functional silicon success of structured integrated circuits (i.e., memories) containing more than 16 million transistors and random logic circuits containing more than 3 million transistors has been achieved. The circuit layout design rules must be based on the inherent (built-in) reliability of the process. Some of the more critical reliability-related layout rules include

1. Those that impact metal and contact electromigration

2. Those that impact the hot carrier-associated problems of threshold instability, avalanche breakdown, and bipolar latch-up

3. The combinations of design rules that control CMOS latch-up

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4. The isolation spacings and channel lengths that limit chip voltages due to punchthrough

5. Those for the input and output structures that determine electrostatic discharge (ESD) susceptibility

6. Those for guard-ring and scribe-line structures needed for contamination and moisture protection

These design rules are based on the results of a series of reliability evaluations. The validity of each of these sets of rules is verified under the combination of worst-case conditions for both critical dimensions and alignment.

Modern integrated circuit design is achieved via a computer that stores all of the required on-chip elements and vital electrical characteristics from a schematic viewpoint, as well as the elemental circuit dimensions, physical layout geometries, and critical fabrication parameters and dimensions. The IC designer then connects the various elements as chosen, in the manner required to achieve the desired IC function. A computer verification program checks the layout against the original circuit design. Next, rather than physically building a breadboard (prototype) circuit with its inherent limitation of inaccurate representation of the desired IC, the IC designer uses a computer to simulate the performance of the computer-generated design in software (called logic simulation). This method tests the design in software for logic functionality and proper threshold, current, and timing levels before committing it to a relatively lengthy production cycle. This shortens the overall process by limiting the scope and impact of the design iterations and restricting them to the very front end of the IC design procedure before fabrication begins, saving time and money.

Therefore, making use of simulation via software both provides circuit designers with the power to evaluate changes in the design without the lengthy procedure usually associated with a build cycle (designers can add or subtract circuitry and immediately evaluate the differences) and verifies circuit performance as a function of the process being used.

Once the circuit design and layout are verified as correct, the same computer database is used to generate the photomasks used for device fabrication, as well as the test vectors for ATE program generation. Automated techniques for generating both of these require several translations of the initial databaseand the possibility of introducing errors into the database and thus the masks and automatic test equipment (ATE) software test programs.

Since IC quality begins during circuit design, there are some critical issues that must be addressed in order to generate an error-free design:

Proper design rules and tolerances are required.

Accurate layout and positioning is needed.

Accurate circuit models, performance models, and process models are required.

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Accurate circuit simulations are required, including exacting and error-free software.

Design rule checks (both electrical and layout) must be performed accurately.

Accurate digitizing is required.

Sources of Error

IC Design and Manufacturing

The goal of the IC manufacturing process is to provide integrated circuits that satisfy the given specifications and meet customer requirements. There are a myriad places during the design, manufacture, assembly, and test flow at which errors or problems can occur.

At the logic design phase of the design and manufacturing flow, due to insufficient design verification and simulation, specifications may not be transformed into logic design data correctly and erroneous logic design data may be passed to the physical design phase.

At the physical design implementation phase, the logic and process model library may not be accurate, producing manufacturing errors. Another factor is that a physical design system, such as an artwork data generation program, might include bugs, so that incorrect artwork data may be sent to mask-making resulting in defective masks.

At the manufacturing phase, there are many causes of contamination (Chapter 11.) One of these is the dust in the air that may contaminate photomasks, thus causing defective chips.

During wafer probe, final electrical test, and quality control (QC) sample electrical test, errors can occur due to a number of reasons. These include

Inappropriate ATE (accuracy, precision, repeatability, and reproducibility)

Test system out of calibration

Test system/peripheral equipment malfunction

Test system waveform distortion

Logic simulator/ATE setup condition incompatibility (see Chapter 8)

Test software errors

Hardware/software incompatibility

Measurement errors

Performance board/load board/fixture defects and degradation

ATE Sources of Error

The high speed at which ATE operates allows tests to be run in a fraction of the time required with manual test sets, where test technicians themselves perform

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the interconnections, adjustments, and measurements, and record the test results. An improvement in quality normally takes place because of the transfer of control over the critical points in a test cycle from test technicians to a computer. This absence of human control means that the ATE performs each step in the test cycle internally, where the operators cannot observe them as they can on a manual test set.

After the test operator has initiated the test program, the only evidence that the ATE has executed the test correctly is normally a PASS or green light indication on a console display. But such an indication fails to prove that the device under test (DUT) actually passed the test, nor does it mean that the ATE even performed the test. Thus, while the high speed and absence of human control provide many dividends in quality, productivity, and lower per-unit testing costs, they also create problems for quality and test engineering personnel who must assure the quality of the final product. To assure that the ATE correctly tests ICs, the following are required:

1. Hardware and internal operation of the ATE must be correct, precise, accurate, repeatable, and reproducible.

2. ATE software programs must be correct, the sequence in which test vectors are applied must make functional, electrical, and thermal sense, and the software must be compatible with the peculiarities of the hardware.

Sources of Testing Errors*

The hardware-software combinations of ATE systems present complex possible causes of error or failures that occur when testing integrated circuits. Some of these are summarized in Table 13.1. Not listed are the failures due to circuit design errors and manufacturing/processing-induced errors.

Test system malfunction can be a cause of errors in testing ICs. Though they are certainly very scarce, there can be tester hardware design errors. More common is unsatisfactory calibration in timing and electrical characteristics of drivers/comparators. Furthermore, tester malfunctions can be caused by external sources such as AC input power noise or mechanical equipment malfunction (tape drive, disk, etc.).

Test software errors can occur as a result of the wrong test model, including database tape errors, test software generation system error, design rule violation, and test program error.

A wrong test model could be generated as the result of several factors. One of them is wrong design data, including discrepancies among IC specifications, logic design data, and physical design (process) data. Another reason is

*Portions of this section are from Ref. 1, with permission.

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having the wrong IC cell block description in a cell block library. It may be a function error or a timing error. Other than those, manual input signal assignment can result in test model errors. For example, a partitioned circuit model may be erroneous, when input signal assignment to realize partitioning has to be specified manually. Similarly, when degenerated models are used for large function blocks, such as RAM (random access memory) blocks, manually specified input signal assignment may not establish the required conditions.

Test software generation system error can be caused by software bugs, even though significant advances have been realized in the field of software verification. Design rule violations can sometimes be a cause of wrong test software. An example is incorrect implementation of design-for-testability (DFT) approaches, such as a scan path. Scan path is a methodology of Design for Testabilityan entire body of knowledge.

Measured errors occur as a result of both hardware- and software-related issues. Hardware issues include tester accuracy, precision resolution, repeatability, calibration, and test head limitations as well as usage wear of the test socket. Test program errors can result in measurement errors.

Some of these issues involving the ATE (tester) environment are now addressed.

Signal Integrity (Quality)

Performing DC and AC parametric measurements of high-performance digital ICs involves many areas of concern, especially those relating to signal quality and integrity: proper trace and line termination, use of short lines (an 8-in line results in a delay of 1 ns), tester pin electronics physical implementation, etc. These must be addressed based on the interface relationships between the IC circuit function, the technology characteristics (CMOS, TTL, and ECL), and the ATE test head (pin electronics) [2]. Elaborating somewhat further, the accuracy (or inaccuracy) of VLSIC ATE requires strict adherence to proper termination of transmission lines leading to the comparators. Timing errors become serious when there is a mismatch of the output impedance of the DUT and the transmission-line impedance [3]. The limit to timing measurement accuracy is defined by the characteristic impedance of the capturing device (latch or flip-flop) [4].

Proper ATE fixture design and implementation (including quality high-frequency sockets and contact set) in a high-speed environment is critical to obtaining accurate measurements [2,3,5,7], as is bench fixture correlation [6]. Driver signal, DUT loading, and observed waveforms all require special attention.

The many internal ATE drive signals required to thoroughly test an IC are often subject to capacitive, resistive, and inductive loading, and switching events generated internally (such as the opening or closing of a relay or hundreds of

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relays) or coming from the raw AC power. These events are manifested as conducted, generated, or radiated noise, and adversely affect the quality of the signal going to the DUT. Additionally, signal fanout over large distances also affects the signal quality. The resulting signal skews, slow rise/fall times, excessive overshoot, and noise can cause improper cell addressing (in a memory), resulting in nonrecurring (i.e., soft) failures.

Signal quality relates to both timing and level. Signals must cross the thresholds at the prescribed time, with no extraneous excursions across the threshold, the signals and signal edges must be properly referenced, and the signal must not exceed the operating range of the IC under test's input. Figure 13.1 shows the typical factors that affect waveform signal quality.

Timing uncertainties arise from overshoot/undershoot, and noise controlled by the design of the internal ATE PC boards, pin electronics cards, and the signal drivers. Skew is a major factor in most systems. Skew results from the unequal delays through drivers and signal paths. In order to accurately place a signal at a particular point in time, individual and bank delay adjustments are typically required. The impact of skew, with rise and fall times, directly affects the ability of the system to approach the desired operational speed of the device under test. Thus, in order to test a complex IC properly each of these factors (overshoot, undershoot, skew, and noise) must be controlled, or erroneous and misleading results will be obtained.

ATE Accuracy

With the increased levels of performance achieved by VLSI circuits, tester accuracy is extremely important and should be guaranteed by both system specifications and automatic timing calibration software. The DC accuracy is

Figure 13.1
Factors that affect signal quality.

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determined by the power supply accuracy and stability and calibrated loads. The overall system timing accuracy consists of the sum of the two primary individual accuracies, driver skew and comparator skew, each of which is composed of several elements. Driver accuracy includes all clock, address, and data drivers, while the comparator accuracy includes data on single and multiple comparators. The individual accuracies are as follows:

1. Strobe placement accuracy.

2. Rising and falling driver edge placement specifies the test system's ability to accurately and repeatedly produce an edge transition at some programmed value. The accuracy specification should include the worst-case number of both the rising and falling edges.

3. Driver linearity (measured at all increments of the delay lines) specifies the driver placement accuracy over the full range of linearity of the delay lines which derive the timing system resolution.

4. Driver skew (measured for all formats) specifies the test system's ability to produce all driver edges accurately when programmed to the same value.

5. Input/output switch driver accuracy (placement and skew) specifies the accuracy of the data drivers through the I/O FET switch.

6. Driver multiplex accuracy (placement and skew).

7. Comparator accuracy (rising and falling edge detection) specifies the test system's ability to measure an edge transition accurately and repeatedly, as measured at the rising and falling edge's 50% points.

8. Comparator linearity specifies the comparator's ability to measure an edge transition accurately over the full range of input levels and comparison trip points.

9. Comparator skew specifies the ability of all comparators to measure the same edge transition accurately.

10. Comparator saturation (large voltage swings) specifies the comparator's ability to measure rising and falling edge transitions for large voltage swings.

11. Window strobe accuracy at minimum pulse width.

12. Jitter.

Test system manufacturers specify overall system accuracy in terms of driver-timing accuracy and comparator-timing accuracy. It is not, however, as simple as that. Overall system accuracy is very difficult to specify because it is very difficult to measure. To specify accuracy, it is necessary to perform exhaustive characterization studies under many operating conditions.

The major purpose of accuracy in ATE is to increase product yield. The more accurate the test, the fewer the uncertainties. The fewer errors made by ATE, the smaller the testing guard bands, or gray areas, which means fewer

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good devices will be rejected (Type 1 errors). A by-product of accuracy is better grading or product sorting.

Accuracy is the degree of exactness possessed by a measurement; it is a measure of the quality of freedom from error. A high degree of accuracy implies a low degree of error. Accuracy should not be confused with precision or resolution. Accuracy denotes the absolute quality of measured results, while precision refers to the degree to which measured results reflect the theoretical values. A 20-ps resolution timing system may be less precise than a 10-ps resolution timing system; nevertheless, the measurement results of a 20-ps system might be more accurate than the results obtained with a 10-ps system that contains errors.

In ATE, a timing error is the difference or variation (uncertainty) of a controlled unity value compared with what it should have been. The control unit may be a reference delay line or a gold device.

When making IC timing measurements the errors may be due to unavoidable random disturbances or to the use of finite approximations. The approximations contain errors due to test circuit and other measurement uncertainties, computational errors, and even human mistakes. For these reasons a measurement guard band as shown in Fig. 13.2 is essential. Guard bands provide the margin of safety against bad devices being processed as good (Type II errors).

Test system accuracy is required by IC supplier and user alike. High accuracy allows the early detection of any variance in process control values that would adversely affect product quality. The device designer needs high accuracy to determine the device's operating range during the characterization process, and to determine whether the device meets its switching specifications. The IC user needs high accuracy to ensure that the specifications being purchased are actually being met, especially if the user is relying on the device to closely meet the timing values required by the final product. If the device operates too slowly, unacceptable differences in designed timing relationships could easily result in race conditions. Conversely, a device that operates too fast could cause equipment/product problems as well.

Several factors that affect AC measurement accuracy are ATE test head capacitance and edge placement. These are now discussed.

Measurement Errors and Test Head Capacitance

A serious testing problem may be encountered if long cables are used to connect a high-pin-count device to the test system. With current high-performance ICs a hard connection between the IC and test system and between the test head pin electronics and the mainframe is ideal, but not always practically realizable, since there is then no cable loss and thus no loss of signal integrity. A pin electronics circuit has both resistance (R) and capacitance (C). An applied voltage signal will have a rise time of 2.2 RC for 1090% of its amplitude (or 1.4

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Figure 13.2
Guard-band testing.

RC for 2080% points). If a coaxial cable or transmission line is attached to the pin electronics, the output signal TR will be 2.2 times the characteristic impedance of the transmission line (ZO) multiplied by the load capacitance (CL) for the 1090% points, i.e., TR = 2.2 ZO CL. This is shown in Fig. 13.3.

When testing, if the length of the transmission line does not exceed 2TR, rise time will not be significantly affected. As the load capacitance becomes small, the rise time of the output signal will start to equal the rise time of the pin electronics output. Although rise time is not adversely affected by the cable length, signal integrity is. Distortions due to reflections will exist when the DUT pin is an output, but may be reduced if the transmission line is properly terminated.

This analysis is also true when the tester is driving the device as well as when the device is driving the tester. These are fundamental physical laws that cannot be altered by any pin electronics design. Additionally, the DUT often lacks the capability to drive a transmission line. A 5-V pulse applied to a 50-W back-matched transmission line requires 50 mA of current from the DUT. The

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Figure 13.3
Typical pin electronics circuit rise time.

higher the resistance, the easier it is to drive the line, but the trade-off is rise time.

For CMOS devices, the rise-time trade-off of a 93-W environment, which is easier to match to high-impedance devices, requires less edge current drive, has lower capacitance, and is preferable. CMOS output circuits are designed specifically to drive small capacitive loads. A poorly terminated transmission line on the DUT output will appear capacitive. In fact, high or varying tester pin capacitance compromises both DUT performance and measurement accuracy. In this situation a 93-W line is less capacitive than a 50-W line.

Therefore, the input capacitance of the comparator is an important pin electronics parameter for device testing. The DUT output must drive the tester comparator circuitry. Hence, the tester environment must provide low capacitance, high bandwidth, and high-impedance comparator circuits for testing high-pin-count devices.

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If transmission lines are employed to interconnect the devices and tester comparators, and if the total capacitance exceeds 20 pF (picofarads), the device may not be able to drive the circuits properly, and measurement errors of as much as 10 ns can be expectedeven if the test system is deskewed and adjusted to picosecond accuracy. This error is magnified when the device has a high output impedance such as CMOS.

The other issues associated with driving high-capacitance circuits (3050 pF and greater) are test throughput and power dissipation. The higher the capacitance that must be driven, the longer the test time for float state testing, and the greater the power that must be dissipated by the DUT. The elongation of the tester period required to detect float states is directly proportional to load capacitance. Similarly, power dissipation on each output pin is proportional to CV²f.* High test head capacitance compromises device output waveform integrity, which is exactly what the tester is measuring, and it restricts clock and data rate performance.

For these reasons and to reduce uncertainties in the testing process, a low-capacitance test head with the pin electronics circuitry close to the DUT, especially when probing or handling the device automatically, is mandatory.

Edge Placement Accuracy and Data Rates

Just because a particular test system has a 40-MHz data rate does not necessarily mean it can guarantee that a given IC runs at 40 MHz. Let us look at an example to see how this works.

Referring to Fig. 13.4(a), the ideal device environment, assume that the SET UP TIME edge (ts) is the reference edge when testing a typical part. There are five other edges referenced to it: HOLD EDGE (th), PULSE WIDTH HIGH (tpwh), the leading edge of tpwh, which is PULSE WIDTH LOW (tpwl), PULSE DELAY (tpDLH), and the TESTER STROBE (tmin), which represents the minimum DUT operating time. If the part is a 40-MHz part, it will have a specification of 25 ns. To guarantee this, the calculation is 25 ns + (the edge placement accuracy the number of edges) = the guaranteed specification for the part.

In Fig. 13.4(b), G1 through to G6 are the tester guard bands for each edge, and their individual widths are a function of the tester edge placement accuracy. With a tester edge placement accuracy specification of ±700 ps and a load capacitance of 40 pF in a 93-W environment, the best-case tpd (tpd = propagation delay, a timing parameter on IC supplier data sheets) guarantee is 25 ns + (0.7 ns 5) + (93 W 40 pf) = 32.2 ns.

Under these conditions, due to tester uncertainties caused by both edge placement accuracy and the output RC effect, the specification of the 40-MHz part would have to be reduced to 31 MHz. To guarantee the part to 40 MHz

*CV²f = Capacitance times voltage squared times frequency.

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Figure 13.4
(a) Ideal device environment. (b) Reducing the specifications to account for
uncertainties and output RC effect.

would require the part to actually run at 17.8 ns or 56.2 MHz. In other words, a higher speed device would have to be selected to account for the tester uncertainties if the part must be guaranteed at 40 MHz. If the tester uncertainties are simply ignored, then the device yield would be reduced and many good devices would be classified as defective (Type I error).

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On the other hand, with an edge placement accuracy of ±250 ps, and a load capacitance of 22 pF in a 93-W environment, the best-case guarantee is 25 ns + (0.25 ns 5) + (93 W 22 pf) = 28.3 ns or 35.3 MHz. To guarantee the part to 40 MHz would require the part to actually run at 21.7 ns or 46 MHz.

At-Speed Testing

The increased operating speeds of digital ICs plus the demand for ever higher quality require that the IC manufacturer test these parts at the highest specified clock speed. There are some defects that at-speed testing will find that slower speed functional testing will not.

The first is a masking defect in a CMOS or BiCMOS IC. This defect disables a gate in a parallel-gate driver circuit and could be caused by a small particle that prevents the metal from making contact with an N⁺ region. The effect is that the driving signal does not connect to the gate input.

With one of the parallel gates disconnected, the IC cannot drive the output as well as it could with all gates working. Depending on the load on the output, this can increase the falltime seen at the output and cause the IC to fail at high clock speeds. The IC would pass functional tests at slower clock speeds because there is more timing margin at the slower speed.

Resistive vias are a second type of defect that can cause timing problems. Processing that fails to remove all the oxide on a particular layer causes resistive vias. The remaining oxide may have a resistance of hundreds of ohms. Resistive vias may occur on inputs, outputs, or anywhere on an IC.

Resistive vias also cause signal-propagation delays, which can cause the IC to fail at high clock speeds. One might find this defect with propagation-delay testing, but propagation-delay tests normally check a very small percentage of the total number of signal paths. So the chances are low that the failure will be found.

The third type of defect that can cause an at-speed test failure is a resistive short between the gate and drain of a MOS FET in a 2-input NAND gate. This short is the result of a defect in the gate oxide caused by a particle or a high-voltage stress, such as an electrostatic discharge.

An IC with this resistive short might fail an at-speed test because the short reduces the drive capability of the MOS FET, which slows down the part. An IDDQ test might catch this defect and, if the short is low enough in resistance, a low-speed functional test might also catch it. These shorts typically have a very high resistance, however, so the chances of finding the defect with either test is low.

The final example of a problem that can cause high-speed failures is excessive crosstalk. Crosstalk occurs when a signal on one metal layer or path induces a current in another metal layer or path. There is always some amount

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of crosstalk in CMOS circuits; the question is whether or not the crosstalk causes the circuit to fail.

Ideally, one would find crosstalk problems by simulating the circuit layout before production begins. Simulation is not an exact science, however, and many models are not accurate at high frequencies. Process variations can cause crosstalk problems, too. To find the defects caused by the process variations, one must test at rated clock speeds.

Thus, by not testing at speed, there exists the potential of shipping defective devices to customers. However, at-speed testing is not a simple matter. Different ATE and fixturing is required, calling into play a host of complex and interacting issues.

ATE Hardware Integrity

A number of methods are available to increase confidence in the integrity of the hardware and internal operation of the ATE. Some of these include

1. The ATE should be maintained and calibrated at regular intervals.

2. Periodically use a self-test program to assure the correct operation of the test equipment, the interconnection device, the computer, and the internal wiring and connections.

3. Routinely use gold units of a specific device type to verify the correct operation of the test equipment by reading and recording the critical electrical parameters of that device, and comparing these measurements with the originally recorded measurements of the same physical units (gage R&R studies).

4. The computer displays hardware operations as they occur to assure that each operation is performed correctly. For example, if the ATE adjusts the output level of an oscillator to a certain value, the level can be displayed as it is adjusted toward the final value, allowing the operator and/or engineer to observe this operation.

Test Equipment Guard Band Requirements and Uncertainty*

A typical parameter that a test system must measure is diagrammatically shown in Fig. 13.5. The figure illustrates the error budget that must be considered when a parameter (for example, the logical zero current of a digital input) is measured. The typical value is indicated in Fig. 13.5. The measurement inaccuracy consists of two components.

1. The instrument error: This error component lumps both the measurement error of the instrument and the reflected error in the device forcing functions.

*From personal correspondence with S. Millman, Motorola SPD, 1992.

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Figure 13.5
Typical ATE guard bands.

2. The measurement uncertainty: This error includes the uncertainty in the measurement of the instrument and the reflected uncertainty from the noise in the forcing functions. The measurement uncertainty is typically defined as a standard deviation parameter 6s. In order for a test to meet a customer rejection rate of less than 3.4 ppm (parts per million) it is necessary to allow a 6s guard band.

An IC manufacturer generally has a quality control (QC) organization that sample-tests completed devices. These samples must be tested on the same type (manufacturer and model) of test system that is used by production. As a side note, testing or verifying high-performance ICs on a different test head of the same tester (multiple head tester) can provide different results, especially for timing parameters, than the initial measurement, due to test-head-to-test-head variations. The measurements must guarantee that the device will meet its specifications. It cannot make assumptions about the accuracies of any of the production test systems. If QC detects a bad device it will dictate that all of the devices in the lot be reverified by the production test system. It is unacceptable for QC to fail any parts in a sample lot and permit the production lot to be shipped without retesting because this could imply that the 3.4 ppm goal was not met. In order for production to guarantee that none of the devices that it tests will fail in QC, it is necessary that the production test systems be set to pass devices that have the limits tightened by three times the accuracy of the ATE. This triple guard banding requirement is illustrated in Table 13.2.

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Table 13.2 ATE Guard Banding Examplea

Case 1

Case 2

Case 3

Case 4

Case 5

Case 6

Actual value
1.001
1.011

0.999

0.999

1.011
1.021

Test guard band
0.01
0.02

(Erroneous test)

(Erroneous test)

0.03
0.03

Low test limit
1.01
1.02

NA

NA

1.03
1.03

QC guard band
0.01
0.01

0.00

0.01

0.01
0.01

Low QC limit
1.01
1.01

1.00

1.01

1.01
1.01

Test measure
1.011 P
1.021 P

(Erroneous test)

(Erroneous test)

1.021F
1.031 P

QC measure
0.991 F
1.001 F

1.009 P

1.009 F

1.001 F
1.011 P

aSpecification: 1.0 < parameter < 1.2. Measurement error: ±1%. P, pass; F, fail.

In Table 13.2, the test measure and the QC measure rows have a parameter P or F for each entry to indicate that the tester either passes or fails the device. Case 1 emphasizes the fact that with normal single guard bands in both the test system and the QC system, devices can pass the test, but fail QCan unacceptable situation. Case 2 demonstrates the unacceptable scenario that occurs when double guard banding is used on the manufacturing test system and single guard banding on the QC system. Case 3 illustrates the inadequacy of having no guard banding on the QC test system, because that scenario fails to catch the fact that bad devices may have escaped screening in production, and still pass QC. Case 4 illustrates how such failures are picked up in QC if single guard banding is enforced here. Cases 5 and 6 illustrate how triple guard banding at test and single guard banding at QC properly identify failures so as not to pass devices in test but fail them in QC.

The value of the measurement uncertainty, s can generally be reduced by increasing device test time. The value of s can be halved, for example, by averaging four measurements. In general, the uncertainty of measurement can be reduced by a factor N, by averaging N² measurements. This can significantly affect total device test time. For this reason one of the major goals of test system design is to keep the unaveraged uncertainty as small as possible. Above a certain number of averages the uncertainty reaches a level that is not reduced by further averaging. There are several causes for the uncertainty floor, including the following.

1. The presence of alternation of hysteresis in the parameter being measured.

2. The presence of l/f noisea component of the noise that tends to increase as the test time increases.

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3. A situation where the parameter being measured exhibits several modes of operation.

4. The noise is not white or does not display a Gaussian distribution.

Noise is a phenomenon that is significantly affected by system architecture and, in particular, by the grounding structure of the system.

ATE Calibration

The ability of a test system to perform consistent measurements over and over is known as repeatability. Repeatability is a function of the inherent stability of the individual components constituting the test system.

Calibrating ATE, as with software verification, is critical to determining if ICs are in compliance with their data sheet specification limits and to detect ICs with manufacturing defects. Equipment that is out of calibration could result in good devices being rejected (Type I errors), as well as acceptance of devices with manufacturing defects (Type II errors).

The calibration of test and measurement equipment (ATE) is a mandatory requirement for producing high-quality ICs. Some of the relevant issues are listed below.

1. The need for detailed written calibration procedures and instructions.

2. The need for a predetermined calibration frequency (once a month, for example). The severity of expected usage, the sensitivity and delicacy of the equipment, the required accuracy in its application, and the results of past calibrations are used to determine the frequency of calibration.

3. The reference standards should be traceable to the National Institute of Standards and Technology (NIST).

4. The transfer standards should have the same resolution and accuracy requirements as the reference standards.

Thus, each company must answer the following question: How do your measuring instruments (ATE) and their calibration, or lack thereof, reflect the product you manufacture and ship? (Type I and Type II errors are discussed further in the Tester Repeatability section.)

Software Errors

Among the causes of difficulties in assuring ATE quality are the errors that exist in its software, specifically in the test program. Because of the complex nature of software it is difficult to verify that a test program correctly steps through each portion of the test cycle. A single error can cause unseen problems, resulting in good devices being rejected, bad devices being accepted, or even catastrophic device failure. Three actual situations are used as illustrative examples to show

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the effects of test program errors. In the first situation, a test required that a digital voltmeter (DVM) measure a DC voltage around O V (i.e., a digital TTL low level) on a certain pin of the DUT connector. The software program, however, incorrectly directed the interconnection device to connect the DVM to another pin, which was unconnected inside the DUT. As a result, the DVM always measured a voltage near zero. (It should be noted here that the same type of error could occur if the interconnection device is nonconforming or incorrectly installed, and connects the wrong pin to the DVM). This example also underscores the need to avoid measurements near O V whenever possible.

In the second situation, the test required that voltage measurements be made at three separate test points. The software program, however, contained an error that resulted in one test point being measured three times. Since the signal of the test point contained noise that caused the DVM readings to fluctuate, all the readings differed slightly and, thus, appeared to be different measurements. The fluctuation in readings helped to disguise the program error.

In another situation, the test program software could connect a power supply to the wrong device pin, causing an electrical overstress resulting in either a degraded device or a destroyed device. The internal ATE measurement system would correctly identify the part as being faulty. The point, however, is that the software error caused the device failure. As long as the software contained this error, device failure would be a recurring problem, severely impacting upon finished product yield and cost.

Software Backup

Software data and test data loss occur from either random bit error or human error. Sources of human error, which include inadvertently deleting a file, applying a disk formatting program to the wrong disk, or copying a disk or tape in the wrong direction, will destroy all data on the target disk or tape.

The most important precautions against data loss are the establishment and faithful maintenance of proper backup procedures. The overriding principle in software backup is that the version most likely to be needed must also be the easiest to use.

Three levels of backup software are not uncommon. When the primary copy of a piece of software fails, a backup must be substituted. However, because software changes frequently and data change constantly, the backup may not be identical to the original and needs updating before it can be used. The first level of software should require only a minimum of lost time and concentrated effort to restore the system to its predisaster condition. It should therefore be as close to the version on the primary copy as possible. Often this means backing up operating disks dailyin some applications several times a day. The determining factor is the quantity of information that one can tolerate losing should a problem arise. Updating from the second level, generally the previous generation of the

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first level, is more time-consuming and costly. (The first two levels are usually produced by backing up the primary medium onto two disks or tapes in rotation.)

The third level of software backup is normally the hard copy of the test program and test results data, and master copies of the various test station operating components (operating system, run-time languages, APG, data analysis package, etc.), from which a new disk can be assembled. The cost of recovering from the third level is quite high. Its only saving grace is that without it, recovery would be impossible.

Version Control

Implementation of the backup version of a test program during a recovery procedure without updating it could cause the incorrect failure of large numbers of ICs. The inadvertent substitution of an earlier version of an automatic program generator for a later one might mean that the resultant test program will not run on the current tester software.

One must therefore maintain scrupulous records of any alterations to the software, documenting the date and nature of the changes, whether during program or system debug or after release. This step permits the recreation of those changes, in the event that copies of subsequent versions are unusable. In addition, identified bugs can be more easily traced to ensure that they were not introduced in the most recent revision.

Software must comply with document control procedures. Different software versions must be uniquely identified, usually by a number representing the major revision followed by a decimal point and one or two additional digits signifying levels of minor revisions.

A production disk should carry a version designation (letter or number) with accompanying documentation of the revision of each of the software assemblies it contains. Reconstruction of that disk without certain knowledge of the revisions of APG, run-time software, etc., guarantees that the cost of recovery will be higher than necessary, even if eventually done correctly.

Causes of Software Errors

Errors in software normally arise from two sources:

1. Erroneous information provided to the programmer. If a test specification gives a tolerance that is wider than is actually required, for example, the programmer will test to that tolerance, and the ATE could pass nonconforming units (Type II errors). On the other hand, a tolerance that is tighter than required would cause the ATE to reject acceptable DUTs (Type I errors).

2. The programmers themselves unknowingly introduce errors into the program. They can do this by misreading test specifications, for

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example, or by making an error in the programming itself. Because of the length and complexity of programs, a programmer can recheck a program but miss subtle errors.

One method of increasing confidence in ATE software involves two phases. In the first, the programmer or test engineer is responsible for the complete documentation of the software including ATE configuration, test procedures, a description of the test program including extensive comments, test program consisting of test vector list, installation procedures, performance board/DUT board/load board schematic diagrams, and read-and-record data of all parameters of gold units demonstrating the capability of the software to perform the desired measurements. In the second phase, this documentation is given to the quality department for detailed review and verification.

Anomalies in the behavior of a test or networking system may go unnoticed because they occur infrequently, or because the only person to notice them is the equipment operator. A log of every instance of unusual behavior will help enormously to identify such problems, even if individual events are months apart. No observation should be considered too trivial to report. Often such trivialities, traced over time, will point to a subtle bug or small error in the software which would otherwise go unnoticed.

Procedures for recovery from ATE failure should be written down precisely to limit the possibility of missing a step and preventing the loss of additional data.

Small errors in computer memory or magnetic media should not be ignored. A bit error in the memory will proliferate onto the storage medium every time the faulty address is written to. Even soft errors (those that do not occur every time the location is accessed) should be identified and repaired whenever possible.

When an error appears on a disk, one should immediately copy all accessible files onto a clean (formatted) disk, then reformat the original disk to remove all logic errors, after which it can be reused. If the format operation generates hard errors, the disk should be discarded. If the error appears on a reel of tape, back up the files and discard the tape (or use it in noncritical applications). The sooner one acts, the more likely that all files can be recovered.

Should a medium become completely inaccessible, narrow down the cause of the problem with expendable software. Check out the disk on another system, make an additional copy of the primary backup, and use the extra copy on the suspect system.

Software Quality Assurance [8]

Software quality assurance is important because of the short time-to-market pressures of ASICs and the resultant short test vector generation time required.

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The later in the development process that an error is found, the more difficult and expensive it is to correct. Developing reliable software requires a structured quality assurance program from the very beginning of both the IC development process and the software design. This program ensures not only that functions work as planned, but that planned functions are useful.

Software quality assurance (SQA) can reduce the time spent on program maintenance by uncovering and eliminating potential problems while the software is still in the development stage. In addition, putting an SQA program in place throughout the software product development cycle minimizes time spent later in the costly and time-consuming process of program maintenance. Typically, there has not been a separate SQA function in software development departments; it has been common for programmers to perform their own QA evaluation, and to develop their own test tools. However, programmers/test engineers suffer from the bias of the work environment. Often, they are so familiar with the program and how it should operate that it is difficult to devise valid tests for unexpected glitches. Even very good programmers do not necessarily know how to test their software, due to lack of experience.

To avoid this situation, the SQA group should be the first critical user, apart from the software development team. This eliminates the bias of the programmer/test engineer and prevents critical omissions due to overfamiliarity with the product. Furthermore, SQA sets standards for software operation. A set of comprehensive standards ensures that the software product will be able to stand the test of time and field trials with actual customers. Therefore, tests devised by the SQA group should set up much more stringent conditions than those that will be encountered by users.

The establishment of an SQA team provides an independent, unbiased viewpoint from which to judge the functionality of a piece of softwareit furnishes experienced personnel who can deal with the problems that frequently occur in software development. Software review and testing must be an inherent part of the software development process. Ideally, software testing should exercise 8595% of a program's code to determine that it adequately fulfills the specification. Most software problems are due to either inaccuracies or omissions in the code, or from interactions that are not expected.

The SQA personnel review the software and verify the following: conformity to specifications, error handling (does the software identify errors?), boundary conditions, and deviations from standards.

Some software review and testing techniques include (1) static analysis, (2) dynamic analysis, (3) code inspection and review, (4) symbolic evaluation, and (5) formal proof of correctness.

Static analysis, which is extremely useful early in the software review process, isolates such software defects as unusual variables and functions, unexecuted statements, or type mismatches. The major shortcoming of static

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analysis is that it does not exercise the code in a manner that resembles actual use of the software.

Dynamic analysis exercises the software program using test ICs in order to exercise as much of the code as possible and verify its correctness. It involves both functional and topological testing.

Code inspection and review involves going through the entire software program line-by-line of code.

Proper error handling is tested by feeding incorrect instructions to the program and seeing if the software does indeed identify the errors. Whereas the conformity-to-specification testing checks to see if the program handles correct data properly, error-handling tests confirm that errors are correctly detected and reported.

Also, the SQA group must act as a data history repository for the software product, from inception to final release. Since revisions are inevitable, SQA must fully document all changes to the software over time. It should also confirm the proper operation of the software as these changes are made. An important point to remember, however, is that a correction or modification in one section of the system can impact upon other portions that have not been modified.

Tester Repeatability [9]

A great deal of attention has been placed on improving the test process in IC manufacturing environments. Efforts have focused on addressing two issues: passing bad parts (Type II errors) and failing good parts (Type I errors), as shown in Fig. 13.6. Industry reports [10,11] estimate that 3070% of VLSICs failed by the testing process are indeed good. These errors (Type I) are greatly affected by the repeatability of the tester.

Another study [12] of high-reliability, low-volume MOS ICs revealed that

Figure 13.6
Test model describing the four basic categories
of tested units.

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Type I errors accounted for 16.8% of all in-process test failures, qualification test failures, customer-reported next assembly, and field failures that were returned for failure analysis. The failure analysis that was conducted on every part traced the Type I errors to six primary causes arranged in descending order of occurrence and so plotted in Fig. 13.7.

1. Software program errors due to vector sets that place the devices in race conditions, or do not properly initialize the device prior to testing.

2. The tester itself; tester errors may be caused by a variety of reasons within the tester hardware, such as uncalibrated testers, defective tester hardware, or temperature and humidity changes within the test facility. These errors were listed as test anomalies: failures where the error cannot be determined.

3. Use of incorrect test acceptance limits that were more stringent than customer needs.

4. Operator error such as placing devices in the test sockets incorrectly or using the wrong test program, test limits, or test fixture.

5. Test fixture temperature sensitivity; leakage currents increase with temperature environments, inducing tester or continuity failures. Incorrectly constructed test fixtures are also a factor.

6. Intermittent continuity of the device/test fixture due to worn, dirty, or poorly designed test fixtures.

Let me cite some specific details. One IC that experienced 34.5% Type I errors contained both analog and digital circuitry that could not be consistently tested solely by digital testers. The Type I errors were mainly due to incompatibility between the device design and the available test technology of the company. Awareness of these failures allowed improved test routines that reduced the Type I error rate, but could not completely remove them.

Figure 13.7
Pareto chart of percent Type I errors identified by
numbers given in text.

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Another device type had 95% Type I errors, all of which were induced by an improper test routine or tester malfunction. A third IC experienced 77.8% Type I errors that were traced to improper acceptance limits for IDDQ (quiescent power supply current) tests that were tighter than the product specification, and to temperature sensitivity of the test fixture, which caused excessive leakage current during hot-temperature testing. The Type I errors were eliminated by correcting the IDDQ limits and redesigning the test fixture.

The Type I errors experienced by a fourth IC were tester-induced errors due to uncalibrated equipment. After recalibration, all devices were found to be acceptable.

Thus, it is important to know tester repeatability, and the only way to know tester repeatability is to measure it using known good (gold) units. These gold units should be selected carefully. They should be tested with a reasonable margin to the specification limits to ensure that the units are definitely good units. Figure 13.8 shows an example of the distribution of units suitable for use as gold units for a specific test.

Numerous tests are conducted on a device to ensure that it meets published specifications. A typical full device (IC) test set incorporates parametric, functional, and other tests, all of which may also incorporate a number of smaller test blocks as is shown in Fig. 13.9. In order for a device to be used as a gold unit, it should exceed all published specifications, which means the device should pass all tests with significant margins to each specification limit. A marginal device should not be used as a gold unit, because the marginality of the part could easily corrupt the measurement of tester repeatability.

A typical repeatability test is conducted by cycling full tests on a gold unit with a given tester. Repeatability is the ratio of the number of times the device fails a full test divided by the number of times the device is tested. For example, if a device passes 95 times out of 100, the tester is said to have a tester repeatability of 5%. The number of tests conducted on a device to determine repeatability depends on the accuracy desired.

Each individual test block could contribute to a poor (degraded) tester

Figure 13.8
Distribution of gold units for a specific
test. Notice that the distribution has a large
margin to the customer or test specifications.

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Figure 13.9
Sample test flowchart.

repeatability measurement. Therefore, it is essential that the test blocks contributing to a large repeatability are understood. For simplicity, each test block in a full test may be classified into one of two categories: (1) objective tests, and (2) marginal tests.

Objective tests are tests in which the device either passes or fails with very few marginal parts, as shown in Fig. 13.10. Open and short tests are good examples of objective tests. These tests are not greatly affected by a tester with poor repeatability.

Figure 13.10
Examples of objective test.

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Figure 13.11
Device/design process marginal test.

Marginal tests are tests in which either the tester deficiencies or the device specifications allow for only a small margin to the customer specifications. The process is so close to the customer fail specifications that any tester repeatability problem will be greatly magnified by yield losses. Tests that have the greatest impact on tester repeatability fit the marginal test classification. Figure 13.11 shows an example of a marginal test.

What Causes Marginal Tests?

The five primary causes of marginal tests are (1) unreasonable (tight) specifications, (2) device process marginal tests, (3) device design marginal tests, (4) tester calibration, and (5) tester measurement variation.

Many applications require tight specifications for selected parameters. These specifications are critical and require careful consideration. Process marginal tests can be the result of processing equipment that is not repeatable, or the result of a poor process design. Device design marginal tests are the result of a poor device design, or failure to follow design rules. Concurrent engineering and design-for-testability should be used to combat this type of issue.

Tests that are affected by a tester being out of calibration significantly affect repeatability measurements. Although the range of tester measurements may be quite small (Fig. 13.12), a calibration shift in the mean of the distribution of measurements will induce errors and inaccuracy.

A tester that has a great deal of tester measurement variation has a test distribution spread over a wide range as is shown in Fig. 13.13. The tester in this case might be calibrated, but its poor repeatability results in a high fallout. This type of tester could potentially pass a large number of failing units as a result of this problem.

There are numerous methods of reducing tester repeatability, including (1) design for testability, (2) continuous tester improvements, and (3) using software to improve repeatability.

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Figure 13.12
Test distribution for a test out of calibration.

Figure 13.13
Test distribution for a tester with high
variability.

Reproducibility

Closely related to tester repeatability is the issue of test operator reproducibility or the variation that is due to the effect of different operators using the same ATE. Excessive reproducibility signals a need for training and consistent procedures. In some applications, reproducibility might be defined as the effect of the same operator using different ATE to investigate differences between similar ATE. Reproducibility will then define the bias due to the different ATE, while the differences in repeatability define relative precision.

References

1. M. Kawai, T. Shimono, and S. Funatsu, Test data quality assurance, 1986 International Test Conference Proceedings, 811 September, IEEE, Washington, DC, 1986, pp. 848852.

2. J. D. Bray, ATE test head requirements for low-cost VLSI testing. 1986

Page 523

International Test Conference Proceedings, 811 September, Washington, DC, 1986, pp. 568591.

3. M. K. Barber and W. I. Satre, Timing measurements on CMOS VLSI devices designed to drive TTL loads, 1986 International Test Conference Proceedings, 811 September, Washington, DC, 1986, pp. 161168.

4. M. Keating, Fundamental limits to timing accuracy, 1986 International Test Conference Proceedings, 811 September, Washington, DC, 1986, pp. 756762.

5. S. Cohen, A new pin electronics architecture for high performance functional module testing, 1986 International Test Conference Proceedings, 811 September, Washington, DC, 1986, pp. 763770.

6. D. R. Simpkins, Testing Fmax in a production environment, 1986 International Test Conference Proceedings, 811 September, Washington, DC, 1986, pp. 771777.

7. Session 22: Using Test Systems at High Frequencies, 1990 International Test Conference Proceedings.

8. T. S. Closi, Software Quality Assurance: A Practical Approach, IEEE Computer Society Press (1989). R. Dunn, and R. Ullman, Quality Assurance for Computer Software, McGraw-Hill, New York.

9. R. J. Montoya, Using tester repeatability to improve yields, 1992 International Test Conference Proceedings, Baltimore, Maryland, 1992, pp. 270274.

10. T. W. Williams, Test length in a self-testing environment, IEEE Design and Test of Computers, April, 1985, pp. 5963.

11. R. H. Williams, and C. F. Hawkins, Errors in testing, 1990 International Test Conference Proceedings, Washington, DC, 1990, pp. 10181027.

12. R. H. Williams, R. G. Wagner, and C. F. Hawkins, Testing errors: Data and calculation in an IC manufacturing process, 1992 International Test Conference Proceedings, Baltimore, Maryland, 1992.

Page 525

14
Materials Issues*

Introduction

Throughout history, many technical advances have resulted from an increased knowledge of materials. This is particularly true with the development of semiconductor devices during the last four decades. There is every reason to believe that future developments will be even more dependent on our increased understanding of how materials behave. Well-founded knowledge of materials behavior will become more and more crucial for the design of durable integrated circuits.

Integrated circuits are precision composite structures that employ the following categories of materials:

Metals and their alloys

Insulators and dielectrics

Chemical compounds

Ceramics

Polymers

Semiconductors (elemental and compound)

*Some of the material in this chapter was developed by Dr. Billy Livesay, formerly of Georgia Institute of Technology.

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VLSI circuits are vertical thin-film sandwich structures consisting of a number of different elemental materials: Si, SiO₂, Au, Al, Cu, Ti, W, Ge, Ga, As, Pt, SiN, Mo, Ta, Ni, and P, for example. Figures 14.1 and 14.2 show these thin-film sandwich structures for several VLSIC configurations.

IC Material Properties

As a starting point, it is important to understand the fundamental properties of the many different materials used to construct an integrated circuit and how they differ from one material to another. Table 14.1 provides a listing of some of the relevant material characteristics categorized as electrical, chemical, thermal, mechanical, structural, optical, radiation and cross discipline effects. Table 14.2 through 14.5 and Figs. 14.3 and 14.4 present various listings of critical parameters for semiconductor materials, metals, ceramics and polymers. Table 14.2 lists the physical properties of several semiconductor materials; Table 14.3 the thermal and mechanical parameters for some of the metals used in IC manufacture; Fig. 14.3 the thermal coefficients of expansion for metals and ceramics; Fig. 14.4 the thermal conductivities of typically used metals; Fig. 14.5 the resistivities of these metals; and Table 14.4, the linear coefficients of thermal

Figure 14.1
Typical dimensions for a CMOS (thin-film) VLSI circuit.

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Figure 14.2
Vertical sandwich of thin film VLSIC structure. Four layers of single crystal silicon
were stacked one above the other by researchers at Matsushita to form an image
processor. Al, aluminum; Cr, chromium; N, nitrogen; Si, silicon; Ti, titanium; W, tungsten.

expansion of different materials. From these tables, notice the wide variation (differences) in the thermal coefficients of expansion, thermal conductivities, Young's modulus, and resistivities of several widely used IC fabrication materials: aluminum, SiO₂, silicon, and epoxy resins.

For example, from Fig. 14.3 it is seen that the thermal coefficient of expansion of aluminum is almost 10 times that of silicon. Thus, as the operating temperature of an IC increases, the aluminum experiences very large compressive stresses. This results in plastic deformation. When the temperature is again decreased, the now deformed aluminum film is subjected to large local tensile stresses.

These structures must remain mechanically, chemically, and thermally stable in order to accomplish their intended electronic functions over a reasonable lifetime. While the phenomena involved with the mechanical behavior of materials constituting an integrated circuit are not unique relative to their behavior in bulk form, there clearly are special geometrical considerations because of the small dimensions that currently exist in integrated circuits. These factors will become progressively more significant with still smaller feature sizes.

Wear-out mechanisms operate on circuit materials determined by basic materials characteristics and configurations and with the stresses experienced during either operation or storage. Certain defects accelerate the normal wear-out mechanisms, while others may introduce degradation mechanisms that otherwise

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Table 14.1 Material Characteristics

Electrical

Resistivity

Dielectric constant, dielectric strength (breakdown), etc.

Magnetic susceptibility, permeability, etc.

Band structures, band gap

Mobility

Wide range of device characteristics

Contact potentials

Chemical

Chemical activity for processes, degradation

Chemical bonding

Electron affinity

Phase diagrams

Chemical potential

Thermal

Melt point

Latent heats of phase transformations (fusion, etc.)

Thermal expansion

Vapor pressure; sublimation

Diffusion coefficient

Specific heat

Thermal conductivity

Mechanical

Elastic modulus (various)

Tensile strength

Elastic-plastic characteristics, yield point, etc.

Toughness, hardness

Fatigue durability

Poisson's ratio

Acoustical

Creep

Friction, adhesion, wear

Structural

Single crystal, polycrystal, amorphous, epitaxial, etc.

Crystal structure

Relevant crystal transformations

Relevant crystal defects

Optical

Fluorescence

Reflectivity

Refractive index

Electroluminescence

Birefringence

(Table continued on next page)

Page 529

Table 4.1 (Continued)

Radiation

Cross sections; neutron, ionizing radiation

X-ray absorption, fluorescence

Radiation damage effects

Scattering

Cross-Discipline Effects

Magnetomechanical (Magnetostriction)

Chemomechanical; stress corrosion, corrosion fatigue, etc.

Electrochemical

Mechanoelectric (piezoelectric)

Electro-optical (photovoltaic, photoelectron, photoelectrolysis)

Electro-optical; laser, LED (light emitting diode)

Magneto-optical

Thermoelectric

Thermomechanical; expansion-contraction, glass transitions

would never have occurred in the part or circuit. If an integrated circuit does not operate electrically when initially tested, then the presence of a defect is obvious. However, a circuit may initially operate properly, yet have a material weakness.

The materials making up an integrated circuit are not in a state of equilibrium with one another, so that a circuit structure is destined to change with time. Particular manufacturing mistakes may result in flaws that directly reduce strength, accelerate atomic migration or corrosion, or otherwise create another problem in a critical region of the circuit. In addition, defects often create stress concentrators, which further enhance the rate of degradation.

Epoxies and other polymers are used for die attachment and for encapsulating the die/lead-frame combination in the manufacture of integrated circuits. In addition to providing many benefits, polymers

May evolve a number of chemical agents that attack circuit materials.

Will not prevent moisture from reaching circuit metals. Moisture tends to reside at polymer-metal interfaces. Table 14.5 lists the moisture permeability of various polymers.

Have glass transitions that can introduce large mechanical stresses.

Have as great as a 20-fold difference in thermal expansivity between silicon and epoxy resin, resulting in thermal stresses that can lead to mechanical failure, strain-induced increases in permeability, and strain-induced chemical reactions.

Polyimides are also used in the IC manufacturing sequence, especially as die overcoats. Table 14.6 lists the typical physical properties of polyimides.

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Table 14.2 Physical Properties of Several Semiconductors and Diamond

Material

Density (g/cm³)

Hardness (kg/mm²)

Flexure strength (kpsi)

Young's modulus (GPa)

Poisson's ratio

Thermal exp. coef. 10⁻⁶/K at 23°C

Thermal exp. coef. 10⁻⁶/K at 200°C

Specific heat (J/g K) at 23°C

Thermal conductivity (W/cm/K)

Fracture toughness (MPa/m²)

Band gap (eV)

GaAs

5.32

700

8

85.5

0.31

5.7

6.4

0.345

0.53

0.43

1.43

Si

2.33

1150

18.5

130.1

0.28

2.3

2.9

0.758

1.41

0.95

1.12

Ge

5.32

850

13.5

103.3

0.28

6.0

0.310

0.60

0.66

0.67

Diamond

3.52

9000

427

1050.0

0.16

1.0

2.0

0.515

26.00

2.00

5.40

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Table 14.3 Thermal and Mechanical Parameters for Materials Used in Integrated Circuits

Temperature coefficient of expansion × 10⁻⁶ (°C)⁻¹

Material

Crystal structurea

200 °K

300 °K

500 °K

Thermal conductivity (W/cm/K)

Young's modulus (N/m² × 10¹⁰)

Aluminum
FCC

20.0

23.2

26.4

2.4

7

Copper
FCC

15.1

16.8

18.3

4.0

12

Gold
FCC

13.4

14.1

15.0

3.1

8.1

Molybdenum
BCC

4.6

5.0

5.3

1.4

29

Nickel
FCC

11.0

12.7

15.2

0.9

21.4

Palladium
FCC

10.8

11.6

12.6

0.7

16.7

Platinum
FCC

8.4

8.9

9.5

0.7

16.7

Silicon

1.3

2.5

3.5

1.5

Tantalum
BCC

6.3

6.5

6.8

0.54

18.6

Titanium
HCP

7.2

8.5

9.8

0.2

11.6

Tungsten
BCC

4.1

4.5

4.6

1.7

36

Kovar

(5.0)

Al₂O₃

(4.65.5)

(7.17.8)

0.4

31

SiO₂ (vitreous)

0.1

0.42

0.56

0.014

7.3

Glass (pyrex)

(7.89.7)

0.010

6.2

Lead-tin (solder)

(25.1)

aFCC, face-centered cubic; BCC, body-centered cubic.

Source: Values are taken from the Handbook of Chemistry and Physics, Chemical Rubber Publishing Co., and the American Institute of Physics Handbook, McGraw-Hill.

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Table 14.4 Coefficients of Thermal Expansion, Linear

Material

CTE (×10⁶/°C)

Silicon
3.2

Germanium
6.0

Alumina
6.5

Glasses
810

Steel
1012

Gold
14

Copper
17

Aluminum
24

Filled epoxy resins
1517

Filled silicone resins (no solvent)

30

Filled phenolic resins
35110

Epoxy resins (unfilled)

6070

Phenolic resins (unfilled)

80110

Silicone resin (unfilled, no solvent)

125

Polyurethane resins, flexible (unfilled)

150

Silicone rubbers
170250

Silicone gels
300400

Degradation

Reiterating, a wide variety of materials is employed in the construction of an integrated circuit. A single integrated circuit normally consists of several different metals and alloys, ceramics, oxides, dielectrics, one or more polymer material configurations, semiconductor crystals, etc. Circuit-board assemblies involve an added range of materials including composite structures, thin copper striplines, solders, various types of circuit components, and connectors. The net result is an extraordinarily complex array of precise structures incorporating the physical and chemical characteristics of all the circuit materials used. There are large numbers of interfaces between the materials within the circuit structure, which must reliably accommodate a range of differences in material parameters.

Electronic materials are subjected to a range of physical (mechanical,

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Table 14.5 Moisture Permeability of Various Polymers

Material

Temperature (°C)

Permeability [cm³(STP)/s-cm-atm × 10⁶]

Silicone

38

8.4

Silicone RTV

25

240

20100

Silicone junction coating

25

36190

Polyurethane

25

616

25

1.75.2

25

53

Epoxy, anhydride

25

4.8

Epoxy, amine

25

3.6

Epoxy, amine

25

3.27.5

Epoxy, amine

25

2.93.4

Epoxy, commercial

37

0.64

60

0.98

60

1.2

Epoxy, commercial

38

0.26

60

0.62

Epoxy, experimental

38

1.16

60

0.26

60

0.38

Phenolic

60

0.11

Poly (diallyl phthalate)

69

0.88

Poly (ethylene terephthalate)

39

1.7

Polycarbonate

25

20

25

0.67

Polytetrafluoroethylene

40

0.23

23

0.064

60

0.11

60

0.100.22

Polychlorotrifluoroethylene

38

0.028

Polychlorotrifluoroethylene

30

0.11

Polyethylene copolymer

45

0.13

Polyvinylfluoride

25

1.4

38

0.26

60

0.66

60

1.4

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Figure 14.3
Thermal coefficient of expansion for metals and ceramics employed in ICs.

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Figure 14.4
Thermal conductivity of metals employed in ICs.

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Figure 14.5
Resistivity of metals employed in ICs.

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Table 14.6 Properties of Typical polyimide Dielectrics

Dielectic constant (1 MHz)

3.5

Dielectric loss

0.002

Volume resistivity

10¹⁵

Dieletric strength (kV/mm)

300

Coefficient of thermal expansion (10⁻⁷/°C; RT to 400°C)

450

Decomposition temperature (°C)

>450

Tensile strength (MPa)

130

Tensile elongation (%)

20

Young's modulus (GPa)

3.3

Density (g/cm³)

1.38

Moisture absorption (%)

2.0

Impurities (ppm)
Na
K
Ca
Cu
Fe
Cr
0.4
0.1
0.3
0.1
0.1
0.1

Source: Data from R. R. Tummala, R. W. Keys, R. W. Keys, W. D. Grobman, and S. Kapur, Microelectronics Packaging Handbook (R. R. Tummala and E. J. Rymaszewski, eds.), Van Nostrand Reinhold, New York, 1989, p. 703.

electrical, thermal, and chemical) stresses during wafer fabrication, assembly, evaluation, storage, and application. Figure 14.6 shows an example of the stress built into an IC during wafer fabrication. The cross-sectional SEM photomicrograph shows the areas of high built-in stress in the uppermost deposited oxide layer at the edges of the via structure. Also shown are the grain structures of the two aluminum metal layers and the striations in the deposited oxide layer. A circuit can continue to function electrically only if structural integrity is maintained throughout its desired life.

The IC use (application operating environment) conditions in conjunction with the material properties of these composite structures can subject the various materials and their interfaces to stress conditions that lead to degradation mechanisms and in extreme cases device failure. Degradation and failure mechanisms can be defined as

Degradation mechanism: material processes acting to alter the configuration or properties of the materials in a device structure such that operational characteristics become less desirable.

Failure mechanism: the degradation mechanism, or mechanisms, that contribute to device failure.

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Figure 14.6
SEM photomicrograph showing stress in the deposited oxide layer.

The degradation mechanisms found in IC materials include

Corrosion; various chemical reactions

Mechanical overstress

Crack initiation/propagation

Intermetallic diffusion

Mechanical fatigue

Stress-corrosion cracking

Current-density-induced atomic transport

Electric-potential-induced atomic transport

Decomposition of polymer materials

Moisture diffusion/migration

Figure 14.7 depicts various possible corrosion mechanisms, while Table 14.7 lists some typical degradation mechanisms with more specificity.

Dislocations

Dislocations are linear defects in a crystal lattice (see Fig. 14.8) that move easily on preferred slip planes; for face-centered cubic (FCC) crystal, the favored slip planes are (111) wafers. Dislocations are responsible for practically all plastic

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Figure 14.7
Schematic illustrating different types of corrosion mechanisms.
(Courtesy G. Wranglen.)

deformation of metals and alloys. For very small geometry devices (ICs), fast dislocation movements combine with other dislocations or defects, resulting in the creation of voids.

Dislocation motion is affected by

The lattice

Material interfaces

Surfaces

Grain boundaries

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Table 14.7 Examples of Degradation Mechanisms

Chemical dissolution, specific atomic activity

Mechanical cleavage fracture

Interatomic diffusion across an interface

Galvanic-potential-induced atomic displacement leading to growth of dendrites

Electric-current-induced excessive atomic displacement leading to void and hillock growth

High lattice excitation with Joule heating and resulting enhanced atomic mobility, melting

Atomic migration along surfaces, grain boundaries

Formation of specific chemical compounds due to presence of particular chemical agents

Note: Some of these so-called degradation mechanisms are also some of the most useful manufacturing processing mechanisms. For example, one may use chemical dissolution mechanisms to etch away layers to create IC or PWB traces, employ controlled fracture to separate individual chips from a wafer, and control particular chemical reactions to create dielectric layers.

Other dislocations

Precipitates

Applied shear stresses

Chemical agents

Intermetallic compounds

Figure 14.8
Schematic showing crystalline defects. (Courtesy J. J. Gilman.)

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Mechanical Defects

The materials normally used in IC construction are principally chosen on the basis of their electrical performance coupled with manufacturability characteristics. However, many of the materials employed as conductors, dielectrics, and semiconductors are intrinsically weak as structural materials. The use of these materials in conjunction with small feature sizes, large and complex chips and packages, multiple layers with complex material interfaces, and crystallographic defects can lead to the defects listed in Table 14.8.

Typically, IC structures have large ratios of interface surface area to circuit volume. Table 14.9 lists some of the interfaces found in integrated circuits (see also Fig. 14.9). It is the characteristic of these interfaces (including surfaces) in composite IC structures that are critical to the reliability and durability of the resultant circuit.

Stress Concentrators

Most types of stresses either will activate or will accelerate degradation mechanisms. Certain circuit features, including faults, act to greatly concentrate stress at particular sites. Degradation mechanisms can correspondingly be greatly accelerated at such sites. Sharp notches (Fig. 14.10), cracks, voids, precipitates, or intermetallic compounds (Fig. 14.11) may serve as mechanical stress concentrators. Fatigue cracks generally grow from such stress concentrators.

Griffith proposed that the energy necessary to initiate or increase the size

Table 14.8 Typical Mechanical Defects in Electronic Circuits

Overbonded, underbonded wire bonds

Misplaced wire bonds

Scratches, voids, cracks, etc. in thin-film interconnections, dielectrics, chips, wires, etc.

Improper solder joints, including embrittled solder due to intermetallics

Thin oxide step coverage

Thermal-mechanical misfit between circuit materials

Incompletely cured polymers

Interface impurities

Inadequate bonding between metallization and substrate

Precipitates and other hard particles within metal films, wires, and interfaces

Poor die attach

Necked-down leads at package

Cracks in glass or ceramics of package insulators

Grain boundary segregation at package weld interfaces

Loose conducting particles

Plating defects

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Table 14.9 Interfaces in IC Structures

Surfaces

Surface-gas

Surface-vacuum

Surface-chemical agents

Semiconductor-metal (see Fig. 14.9)

Semiconductor-dielectric (see Fig. 14.9)

Metal-metal

Metal-dielectric (see Fig. 14.9)

Metal-polymer, dielectric-polymer

Grain boundaries

Dispersions, precipitates

of a crack is that of the increase in surface energy, or the product of the surface energy density (gS) and the total area of newly created surfaces [1]. This is balanced by the decrease in potential energy in the form of stored elastic strain energy and the work done by external stress sources. Figure 14.12 shows a typical stress-strain curve in which the elastic region and onset of plastic deformation are identified.

Fast fracture is propagated after initiation at stress concentrators.

The operating environment of materials in integrated circuits generally involves a superposition of mechanical, thermal, electrical, and chemical stresses. It is therefore important to consider the synergistic effects of more than one of these stresses acting simultaneously. Numerous examples demonstrate, that this synergism can greatly enhance degradation rates. Let's look at the issues, first of mechanical stress, then of thermal stress caused by thermal shock, and finally of chemical stress.

Mechanical Stress

Mechanical fatigue damage in metals is the result of cyclic stresses and strains that produce permanent damage to the material. Damage is sustained on each

Figure 14.9
Metallization over oxide step.

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Figure 14.10
Crack in metallization at step.

cycle and can cause failure at loads well below those necessary to cause failure under non-cyclic conditions. The following are some of the important factors affecting fatigue damage mechanisms:

Surface roughness

Inclusions, voids, and formation of intermetallic compounds

Impurities and corrosion agents

Temperature

Solder composition

Relevant interfaces

Strain rate

Figure 14.11
Potential locations for crack initiation: (A) at solder surface or
interface; (B) at internal particle; (C) at internal void; (D) at
intermetallic compound.

Page 544

Figure 14.12
Typical stress versus strain curve.

Strain range

Dislocation pinning

Dislocation pileups at grain boundaries and other interfaces

Formation of stable dislocation configurations (cells)

Dislocation interactions with inclusions; precipitates

Dislocation interactions with other slip bands

Formation of intrusions and extrusions by surface and interface slip

Deformation twinning

Initiation of microcracks

Crack growth, or joining of microcracks

Microenvironment interactions with surfaces

Stress concentrators

Mechanical stress-induced failures can manifest themselves in several different failure mechanisms. These include lifted ball bonds; shear stress-induced passivation and interlevel dielectric cracking and delamination; point stress-induced failures due to silica fillers in the plastic molding compound; and

Page 545

tensile stress-induced metal notching and voiding in the metallization. It has been demonstrated that mechanical stress is greatest at the die corners (Fig. 14.13). Consequently, any active devices and circuitry and wire bonds located in these areas are subject to damage, including metallization cracking, shifting, and delamination; and lifted bonds, respectively.

Furthermore, for nMOSFETs, increased degradation is found to occur during tensile stress conditions such that both the supply of electrons in the channel and the creation of hot carriers is enhanced [2].

Thermal Stress

Operational stresses (generated both during wafer fab processes and in applications usage) can result in device damage and failure when they relieve themselves. For example, due to the thermal expansion mismatch of VLSI and ULSI materials, in-use temperature cycling can generate failures (Fig. 14.14).

Thermally induced stresses, normally by thermal shock, are associated with large thermal gradients introduced by rapid changes in temperature. Due to applications conditions, materials having high temperature coefficients of expansion experience large localized mechanical stresses at sites of large thermal gradients. For example, brittle materials such as glass seals, glassivation, and semiconductor dice are subject to crack initiation and growth with thermal shock, whereas ductile materials such as pure aluminum and gold experience little degradation with thermal shock. Thermal gradients also result in large mechanical stresses across interfacessome interface factors embrittle the materials.

Figure 14.13
Maximum modeled shear stress at die corners.

Page 546

Figure 14.14
Thermal stresses generated by two materials with unmatched thermal expansion
coefficients.

Chemical Stress

Chemical stresses are normally generated in the presence of moisture and manifest themselves, typically, as corrosion failures. Moisture is probably the single most damaging environmental agent potentially affecting the lifetime of electronic circuits. Moisture is often trapped in circuit cavities, and within hermetically sealed IC packages; moisture can evolve from circuit materials such as polymers used for PCBs, die attachments, and plated surfaces; moisture is conducted through polymers used as seals or package materials; moisture is absorbed by all plastic packages; and moisture may induce crack growth in package materials. However, moisture by itself does no damage. Moisture in the presence of ionic contamination migrates to cracks and notches, causing rapid, local corrosion in some cases. This can also cause either environmental fatigue or stress corrosion cracking. As little as a few monomolecular layers of moisture combined with trace quantities of halogens or other ions degrade metal circuit members in time. Table 14.10 lists some of the chemically produced defects found in the IC manufacturing process.

The Arrhenius equation was developed to explain the rate of chemical reaction as a function of temperature. Arrhenius, a 19th century chemist, postulated that chemical reactions can be made to occur faster by increasing the temperature in which the reaction occurs. The Arrhenius equation is stated as:

Page 547

Table 14.10 Typical Chemical Defects Produced in Electronic Parts by Manufacturing Mistakes

Contaminated incoming materials

Residual processing chemicals

Chemical agents evolving from polymers (incompletely cured adhesives, package materials, etc.)

Solder fluxes

Impurities trapped at interfaces with metallization layers, wire bonds, etc.

Atmospheric impurities

Human-derived chemical agents (spittle, perspiration, cosmetics, etc.)

(1)

where

R₀ = constant

e = natural logarithm base 2.7182818

Ea = activation energy for the reaction (eV)

k = Boltzmann constant (8.625 × 10⁻⁵ eV/°K)

T = temperature (°K)

The equation can be diagrammed as shown in Fig. 14.15.

Dielectric Layers

Dielectrics like silicon dioxide and silicon nitride are used in a variety of areas in integrated circuit fabrication. Silicon dioxide films, for example, are used for

Figure 14.15
Diagram of Arrhenius equation.

Page 548

gate dielectics, for device isolation, as the capacitor material in DRAMs, for tunneling oxides in EPROMs, and for final passivation. Three areas where the manufacturing challenges appear to be greatest are gate oxide formation, intermetal dielectric (IMD) deposition, and DRAM capacitors.

Two of the foremost concerns that are driving the long-term trends in these areas are the material's dielectric constant and the temperature at which the oxide is deposited (or grown in the case of thermal oxides). In DRAM memory cells, for example, a high dielectric constant is desirable, since the higher the dielectric constant, the more charge one can store. Oxides, nitrides, and so-called oxynitrides are now used for these applications, but researchers have been working on materials with higher dielectric constants like tantalum oxide (Ta₂O₅) and barium strontium titanate (BST), and, for the more distant future, ferroelectrics.

In the case of intermetal dielectrics (IMDs), which insulate metal lines from each other, a low dielectric constant is desirable since it is part of the RC time constant that governs speed (frequency = 1/RC). For the same reason that low-resistance copper is being considered as a replacement for aluminum, lower dielectric constant materials like parylene or Teflon are being considered as the IMD material of choice.

Gate dielectrics are getting thinner as device dimensions shrink: now about 120 Å, gate thickness is expected to shrink to about 60 Å by 1999. The requirements of ultrathin dielectric films that are being used for gate, tunnel, and storage applications are high dielectric strength, low defect and interface state density, high breakdown fields, good radiation hardness, diffusion resistance, and minimum charge trapping.

The most prevalent method of forming the gate dielectric has been to grow a thermal oxide, in wet, dry, pure oxygen- and/or chlorine-containing ambients. In the quest for higher reliability, research has moved to sandwiches of oxides and nitrides like ONO (oxide/nitride/oxide) and more recently to oxynitrides (SiOxNy).

Work in oxynitrides first focused on growing the oxide in an ammonia (NH₃) ambient, but the excess hydrogen was found to create electron traps. Now, instead of ammonia, nitrous oxide (N₂O) is the nitrogen source of choice.

Fluorine also appears to be a beneficial addition to the gate dielectric, in that it enhances oxidation rate, relaxes the oxide stress, and suppresses the hot-electron-induced generation of interface traps. Research is underway to try to understand the effects of fluorine on dielectric breakdown strength, junction leakage currents, radiation hardness, and hot electron immunity. However, most of this research is still at the university level; integration issues have yet to be addressed.

Temperature is an important consideration, since it is almost always possible to form better quality materials at higher temperatures. Previously

Page 549

deposited silicides and metals, however, can only withstand temperatures of about 400°C. This means that thermally driven processes using hot-wall furnaces or rapid thermal processing systems are used to form gate oxides and DRAM capacitors (since metals or silicides have yet to be deposited at that point), while low-temperature plasma-enhanced chemical vapor deposition (PECVD) or spin-on glass (SOG) techniques are most often used for IMD applications.

The other thing to note is that silicon dioxide, the most commonly used dielectric, goes by many different names, depending on how it is deposited: thermal oxide, TEOS (tetraethoxysilane) oxide, BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), and SOG, for example, are all basically SiO₂give or take some boron and phosphorus.

In addition to dielectric constant and deposition temperature, important film properties typically include step coverage, gap-filling capabilities, density, stress, contamination, carbon/oxygen/hydrogen content, thickness uniformity, refractive index, and moisture resistance. Also of interest are process-related concerns such as deposition rate, which impacts throughput, and how well the material works with chemical or mechanical polishing.

Since the oxide layer is the heart of CMOS technology, its quality is extremely important to the proper functioning of circuits designed and fabricated using this technology. Typical oxide problems include shorts in the oxide, surface migration of ions, oxide breakdown, and cracking of glassivation or nitride layers. These problems occur in the following manner or sequence:

Cracking of glassivation or nitride layers occurs with differential thermal expansion.

Moisture accelerates crack propagation in glass by lowering surface and/or interfacial energies.

Moisture induces dissolution of phosphosilicate glass.

Phosphorus doping, which is used to provide mechanical stability of the glass passivation layer and reduce cracking, causes charge leakage from CMOS gates, and when in the presence of water makes phosphoric acid, which degrades metal members.

Metallization

The intricate conductor shapes required in ICs are accomplished through the use of a number of different industrial technologies. For example, ICs are typically produced by the growth of metallization layers from a vapor followed by appropriate etching processes. Bonds may be made using either tiny weldments or else small solder connections, cast in place.

Metallurgical microstructural features of the deposited metals, such as grain structures and lattice defects, have configurations and dimensions largely

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governed by the various material interface and preparation parameters. As for all metal members, the strength and other physical or chemical characteristics are essentially determined by these metallurgical details. The metalscopper, aluminum, gold, silver, and nickelemployed for electrical conductors have face-centered-cubic (FCC) crystal structures (see Table 14.3). The solder alloys are chosen because of their low melting temperatures. The pure FCC metals and the solders essentially have low yield stresses. Therefore, a pure FCC metal or a solder alloy might never be selected where structural strength is a primary requirement. One normally enhances the strength of metals in the bulk form by appropriate alloying, aging, and controlling grain structure. Comparable control of the metallurgical features must be accomplished in different ways in the thin conductors used in ICs. Also, at the dimensional scales relevant to ICs, metal atoms are quite mobile. This enhances various migration processes, metallurgical recrystallization, interatomic diffusion, and the activation of corrosion mechanisms.

These aspects become even more important for the manufacture of advanced ICs where the dimensions of the metal members are of the same order of, or are even smaller than, the sizes of the grain structures. Whereas normal bulk metals and alloys have properties largely governed by interactions associated with the large numbers of internal grain boundaries or features within the grains, the very fine metal members in an integrated circuit may have a large proportion of grains with boundaries either defined by or else strongly influenced by the dicontinuities at interfaces with substrate or coating materials.

Important parametric discontinuities occurring at the interfaces between different materials involved in IC construction include the following:

1. Elastic modulus

2. Lattice parameters

3. Crystal structures and orientation

4. Interfacial energies

5. Chemical characteristics

6. Diffusion parameters

7. Interface impurities

These interfacial factors are critical to establishing and maintaining, under operational stresses, the planar interconnection conductors of an IC. For example, simple calculations demonstrate that for a thin aluminum or gold conductor with dimensions approaching 1 mm, the surface energy contributions to mechanical strength are comparable to that of the normal lattice strengthening mechanisms. Dislocation dynamics are strongly influenced by the first three factors such that strong arguments can be presented to show that the mechanical integrity of an IC metallic interconnection is primarily provided by these interfacial strengthening factors, rather than the lattice dislocation-internal grain boundary interaction

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mechanics, which account for the strengths of similar materials having bulk dimensions. While factors (5) and (6) clearly are important to interfacial adhesion, each of the other factors also plays a role in the ability of a metal film to establish a sound interfacial bond with another layer. A lattice misfit at the coherent interface between two metals must be accommodated by the establishment of a network of misfit dislocations. The special configuration of this misfit dislocation network is determined by the existence of a suitable mechanism for the creation and glide of the misfit dislocations needed to establish the network. The spacing of the misfit dislocations is determined by the interfacial energy, the lattice parameters, and the elastic constants of the materials. An example of the strengthening effect of these interface factors is the oxide of aluminum, which provides a strong repulsive barrier for dislocations exiting at a surface.

Typical metallization problems/failure mechanisms include

Lifting due to poor adhesion

Cracks, voids

Thin regions, such as at oxide steps

Corrosion

Stress corrosion cracking

Interdiffusion (dissolution)

Hillock or whisker growth

Solid-state electromigration

Electrochemical migration

Large precipitates

Mechanical fatigue degradation

The dynamics of diffusion/interdiffusion/dissolution, electrochemical migration, and electromigration are briefly discussed.

Interdiffusion/Dissolution

Metals do not behave strictly as solids in the small features and configurations employed in ICs, due to the atomic mobility of the materials used. Diffusion processes are thus occurring continuously in the IC structure and are accelerated by temperature according to the Arrhenius expression, and by the presence of surfaces, grain boundaries, and lattice defects.

Diffusion proceeds according to Fick's first and second laws. Fick's first law is

(2)

where J is the atomic flux diffusing through unit area, D is the diffusivity, C is the atomic concentration, and x is the diffusion distance, so that dC/dx is the concentration gradient.

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Fick's second law is

(3)

Silicon and copper are added to aluminum metallization to prevent silicon substrate migration dissolution in the aluminum (silicon spikes) and the incidence of electromigration, respectively. As long as the silicon atoms are distributed uniformly (solid soluble), the silicon inhibits dislocation motion, thus strengthening the aluminum. Higher stress is required for them to move. In the copper-doped aluminum structure, angstrom-sized precipitates provide extraordinary strengthening. But when the precipitates grow and form particles, the strengthening feature is lost.

Both silicon and copper are not soluble (stable in solid solution) in aluminum at room temperature, only at elevated temperature, and tend to form precipitates. A precipitate is a concentration of a material or dopant at room temperature. Similar atoms (such as silicon) migrate toward each other, segregating the aluminum and silicon (pure silicon) in separate regions, or copper intermetallics and aluminum in separate regions. This leads to the eventual formation of an open circuit in the aluminum-silicon case. In the complex aluminum-copper intermetallics case, the combination of aluminum and copper intermetallics acts as a galvanic cell. This galvanic cell action in the presence of moisture causes corrosion, eventually leading to an open circuit, but the process is much more complex than in the silicon-aluminum case.

Electrochemical Migration

Electrochemical reactions proceed in the following manner:

(4)

Electrons are stripped from the elemental metal M; e⁻ is the electronic charge, and E is the standard oxidation potential of metal M. The metal M is the anode. It corrodes via the above equation.

The synergistic stresses found to activate electrochemical migration mechanisms, leading to an electrical short circuit, include a combination of

Potential differences

Moisture within the package

Suitable impurity atoms within the package (halogens and/or other chemical agents).

Time

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Electromigration

The phenomenon of electromigration in aluminum conductors is an increasing reliability problem as process resolution increases. Electromigration is the motion of atoms of aluminum along the conductor in the same direction as the electron flow.

Solid-state electromigration is a major wear-out mechanism in thin-film aluminum interconnections for advanced semiconductor devices. The microstructural features determining mechanical strengthening of thin-film metallization interconnections also are critically important factors for increasing wear-out life due to degradation mechanisms associated with electromigration. Metal atoms are effectively caused to migrate within metal conductors by the high current densities that occur in fine line interconnections. High current densities in thin-film metallization interconnections directly interact with dislocations to enhance mechanical deformation within individual grains. (Grain size is known to influence electromigration damage rates.) The magnitude of forces on individual dislocations is sufficient to produce dislocation motion and multiplication. This results in the mass transport of metal atoms very similar to the mechanisms that produce plastic deformation under mechanical stresses in metals.

Micromechanics experiments conducted using thin aluminum film and fine wire specimens demonstrated that plastic deformation was indeed induced by high-current-density pulses. Significant microstructural transformations were recorded as a result of the high current densities, illustrating both current-density-and thermal-energy-induced effects. Thus, the migration is a function of both the current density (Fig. 14.16) and the junction temperature (Fig. 14.17). The basic design guidelines are shown in Fig. 14.16. Assuming a typical metallization thickness of 10,000 Å and a design limit of 500,000 A/cm², the design limits are approximately 1 mA/mm of line width.

Figure 14.17 shows that temperature is also a critical factor. Electromigration typically has an activation energy in the range of 0.7 eV. Processing techniques such as glassivation and the addition of Cu to the metal can reduce the effects and allow an increase of current density by a factor of two.

Solid-state electromigration may be expressed mathematically as

(5)

where

j = atomic flux of metal

N = density of metal ions

eZ* = effective charge of ions

r = metal resistivity

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Figure 14.16
Metal migration design guideline (maximum allowed current
density).

Q = activation energy

T = temperature (K)

k = Boltzmann constant

D₀ = frequency factor

Some of the other factors besides current density and temperature that affect the rate of migration are

Grain size

Type of passivation

Substrate thermal conduction

Metal composition

Topology

Underlayer metal

Electromigration damage appears as the creation of voids within the metallization lines and as hillocks or whiskers growing out of the lines, leading to open circuits or interlayer short circuits. Void growth and void coalescence ultimately may reduce the effective area of a line such that the line cannot support the resulting increased current density. Burnout, i.e., an open circuit, results. Hillock and whisker growth may cause interlayer shorting. The whiskers grown during electromigration studies were shown to be single crystals of pure aluminum. This phenomenon is consistent with dislocation-based theoretical modeling of electromigration mechanisms taking place in thin-film metal structures.

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Figure 14.17
Metal migration mean time to failure.

The measures used to enhance durability to electromigration damage mechanisms correlate closely with those needed to enhance the mechanical strength of thin-film metal interconnections. Therefore, measures designed to improve electromigration damage resistance also serve to improve the mechanical durability of the precision IC composite structure.

Electromigration improvement is realized by doping the aluminum with copper or by employing certain interface structures such as die passivation (glass) and the use of multiple-layer structures. Pure copper is being investigated as an alternative to aluminum-based alloys [3].

Package and Interconnection Issues

The IC packages provide atmospheric and mechanical protection for the IC die, and a first-level interconnection externally between the IC and the next level of assembly, normally the PCB. As mentioned in Chapter 1, IC trends are significantly impacting package design:

Advanced IC designs are increasing the numbers of transistors and decreasing the real estate occupied by individual on-chip circuit features.

The thermal load is increasing with density increases. New package

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designs need to provide effective thermal conductivity using materials combinations that remain stable while operating at higher temperatures.

Increasing I/O pin counts, ranging from >300 to over 1000.

Large numbers of I/Os driving technology to much smaller lead dimensions (<4 mil) and the need to explore alternate package interconnection designs.

Smaller package leads introduce significant problems for mechanical protection, assembly and test alignment, and handling.

Material combination designs must minimize added inductance and stray capacitance.

Designers are attempting to find packaging materials that will provide long-term stability without the complexity, size, and expense of hermetic packaging.

Table 14. 11 lists some of the IC package issues from a materials perspective. Typical package-related defects are listed in Table 14.12.

Wire Bonding

Chip to package interconnections are accomplished by wire bonding or with tiny solder joints to chip carriers. The mechanisms employed to make IC weld joints result in highly altered microstructures in the metal pairs in the immediate

Table 14.11 Package Issues

Package size, number of I/Os

Feed-through insulator-conductor compatibility

Platings, coatings; stability

Seals: metallic, ceramic, polymer

Package-induced mechanical stresses

Die attachments

Thermal management

Internal interconnections:

wire bonds, TAB, thick films, flip chips, etc.

Microenvironment within package:

Chemical agents that support corrosion of either package or circuit materials

Hermeticity factors

Reaction thresholds for various material degradation mechanisms due to package microenvironment

Transport mechanisms

Moisture

Measurement technology for analysis of package microenvironment

Environmental-mechanical processes affected by package microenvironment

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Table 14.12 Package-Related Defects

Leakage at metallurgical seals due to surface contamination, incorrect welding or soldering parameters, grain boundary segregration at weld surfaces, etc.

Moisuture diffusion through polymers where employed as the seal or else as the package material

Loose conducting particles

Cracks in glass or other ceramic insulators

Incompletely cured polymers used for die attach adhesives

Improperly applied metallurgical die attachments

Moisture and other chemical agents outgassing from package polymers, metals

Trapped moisture and other gasses in package

Excessive thermal-mechanical mismatch in package materials

neighborhood of the bond. The resulting physical state of the deformed bonded metals and the geometrical aspects of the bond shape are critically significant to the performance and ultimate durability of the bond interconnection under operational and other stresses imposed on the circuit. Impurities, including surface oxides, hydroxides, etc., are trapped within the bond interface, and the deformation processes are such that bonded materials have residual mechanical stresses and surface asperities that promote the initiation of fatigue crack propagation.

Wire bonds are a critical manufacturing and quality issue, since they provide the means of electrical connection between the die bonding pads and the package leads (the external world). As was previously mentioned, wire bonds are typically established by one of the following methods:

Ultrasonic bonding

Thermocompression bonding

Thermosonic bonding

All of these methods involve the process of forming metallurgical (friction) bonds; the primary issues of these are addressed in Table 14.13.

The requirements for establishing a high-quality metallurgical bond are threefold:

1. The bond pair must be clean and in contact.

2. There must be significant mechanical deformation of the metal members.

3. Interatomic diffusion must occur between bond members.

Furthermore, elevated temperature decreases the yield stress for deformation during thermocompression bonding, and high ultrasonic energy density decreases yield stress for deformation during ultrasonic bonding.

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Table 14.13 Metallurgical Bonding (Friction) Factors

Wear processes occur between any two solid surfaces that are pressed together and displaced tangentially relative to one another.

Tangential, or frictional, forces result from the surface-surface interactions with relative motion.

The actual area of contact is normally much less than the apparent contacting area.

Surface variations cause the load to be carried by surface asperities (see Fig. 14.18).

Microscopic mechanical stresses at load-supporting asperities may be quite large.

Normal force introduces compressive stress; tangential displacement, microbonding, etc. introduces shear stress.

Complex microscopic stress distribution within surface regions of solids due to rubbing together.

Relative motion of solids produces friction and wear processes due to interaction of surface asperities. Small back-and-forth motions produce fretting wear.

Chemical agents at surfaces can have extraordinary effects on friction and wear. They can:

Serve as lubricants to reduce wear rate and/or friction, or

Be corrosive or stress-corrosive, acting to accelerate degradation.

Electrical currents or potentials between the contacting surfaces can have strong effects on wear rates and/or friction.

Unfortunately, actual wire bonds do not always exhibit these ideal characteristics. IC bonds, in general, tend to have a high density of defects, which serve as stress concentrators to initiate fatigue cracks; elevated temperatures accelerate degradation mechanisms associated with impurities trapped at bond interfaces; temperature cycling accelerates degradation from cracks, intermetallics, and stress concentrators, and produces wire fatigue due to the expansion and contracting force, as shown in Figs. 14.19 and 14.20; and the synergism of mechanical, electrical current, chemical and thermal stresses greatly enhances degradation.

Figure 14.18
Schematic showing surface asperities for two solids in contact.

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Figure 14.19
Bond wire.

Figure 14.20
Wire loop geometry and three possible resonant modes.

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Solder Interconnections

The IC package-PCB substrate must be viewed as a single electronic/materials system. As such, the solder interconnections are extremely important.

Solder interconnections have become a major limiting factor for the development of high-density electronic systems. Several of the technical problems with emerging soldering technologies are

Solder alloys are generally weak mechanically.

Solder alloys above recrystallization temperature at room temperature.

Small surface-mount technology (SMT) solder joints can be very complex metallurgical structures, involving dissolution of bonded metal surfaces, intermetallic compound growth, brittle interfaces, changing microstructures, and changing material properties.

SMT joints are difficult to inspect for faults.

Mechanical creep, fatigue.

Pick-and-place machines can damage parts.

Low-melting-point metal interconnection is needed in current electronic system technologies.

Printed wiring boards involving SMT are replacing boards having plated-through holes in order to reduce size, reduce cost, and increase speed.

SMT solder joints must provide: entire mechanical support for parts, entire electrical conductivity, and most of the thermal conductivity.

Several thousand SMT joints are formed simultaneously.

SMT joints are becoming very small, approaching 0.001 in., and less, in width.

The solder interconnections between the IC leads (pins) and the PCB traces are a source of many problems, including

Solderability

Voids and porosity at surfaces, internal to solder material, and at solder-pad and solder-lead interfaces

Intermetallic compound growth (Fig. 14.21)

Corrosion products or oxides

Residual flux and other process chemicals

Positioning

Cracks

Whisker, hillock, and dendrite growth

Alloy segregation

Surface roughness

Improper coverage: too much, too little (Fig. 14.22)

Poor adhesion

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Figure 14.21
Intermetallic compound growth at interfaces within solder joint. (A) Interface
as solder is initially flowed onto metal trace. (B) Intermetallic compound growth
at the solder-metal trace interface. (C) Growth of several intermetallic
compounds within solder joint.

Table 14.14 lists many of the manufacturing problems that can cause solder joint defects. The application environment, as mentioned previously, can cause thermal, mechanical, electrical and chemical stresses. Figure 14.23 shows solder joint flexure due to temperature changes. A detailed discussion of materials issues of solder joints and the inherent failure mechanisms can be found in Ref. 4.

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Figure 14.22
SMD joints with insufficient solder. A, IC package body; B, lead; C, bond pad;
D, solder; E, substrate; F, chip.

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Table 14.14 Manufacturing Problems that May Cause Solder Joint Defects

Contaminated PWB and SMD surfaces

Metal platings (gold) dissolved by solder

Improper solder alloy

Contaminated or aged solder or solder pastes

Improper choice of solder technique

Improper temperature-time settings for solder reflow

Improper choice of flux

Misalignment of solder paste screening pattern

Improper device placement on board surface

Improper selection of SMD lead material

Excessive oxidation of SMD lead material

Defects in conductor layers on PWB

Movement of device prior to solder solidification

Mechanical damage

Exposure to corrosive agents

Delamination of PWB

Figure 14.23
Gullwing solder lead flexure with thermal expansion due to temperature changes.

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References

1. R. W. Hertzberg, Deformation and Fracture Mechanics of Engineering Materials, Wiley, New York, 1989, p. 271.

2. R. Degraeve et al., Analysis of externally imposed mechanical stress effects on the hot carrier induced degradation of MOSFET's, Proceedings of the 1994 International Reliability Physics Symposium, San Jose, California, pp. 2933.

3. T. Ohmi and K. Tsubouchi, Advanced copper metallization technology for VLSI interconnects, Solid State Technol. April (1992).

4. B. L. Livesay, Micromechanics of advanced solder interconnection systems, Printed Circuit Assemblies, June and July (1989).

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PART IV
CAUSES (SOURCES) OF IC FAILURES

The field of reliability covers many aspects of the completed IC device, from chip surface charging to corrosion, electromigration, ESD, and handling. Tables IV.1 and IV.2 provide a listing of the design factors and Table IV.3 of the manufacturing process factors that affect reliability. Table IV.1 is global, whereas Table IV.2 is more detailed.

Much attention has been focused by IC suppliers on device quality (Does it work when the customer receives it?) but far less on the device reliability (How long will it work after it is plugged in?). The following chapters bridge the gap between IC quality and reliability. Featured are discussions on both wafer fabrication- and packaging/assembly-related failure mechanisms and their affects on IC reliability as relates to the physical implementation of the IC design. This section concludes with a discussion of activation energies of the various failure mechanisms. Part V continues this line of thought by addressing the effectiveness of various environmental, mechanical, and electrical screens in detecting these failure mechanisms.

As was discussed in Chapter 14, IC failures are a function of the circuit design techniques, the interfaces, and the materials and processes used in the

Page 566

Table IV.1 Examples of Design Factors that Can Cause Defects

Digitizing-schematic entry/layout errors
Data base errors

Accuracy and effectiveness of process and fault models
Data base errors

Stimulus errors
Data base errors

Logic design errors
Design errors

Circuit design errors
Design errors

Timing errors
Design errors

Package design errors (electrical signal fidelity/distortion, thermal issues, etc.)

Design errors

Test software (programming) errors
Design errors

construction of the devices and the handling to which they are subjected. An IC is a complex combination of many materialsmetals and their alloys, insulators, chemical compounds, ceramics, polymers, semiconductors, and composite structuresand its successful operation and also its failure depend on the interaction of these various materials and the interfaces between these materials. Interfaces bridge a number of material discontinuities:

Thermal expansion coefficients

Chemical characteristics

Elastic modulus

Crystallographic structures

Crystal lattice parameters

Diffusion rates

These interface factors are important for mechanical, chemical, structural, and electrical stability of circuit materials.

Integrated circuit quality is directly related to the robustness of the design and errors/defects/mistakes introduced during design, wafer fabrication, assembly, test, and all handling operations. As was depicted in Figs. I.1 and 2.24, this is a complex process and there are many places in the IC design and manufacturing (wafer fabrication and assembly) cycle where errors/defects can occur.

The IC defects can be broadly characterized as

Chip/die defects: hard failures, soft errors, and parametric shift

Assembly/package defects

Figures IV.1 and IV.2 expand these two broad categories and provide more details of die- and package-related failures, respectively. Figure IV.3 takes Fig. IV.2 to the next higher level of detail. Figure IV.3 is a fishbone diagram showing a map of the potential IC failures and the complex interrelationships of the many areas where failures/defects can occur. A listing of IC failure mechanisms as a function of manufacturing process steps is presented in Table IV.4, and Table IV.5 expands

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Table IV.2 Main Design Factors Affecting Reliability

Factors that affect reliability

Related factors

Failure mode

Pattern design

Transistor (bipolar)

Size and shape (collector, base, emitter), impurity atom concentration, diffusion depth

Characteristic failure

Transistor (MOS)

Size and shape (W/L), gate film thickness
Characteristic failure

Isolation

Width, diffusion depth, impurity atom concentration

Parasitic transistor, leak defects, breakdown voltage

Resistance (diffusion)

Size and shape, diffusion depth, impurity atom concentration

Insufficient characteristics, breakdown voltage, short

Resistance (polysilicon)

Size and shape, impurity atom concentration, film thickness

Characteristic failure, open

Internal wiring (aluminum)

Size and shape, film thickness
Electromigration, open, short

Internal wiring (polysilicon)

Size and shape, film thickness, impurity atom concentration

Characteristic failure, open

Internal wiring contact

Size and shape, contact combination (Al-silicon, Al-polysilicon, etc.)

Open, short

Bonding pad

Size and shape, wiring extracting form
Improper bonding, open

Bonding pad arrangement

Bonding pad distance, package, interrelation between bonding positions

Open and short of bonding wire, flow of bonding wire (resin mold)

I/O Protection circuit

Protection resistance, protection diode/transistor
Electrostatic discharge, surge damage

Manufacturing process design

Photolithography-etching process

Resist application

Film thickness, dust, foreign matter attachment, resist

Improper PEP shape (open, short, characteristic failure), pin hole

Mask matching

Accuracy of matching
Characteristic failure

Exposure

Time, intensity of illumination

Insufficient PEP shape (open, short, characteristic failure)

(table continued on next page)

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Table IV.2 (Continued)

Factors that affect reliability

Related factors

Failure mode

Development

Time, developing solution

Insufficient PEP shape (open, short, characteristic failure)

Etching

Time, temperature, etching solution

Insufficient PEP shape (open, short, characteristic failure)

Oxidized film formation (thermal oxidation film method)

Temperature, time, reaction gas, film thickness
Characteristic failure (Vth, hFE, etc.)

Oxidized film formation (CVD method)

Temperature, time, reaction gas, film thickness

Characteristic failure (Vth, hFE, leakage current, etc.)

Diffusion (thermal diffusion)

Temperature, time, impurity atom concentration, diffusion depth

Characteristic failure, breakdown voltage

Diffusion (ion implantation)

Acceleration voltage, dose amount, ion source, implantation depth

Characteristic failure

Electrode formation (aluminum)

Evaporation method, temperature, film thickness
Characteristic failure, open, short

Electrode formation (polysilicon)
Temperature, time, reaction gas, film thickness
Characteristic failure, open, short

Die separation
Dicing method, wafer thickness
Die crack, flaw, open, short

Die bonding

Die bonding method, temperature, die bonding material (Au-Si, epoxy, etc.)

Characteristic failure (unstable action)

Wire bonding

Wire bonding method (thermocompression bonding, etc.), wire material (Au, Al), wire diameter

Open, short

Sealing (hermetic sealing)
Sealing method (metal, glass, etc.), sealing width

Defective hermetic seal, large leakage current, corrosion breakage

Sealing (plastic sealing)

Molding method, temperature, time, material characteristics (thermal expansion factor, impurities)

Improper characteristics, die crack, open, short and corrosion breakage of wire

External lead molding
Lead molding method, size and shape

Broken package, lead shape, abnormality, broken lead

External lead surface treatment

Treating method (plating, dipping), protective material (gold, tin, solder, etc.)

Contact failure, soldering failure

(table continued on next page)

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(table continued from previous page)

Factors that affect reliability

Related factors

Failure mode

Package design (hermetic sealing)

Marking

Temperature, time, marking agent
Marking errosion

Sealing method

Glass, metal welding, metal melting, resin adhesion, sealing conditions

Defective hermetic seal, characteristic failure, increase of electric leakage, corrosion breakage

Sealing gas

Chemical reactivity, moisture content

Characteristic failure, increase of electric leakage, corrosion breakage

Package material

Glass, ceramics, metal, resin, thermal expansion, mechanical strength

Broken package, defective hermetic seal, characteristic failure, thermal runaway

Package shape and size

Correlation of die size, margin for sealed part size
Insufficient hermetic seal, characteristic failure

External lead material

Electrical conductivity, hardness, thermal expansion anticorrosiveness, mechanical strength

Contact failure, broken lead failure

External lead shape and size

Lead section form, tensile strength, bending strength
Broken or defective lead

Package design (plastic sealing)

Sealing method

Transfer mold, potting, etc.
Open, short (bonding wire)

Sealing resin material

Base resin, hardness, chemical resistance, impurities, thermal expansion, thermal conductivity

Characteristic failure, open, short (bonding wire), corrosion breakage

Package shape and size

Correlation of die size, size of sealed part, margin

Missing external lead, open, short, corrosion breakage

Molding conditions

Temperature, time, pressure
Open, short (bonding wire), bonding wire flow

External lead material

Electrical conductivity, hardness, thermal expansion, anticorrosiveness mechanical strength

Contact failure, broken lead failure

External lead shape and size

Lead section shape, tensile strength, bending strength

Broken lead failure

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Table IV.3 Manufacturing Process Factors Affecting Reliability

Manufacturing process affecting reliability

Related parts on element

Related factors

Failure mode

Wafer process

Wafer (silicon substrate)

Silicon bulk

Resistivity distribution, dispersion, defective crystal, surface dirt, abnormal crack, flaw, curvature, distortion

Characteristic failure, unstable action, short, open

Oxide film formation

Field oxide film, gate oxide film, interlayer insulated film, surface protective film

Pin hole, crack, uneven thickness, contamination, step coverage failure

Reversed surface, channel leakage, Vth (variation, worsened pressure resistance, hEF variation, noise, unstable action

Photolithography-etching process

Resist application

Transistor, diode, resistance, internal wiring, contact

Improper film thickness, uneveness, dirt, foreign matter attachment, residual resist

Improper characteristics, pinhole, increased leakage current

Mask matching

Same as above

Matching deviation, dirt, foreign matter attachment, flaw

Same as above

Exposing

Same as above
Insufficient exposure
Improper characteristics

Development

Same as above
Insufficient developing
Improper characteristics

Etching

Same as above

Insufficient etching (improper size), etching temperature, insufficient washing

Improper characteristics, characteristic variation

Diffusion (thermal diffusion)

Transistor, diode, diffusion resistance, isolation, contact

Abnormal diffusion (transverse, depth), impurity separation, improper crystal, improper impurity concentration

Improper characteristics, worsened pressure resistance, open, short, unstable action

(table continued on next page)

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(table continued from previous page)

Manufacturing process affecting reliability

Related parts on element

Related factors

Failure mode

Diffusion (ion implantation)

Transistor, diffusion resistance, contact

Oxide film, damaged bulk silicon, insufficient dose amount, insufficient implantation depth

Same as above

Electrode formation (aluminum)

Transistor electrode, internal wiring, contact, MOS gate electrode

Flaw, void, stepping, insufficient sealing, insufficient thickness, electromigration,

Open, short, increased wiring resistance, corrosion breakage

Electrode (polysilicon)

MOS gate electrode, resistance, internal wiring, contact

Flaw, stepping, improper sealing, insufficient thickness, fusion cut

Open, short, increased wiring resistance

Assembly process

Die separation

Die peripherals
Flaw, crack, contamination

Improper characteristics, increased leakage current, worsened pressure resistance, corrosion breakage

Die bonding

Die adherence

Insufficient die adhesion, overflowed adhesive agent, waste adhesive agent, gas generation (resin bonding agent)

Improper characteristics, unstable action, increased leakage current, short, intermittent failure

Wire bonding

Bonding wire connecting part

Improper bonding pressure, improper bonding part foundation, bonding group shape, wire flaw, contamination, excess wire attachment

Open, short (package, substrate), broken wire, peeled bonding

Sealing (hermetic sealing)

Package sealing part

Insufficient sealing, improper sealing gas (moisture, impurities), dirt on surface, mixture of foreign matters

Increased leakage current, corrosion breakage, short, intermittent failure

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Table IV.3 (Continued)

Manufacturing process affecting reliability

Related parts on element

Related factors

Failure mode

Sealing (plastic sealing)
Package

Defective molding (void, crack), bonding wire flaw, insufficient lead-frame sealing, molding shrinkage distortion, moisture absorption

Bonding wire open and short, corrosion breakage (die ± metal wiring), die crack, improper characteristics

External lead formation
Lead terminal

Improper shape, damage, insufficient terminal strength

Open, improper contact

External lead surface treatment
Lead terminal

Oxidation, residual surface treatment solution (insufficient washing)

Open, improper contact, interterminal leakage

Marking
Product display

Erroneous display, improper display

Destruction due to improper operation

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Figure IV.1
Map of die-related defects.

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Figure IV.2
Map of package (assembly)-related defects.

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Figure IV.3
Fishbone (Ishikawa) diagram of typical integrated circuit failures.

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this listing still further. Then too, from a die perspective, there is a major difference in the type of predominant failure observed by technology:

Bipolar ICs: dominated by sodium contamination (originally), buried layer shift (due to preferential epitaxy growth in <111>), junction spiking (due to use of pure Al) and ESD (no input protection networks)

CMOS ICs: dominated by oxide defects, especially charge retention in the gate oxide, and hot electron effects

Today (1994), the major causes of IC failure are attributed to

Foreign particle contamination weakens dielectrics and reduces conductive capacity.

Stressed materials lead to stress voiding, electromigration, burnout at thinned areas, oxide wear-out, and degradation of IC structures due to high-energy electrons (hot carriers).

Chemical contamination results in parameter drift, corrosion, and breakdown.

Process errors lead to poor oxide step coverage, misalignment at photolithographic steps, overetching, and latch-up.

Customer use can result in ESD and handling damage such as bent leads.

Radiation effects.

Figure IV.4 is a Pareto diagram of CMOS wafer fabrication defects.

Figure IV.4
Types of defects found as a percentage of all defects.

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Table IV.6 Common CMOS IC Failure Mechanisms

IC failure mechanisms

Primary electrical effect

Time-dependent dielectric breakdown
Gate oxide shorts

AlSi creep
Metallization opens

Negative charge instability
Lowered p-channel field transistor Vth

AlSi plasma etch residue
Interconductor shorts

Ionic contamination
Gate and field oxide Vth shifts

Silicon surface defects
Soft p-n junction

Lastly, Table IV.6 lists the six most common CMOS failure mechanisms and their respective failure modes encountered at Sandia Laboratories during the 1980s. The predominant IC failure mechanisms listed in Tables IV.4 and IV.5 will be discussed in greater depth in the next several chapters (15, 16, and 17).

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15
Fabrication-Related Causes of IC Defects*

Bulk and Surface Failures

Failures that arise from defects or impurities within the silicon or oxide layers manifest as an out-of-specification parametric drift condition in which the device is operable but not to its intended limits, or as a catastrophic breakdown.

Bulk Defects

Bulk or gross defects such as cracks or pits in the chip or passivation cause degradation failures in the silicon or gallium arsenide crystal structure. They are in general caused by mishandling of the chip, especially in the dicing and packaging processes. Three methods are used to dice wafers into individual dice: scribe and break, laser dicing, and diamond sawing. Each of these methods can induce defects in each die during the dicing process.

The older scribe and break technique does not provide an exact square edge, leading to handling difficulties on high-speed die attach machines, and the

*Portions of this chapter used with permission from Ref. 1.

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chips resulting from this operation frequently have crack propagation problems. Laser die separation is fast, but the capital equipment is typically very costly, and maintenance is high. Also, peripheral heat and spatter from melted silicon can significantly reduce yield, and laser cutting also requires a secondary breaking operation. Diamond dicing provides clean cut straight streets in one operation, thereby increasing yields in packaging. Chipping is the greatest problem with diamond sawing. Critical parameters for chipping are feed rate, grit size, cut depth, and blade sharpness (dull blades create extra pressure, causing excessive chipping). Figure 15.1 shows a diamond saw dicing a 6-in. wafer containing VLSI circuits.

Mismatch between the thermal expansion coefficients of silicon and the glass passivation introduces stress and strain during subsequent thermal processing, which may result in cracks or breaks. Defects of this kind tend to be yield

Figure 15.1
Die separation (dicing) using diamond saw cutting technique. (Photograph courtesy of
Kulicke and Soffa.)

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rather than reliability problems, as they are easily spotted during visual inspection of the chips.

Crystalline defects in the silicon tend to affect devices that operate in the avalanche mode by acting as generation-recombination centers, which enhance the diffusion of impurities. The defects may arise as a result of incomplete annealing of the damage caused by ion implantation. High-temperature processes subsequent to the emitter diffusion or implantation, or operation at elevated temperatures, may cause the dopants to diffuse, giving junction curvature and nonuniform current densities. These phenomena may result in degradation of the device and eventual failure. The processes of dopant implantation and diffusion into silicon are well characterized and have not caused major reliability problems through LSI integration levels. However, with the small-geometry VLSI devices, a reliability problem may exist.

Processing Faults

The complexity of the IC fabrication process requires the use of many photolithographic and etching operations. Flaws in the devices may arise due to misalignment of the photomasks, or under- or overetching. These faults can, in some cases, pass the screening and burn-in procedures and only come to light as time-dependent failures in service. (Table 15.1 provides a listing of some examples of process-induced defects. Figures 15.2 and 15.3 show several photomask faults that resulted in device failure.

Table 15.1 Examples of Processing-Induced Faults

Fault category

Resultant effect

Lithographic/mask defects

Polynicks or gate misalignment causing changing in channel length, punchthrough or weakly turned on device

Missing contact results in open circuit

Metal shorts (to Vcc), notches or opens (resulting in floating lines); due to surface topology and high reflectivity, it is hard to pattern metal

Automated techniques for inspection requires several translations of the databaseintroducing errors such as shifted or missing patterns

Contamination

Junction defects (in depletion region), which cause increased leakage current (device becomes resistive) and ultimate junction failure

Nonplanar oxide surface with high aspect ratio

Poor metal step coverage
Contact misalignment
Metal notching

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Figure 15.2
SEM photo of photomask flaw induced metal
defect. Part worked until electromigration reduced
thin conductive bridge to the point where it blew
open. (Photo courtesy of Hi-Rel Labs, Inc.)

Examples of failures due to processing errors include improperly formed contacts (Fig. 15.4), missing contact windows, silicon growth in contact windows (Fig. 15.5) resulting in high resistance or an open circuit, overetched contacts causing pitting (Fig. 15.6) resulting in either high leakage current or junction spikes, and the creation of parasitic transistors. Missing metal-to-polysilicon windows in the nitride layer allow the transistor gates to float (see Fig. 15.7).

Figure 15.3
Photomask flaw that produced an oxide and
diffusion flaw beneath a metal run.
Electromigration caused eventual opening of the
metal over the step. (Photo courtesy of Hi-Rel
Labs, Inc.)

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Figure 15.4
Improperly formed contacts.

The nitride capacitance to the floating gate is often sufficient to permit normal device operation until hot electron injection through the thin gate oxide charges the floating gate to some critical offset potential, whereupon device failure is evident.

Parasitic transistor action can occur between adjacent devices, due to overetched or misaligned contact windows (see Fig. 15.8). Failure occurs when a charge built up on the thinned dielectric, in the field region between adjacent diffusions, is sufficient to invert the underlying silicon and create a conducting channel. The rate at which the charge builds up depends upon the local electric fields, and is thus likely to be dependent upon stored information.

Latch-up is a primary failure mode of CMOS ICS. Latch-up is triggered by excessive charge being injected into the IC, which alters the conduction state of the parasitic SCR that is formed during IC manufacturing. Normally in the off state, parasitic SCRs don't interfere with device operation. If a parasitic SCR is triggered into conduction, a low-impedance path is developed between Vcc and ground, which can result in high power supply current. The amount of charge needed to latch up an IC is a function of IC design and processing. Thus, the

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Figure 15.5
Silicon growth in contact window.

amount of charge needed to latch up an IC may significantly differ from the amount of charge needed to latch up a similar IC from a different supplier.

Latch-up is triggered by voltages appearing on a pin that exceed the manufacturer's recommended operating limits. This includes

Power supply overvoltage

Noise spikes on input or output pins

Rate at which power supply voltage is supplied

Improper sequencing of power supplies

A CMOS IC will remain latched up until either the power supply voltage is removed or the device self-destructs.

For VLSI circuits, oxide breakdown in multilevel polysilicon structures is a problem. This is because the etch rates of the deposited oxide and polysilicon layers are different (using the usual etchants), resulting in gate oxide undercutting of the polysilicon layer(s) and subsequent thinning of the oxide between the polysilicon and the substrate or adjacent polysilicon layers. The thinning can reduce the oxide to less than half its nominal thickness, with the corresponding reduction in breakdown voltage.

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Figure 15.6
Overetched contacts resulting in pitting.

Gate oxide undercut can also lead to trapped voids in the regrown oxide, again reducing the breakdown voltage. It has been found that a mixture of CrO₃ in aqueous HF will etch the polysilicon at the same rate as the oxide, and thus no undercutting will occur even with overetching; consequently no thinning of the local oxide will be observed.

Dielectric Breakdown

In typical CMOS technologies under standard operating voltages (i.e., low electric fields), most dielectric failures are related to defects in the various layers. These defects are caused by contaminants and process-induced damage, for example.

Contaminants are introduced during the cleaning steps of the gate oxidation process. Gate smoothness is improved by controlling the amount of ammonium hydroxide (a potential contaminant) used during the first stage of cleaning. The manner in which the cleaning chemicals react with silicon/silicon dioxide, as well as differences in where the chemicals were produced, determines the amount of contaminants present.

Integrated circuit manufacturing steps such as plasma processes used during

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Figure 15.7
Missing contact window in the silicon nitride layer [1].

photoresist etch can damage thin oxide layers by causing DC current flow. CMOS gate oxide degradation has been attributed to electrical charging during plasma processing. In a plasma ambient, charge is collected on metal or polysilicon electrodes, called antennas (Fig 15.9). The charge is collected through the conductor surfaces, which are not covered by photoresist during plasma processing. The resultant current flow causes current-induced stress and can lead to charge trapping in the oxide and trap generation at the SiO₂-Si interface. Although a forming gas anneal can passivate many of the traps generated during

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Figure 15.8
Misaligned contact window resulting in parasitic MOS
transistor action [1].

plasma etching, latent damage remains, and subsequent electrical stressing causes roughly half of the passivated traps to be reactivated. Interestingly, these very phenomena may be used to measure the oxide-charging current. Interface trap density (Nit) and oxide-charging current can be determined from capacitance-voltage and MOSFET characteristics such as the subthreshold swing, threshold voltage (Vth), or mobility. Since plasma-induced damage may cause further IC yield loss by enhancing the oxide's vulnerability to hot-carrier-induced degradation and time-dependent dielectric breakdown (TDDB), the issue of plasma-induced degradation is a critical one for VLSI processing. Oxide (dielectric) defect-related failures typically occur early in product life and give rise to a declining failure rate. The other type of dielectric failure mechanism is wearout and typically occurs only when the operating field approaches the breakdown strength of the dielectric. Wearout is characterized by an increasing failure rate.

In both cases, the failure mechanisms for silicon dioxide are thought to be

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Figure 15.9
During aluminum plasma etching the resultant charge flux (arrows) from the
plasma causes charges to be collected by A1 antenna, giving rise to electrical
stress in the underlying oxide.

due to charge buildup near the silicon-silicon dioxide interface, enhancing the injection of charge carriers into the oxide. The charge buildup increases the electric field at the interface, and since current is exponentially dependent upon the electric field (Fowler-Nordheim tunneling), a small buildup of charge dramatically increases the current flow. As the current increases, localized joule heating can vaporize the silicon dioxide and silicon, causing a short between the substrate and gate electrode in gate oxides or polysilicon and metal in interlayer dielectrics.

Silicon dioxide, the primary dielectric used in IC wafer fabrication processes, can be characterized using a variety of techniques, including measuring the breakdown electric field distribution, charge to breakdown, and time to breakdown under constant electric field stressing. The first two tests can be rapidly executed at the wafer level, allowing them to be used as in-process monitors. The latter is very time-consuming but allows easier derating to actual device operating characteristics.

A typical oxide breakdown distribution provided by Intel is shown in Fig. 15.10. There is an intrinsic population centered around 10 MV/cm that is brought on through Fowler-Nordheim tunneling through defect-free oxide. A second distribution is sometimes found in the 02 MV/cm range and is typically screened out at wafer sort (probe); it shows up as a yield failure.

Statistically monitoring die fallout for oxide failures is an effective methodology for identifying any major oxide excursion due to processing. The third distribution noted in Fig. 15.10 is that which lies between the 2 MV/cm

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Figure 15.10
Oxide breakdown distribution. (Reprinted by permission of Intel
Corporation, copyright Intel Corp. 1991.)

level and the intrinsic distribution at 10 MV/cm. These are often referred to as latent defects.

An IC transistor with an oxide defect behaves as a weakly turned-on device. Integrated circuits with oxide defects exhibit increased leakage current (which can be detected by IDDQ measurements), decreased logic (threshold) voltage levels, and slower switching speeds (propagation delays), but functional performance (even with a gate-oxide short) is generally not affected. Dielectric breakdown of the gate oxide is and has been the dominant failure mechanism for CMOS ICs.

Although electrical prescreens, using high temperatures and accelerating electric fields, are still used to reduce the level of latent defects, more emphasis is focused on reducing process-induced defects. This is especially important as oxides become thinner, to prevent stressing the oxide into the wearout region. The effect of increasing electric field is shown in Fig. 15.11. Higher electric fields result in much shorter failure time, allowing IC manufacturers to optimally screen out all devices with oxides defective enough to fail during the part's life.

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Figure 15.11
Time-dependent oxide breakdown. Field-accelerated wearout in 100-Å oxides,
T = 150°C. (Reprinted by permission of Intel Corporation, copyright Intel
Corp., 1991.)

Time-Dependent Dielectric Breakdown

Structural nonuniformities in the gate oxide or in the silicon substrate beneath the gate oxide can occur during the fabrication process. Metal ions, particulates, and crystalline defects reduce the dielectric strength of the gate oxide. The silicon surface defects responsible for gate oxide breakdown are typically oxidation-induced stacking faults. In addition, oxide impurities such as sodium are known to reduce dielectric strength. Figure 15.12 illustrates the time-dependent process that can occur when an electric field is applied to a defective gate oxide.

Defects such as in Fig. 15.12a alter Si crystal or SiO₂ geometry such that an abnormally high local electric field is present when a voltage is applied to the transistor gate as in Fig. 15.12b. This higher electric field causes tunneling of electrons into the gate oxide and a subsequent acceleration of charge through the gate oxide. If sufficient acceleration distance exists, then these electrons

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Figure 15.12
Time-dependent shorting process. Conversion of a gate oxide defect to a gate oxide
short. (a) Cross section of a MOSFET having a physical defect at the gate oxide to
p-well interface; (b) application of a high electric field to the gate oxide structure from
a gate bias voltage; (c) conversion of the gate oxide defect to a gate oxide short.

exchange energy with SiO₂ molecules and create hole-electron pairs. Free electrons are rapidly swept from the dielectric, but the relatively immobile holes remain in the thin oxide. Hole buildup in the gate oxide increases the local electric field in the defect region and enhances further tunneling and hole trapping. This time-dependent buildup of local gate oxide electric field leads eventually to a rupture, as in Fig. 15.12c. The time required for rupture to occur depends upon defect geometry, the duration of applied gate voltage, gate oxide thickness, and the magnitude of voltage and temperature applied to the transistor.

Gate Oxide Breakdown

Some failures are attributable to electrical shorts through the thermal oxide between the metallization and the silicon. Such shorts may occur during operation within rated conditions, or as a result of electrical overstress (EOS) or electrostatic discharge (ESD) events. Those occurring within rated conditions are caused by localized defects such as pinholes or thin spots in the oxide, which may arise during processing. The problem is greater with CMOS devices since they have a thinner oxide layer than linear or TTL devices: the gate oxide thickness in CMOS devices may be only several hundred angstroms or less. The presence of defects or impurities or a local region of thin oxide will result in a lower dielectric strength and lower breakdown voltage. Electrical screening is performed at voltages higher than rated value to eliminate those devices that have regions of oxide of only marginal quality.

Because CMOS devices have very high input impedance and thin gate oxides, they are especially susceptible to static electricity effects and voltage

Page 600

transients, which can exceed the maximum rated voltage and cause breakdown of the oxide. Electrostatic discharge and electrical overstress into product input, output, and power supply leads are the leading causes of device failure in the user's manufacturing process. EOS and ESD damage affects device functionality and parametric performance to varying degrees.

Integrated circuits have a discrete ESD threshold value that must be reached before the physical damage is sufficient to affect the functional performance. The failure threshold is determined by the minimum voltage at which electrical failure occurs. Damage sustained below the threshold of failure may affect the subsequent ESD susceptibility of the IC and cause a deterioration of critical electrical parameters. From experience, damage will normally occur at lower thresholds on inputs than outputs.

Catastrophic damage can prevent functional operation. This level of damage is easily detectable by in-process testing. Lesser damage may produce slightly degraded product functionality or may even cause no measurable decrease in device functionality. Typical examples of degraded device performance include increased IDDQ currents, increased input leakage currents, or increased timing delays. EOS and ESD damage may cause latent defects resulting in failure after the devices are fully tested and shipped to the customer.

Data interpretation depends upon many aspects of a particular analysis. For example, EOS and ESD mechanisms may cause gate oxide damage with electrical symptoms that resemble typical process related defects. The failure analyst must use good judgment to investigate and disposition the failures appropriately.

EOS damage typically produces melted bond wires or melted interconnect metallization due to excessive current supplied by test equipment, power supply transients, or power supply voltages applied to the wrong pin. The symptoms of EOS can occur from excessive current during device latch-up or snapback. The current magnitudes associated with EOS are typically large enough to create visible damage to the devices. This is not commonly noted for ESD failures because ESD usually involves higher voltages with lower currents. EOS can occur during device testing or burn-in conditioning. Knowledge of device test history is crucial to determine the source and nature of the failure.

ESD events involve high voltages up to 35 kV, but with much lower current values than those of typical EOS events. ESD damage is often high-resistance shorts of thin oxides. ESD voltages vary greatly, thus creating variable degrees of damage to device circuitry. In almost all situations ESD does not damage bond wires or cause large-area visible damage. Typically, delayering must be performed in order to visibly locate the defect. The location of the actual defect(s) within the device is a key factor in interpreting the cause of oxide defects relative to ESD or process related defects. Again, knowledge of the device test history is crucial in proper failure disposition for most cases. ESD damage is caused by charging of personnel, work area material, and equipment.

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Results of failure analysis over a 6-year period for 23 IC designs from a high-reliability CMOS fabrication facility indicate that over 25% of the failures were induced after wafer fabrication and were not caused by processing defects [2]. The two major causes of these failures were electrical overstress (EOS) and electrostatic discharge (ESD) damage.

Of 1921 reject ICs submitted to failure analysis, 314 (16.4%) of the devices rejected by the electrical test process were found to be good devices; 1,193 devices failed due to process related defects. The predominant causes for these device failures were (1) gate oxide defects, (2) random metal and polysilicon opens/shorts, and (3) mobile ionic contamination. These failures comprise 74.3% of the true failures. The remaining 414 devices or 25.8% of the rejected product was damaged by the cumulative effects of EOS and ESD, all of which were avoidable. It was found that this damage was due to either operator errors or test equipment failures. Of the 414 devices, 200 failed for ESD reasons and the balance (214) for EOS. Failure analysis of the ESD failures showed two categories of failure: design-sensitive causes and poor IC handling practices (a broad category), the most common causes of which were a design compromise in the input protection circuitry, a lack of ESD training, ineffective ESD-protected work areas and equipment, and failure to follow ESD procedures.

EOS failures were separated into two distinct categories. The first category includes all failures induced by personnel. These failures include devices damaged due to operator error, such as not following procedures, and by engineering support errors, such as poorly designed test fixtures or test instructions. The second category includes all failures that were not induced by personnel. These failures are primarily caused by test equipment, such as equipment malfunctions, and by worn test fixtures. Figure 15.13 shows the occurrences of EOS due to these mechanisms, relative to the total population of induced failures.

Figure 15.13
Root causes attributable to EOS relative
to total failures. E, test equipment failure;
OE, operator error; F, worn test fixtures;
ED, poorly designed test fixtures or test
instructions.

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Digital ICs, typically pushing the state-of-the-art feature sizes, historically have used input protection circuits to limit ESD events. Linear (analog) ICs, being larger geometry devices, have not used input protection devices but now are considering their use. The purpose of the protection circuit is to clamp the gate-to-substrate potential at a safe maximum value under conditions of voltage overstress applied with either fast or slow rise time, and absorb large pulse energies. It must not affect the normal operation of the device or introduce any significant propagation delay into the circuit. Its design and fabrication must be compatible with the on-chip technology. Some typical gate protection circuits are shown in Fig. 15.14. These may include reverse-biased p-n junctions with controlled breakdown characteristics. The breakdown must be sharp, so avalanche diodes are used. However, the breakdown voltage of avalanche devices is apt to walk out under high-voltage operation, leaving the gate unprotected. Other circuits include diodes and distributed (implanted) resistors, and transistor

Figure 15.14
Gate protection networks.

Page 603

switches. These devices are so designed that the maximum acceptable voltage corresponds to the punchthrough voltage. Any overstress switches the device on causing it to conduct and absorb power thus protecting the gate. Low-doped devices are used so that the stored charge is low for rapid switching operation. The ICs containing input protection networks usually experience damage within this network after exposure to an EOS or ESD event. Damage will normally occur in the input polysilicon resistor if this exists. If no polysilicon resistor exists, junction damage will normally occur at the first contact window or diffusion connected to the input.

Ionic Contamination

Sodium, potassium, chlorine, bromine, and fluorine are elements that are present in virtually all materials, chemicals, and handling situations encountered during the manufacturing process. The positive sodium ion was quickly recognized by the IC manufacturing industry as a major potential problem affecting yields and reliability, especially due to its mobility in silicon dioxide. Extensive wafer cleaning procedures have been employed to reduce sodium concentrations built in during wafer fabrication.

However, the basic contamination threat occurs primarily after wafer fabrication, during handling and assembly. Sodium causes junction leakage, which results in parametric instabilities in linear ICs.

Ionic contaminants (especially chlorine), contained in many chemicals used in the assembly process (such as bromine mold release agents), and/or sulfur contamination can enter the package along the epoxy/lead-frame interface, migrate along the gold bond wires, and reach the bond pads. The reaction of chlorides with aluminum under high temperature, humidity, and bias conditions results in massive corrosion and dissolution of the exposed bond pads. Aluminum chloride (AlCl₃) forms at extremely low chlorine concentrations, and the amount of AlCl₃ formed is limited only by the availability of Cl₂. The action of chloride ions is to break down or prevent the formation of passivity on metal surfaces. Breakdown of passivity by chloride ions occurs locally on sites possibly favored by small variations in the surface film structure, leading to pitting corrosion.

Another contaminant is fluorine, which can be embedded in the aluminum metallization through improper plasma processing during chip manufacture. Fluorine, although to a lesser extent, is also known to cause corrosion by breaking down passivation or by preventing passivation formation on aluminum surfaces. Analysis has shown that the presence of fluorinein the form of a polymer (CHFCH₂), a carbonaceous residue C₄F, or a complex salt K₃AlF₆causes corrosion on the surface of aluminum bond pads.

Aluminum is sometimes alloyed with small amounts of copper to prevent electromigration. However, this can cause highly localized pitting in the presence

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of moisture. Also, traces of copper ions make efficient cathodes and increase the possibility of corrosion.

Surface Instability

Many device failures can be attributed in some way to the instability of the potential at the silicon-silicon oxide surface: the surface potential. It is the surface potential that determines whether or not a conducting channel exists. Consequently, any drift or variation in this potential will tend to degrade the performance of the device. The problems associated with surface instability are more severe in CMOS devices than in bipolar, since they have a lower doped substrate and a thinner oxide layer, and are thus more easily influenced by variations in the potential and stored charge.

The surface potential influences the gate threshold voltage, the carrier generation-recombination rate, and the depletion width of p-n structures. The changes in these parameters result in degradation of the DC gain and junction breakdown voltage, increased leakage currents, source-drain punchthrough, and changes in the gate threshold voltage and transconductance due to channel inversion. Lateral cooperative effects between adjacent emitters leading to parasitic transistor action may also occur.

The surface potential is modified by the migration of mobile ions in the oxide or on its surface, under the influence of electrical bias. The mobile ions may activate traps within the oxide or at the oxide-silicon interface, and polarize dipole charges in the oxide. The most common impurity is sodium ions, which can arise from etching and washing, or as a result of resistance-heating deposition of the aluminum metallization. The sodium ions have a high mobility in silicon dioxide at elevated temperatures, and drift under the influence of an electrical field. Their mobility is enhanced by crystal defects and damage.

In cases where the device failure is not catastrophic, functional operation may be recovered by thermal annealing of the defects, dispersing the sodium ions. However, high-temperature processing of completed devices may introduce other defects such as alloying of the metallization and oxide, or mechanical strain, which will then reduce the device lifetime. Thermal annealing of the ionic defects is thought to be the reason for the apparent recovery of failed devices undergoing life-testing, which are allowed to cool without bias.

The use of P₂O₅ or phosphosilicate glass (PSG) as a passivation layer over the thermal oxide is often used to getter the sodium ions; they are then fixed and unable to migrate through the oxide. However, PSG increases SiO₂ etch rate. Generally speaking, bipolar devices are much less susceptible than MOS to ion migration effects due to the growth of PSG layers during the vapor-phase emitter diffusion process, which is performed in an oxidizing atmosphere. These areas then serve to getter the sodium impurities. Failures resulting from ion migration effects may still occur even in passivated devices due to photolithographic or

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etching errors, which give rise to misaligned or thin PSG layers and consequent incomplete gettering of the sodium ions. Another source of failure occurs whenever moisture penetrates cracks and other defects in the PSG layer, causing catastrophic device failure due to corrosion of the metallization. The availability of equipment for depositing low-temperature plasma-enhanced nitride (PEN), which not only is a more effective sodium barrier than PSG but also can be deposited in compression on the chip surface, results in a layer of greater physical integrity.

Some suppliers have extended this to the use of a dual-layer passivation technique in which an oxide underlays the plasma-enhanced nitride layer. This results in a reduction, virtually to zero, of cracks and defects, thereby increasing resistance to sodium and corrosion.

The use of electron-beam evaporation of aluminum may be preferred to resistance heating, which can give surface contamination. However, the electron beam causes soft x-ray emission, which introduces damage in the oxide layer in the form of traps and defects. CMOS devices are particularly prone to damage due to ionizing radiation.

Surface Ion Migration

Normal MOSFET operation illustrating both the depletion and inversion regions is shown in Fig. 15.15.

Ignoring the source and drain, the threshold voltage of a MOSFET can be defined as the gate voltage required to induce an inversion layer of charge in the silicon channel below the gate and the gate dielectric. It is called an inversion layer because the charges (free carriers) are of the opposite type to the channel (substrate) doping type. The inversion layer is created by the very rapid process of minority carrier generation occurring in the depletion region. The depletion region is that area of the channel that experiences a loss of majority (doping-type) carriers whenever the gate is charged with carriers of the same type as the substrate. In simple terms, like charges are repelling each other.

There are several physical mechanisms that influence MOSFET stability; all involve the redistribution of the electric field in the gate dielectric. The migration of ions along the surface of the oxide can have an enormous effect upon the electrical properties of the underlying oxide-silicon interface, in all types of silicon planar devices. The effects are greater in thin oxide devices. In general, therefore, current generation (1994) high-performance CMOS and bipolar devices tend to suffer more from surface ion problems than previous generations. The existence of fast states at the silicon surface promotes the existence of conducting channels, either by inversion of the surface layer or by trap-assisted conduction. The effect is most prominent at diffused p-n junctions, where the channel increases the leakage current and reduces the breakdown voltage, thereby degrading the diode performance.

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Figure 15.15
MOSFET depletion and inversion regions.

The MOSFET is made unstable by alteration of the electric field across the gate dielectric. If a charge (an ion or a carrier) is introduced into the region between the gate electrode and the channel, the relative repulsion of channel carriers is affected. If the charge is the same type as those in the gate, the repulsion is increased. If it is opposite, the repulsion is decreased. As a result, the threshold voltage of an ideal MOSFET is decreased or increased (shifted), respectively. For example, when a positively charged sodium ion is introduced into the gate dielectric (Fig. 15.16) of an ideal n-channel MOSFET, the threshold voltage is decreased to a lower value. Figure 15.17 shows the effect of mobile ion contamination.

The issue of mobile positive charges (mainly sodium) is one of the most prevalent problems associated with bipolar (and CMOS) linear ICs. With these devices, the fringing field associated with the bias across a p⁺/n⁻ junction (as high as 4060 V for bipolar linear devices) will accumulate positive sodium ions on the negative side of the surface depletion region. A sufficiently high charge will invert the underlying p⁺ surface, creating a peripheral distortion of the subsurface depletion region as shown. Within this distorted region there now

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Figure 15.16
Depletion and inversion regions with positively charged sodium ions in the gate dielectric.

exists an n⁺⁺/p⁺ junction, which exhibits a low (12 V) breakdown voltage and a saturation current characteristic as shown in Fig. 15.18. The onset of the phenomenon is voltage, temperature, and time dependent.

Localized defects in the oxide film may be activated by surface ion migration, resulting in catastrophic breakdown of the device. The sodium ions will migrate toward the metallization in the vicinity of reverse-biased p-n junctions and hence the depletion region will tend to widen at the surface under these unmetallized areas. Any defects in this incremental area will be activated leading to excessive leakage and breakdown of the junction (Fig. 15.19).

Surface ions can also contribute to surface leakage currents by creating a conductive path between adjacent metal lines. This may take the form of an electrolytic process involving the corrosion of the metallization, which will result in the formation of voids in the metal, and hence device failure. Implanted thin-film resistors are susceptible to corrosion due to surface ion migration effects.

The mobility of the ions is dependent upon the cleanliness of the surface

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Figure 15.17
Effect of mobile ion contamination. (Reprinted by permission of Intel Corporation,
copyright Intel Corp., 1991.)

of the oxide. Laser-scribed chips often exhibit a large amount of surface debris and have been shown to suffer from degradation induced by surface ion effects. A passivation layer of aluminum oxide or silicon nitride may be employed as a barrier to avoid contamination of the completed device. However, MNOS transistors can have unstable threshold voltages due to charge storage and

Figure 15.18
Sodium causes junction leakage [3].

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Figure 15.19
Schematic of increasing depletion width, resulting in
failure when it comes into contact with a local defect [1].

transport in the two dielectrics, unless the conductivity of the nitride is kept low by carefully controlled fabrication.

Ion Migration in the Oxide

The mobility of sodium and also hydrogen ions in the silicon oxide is high and can lead to device failure by one of several mechanisms. Time-dependent dielectric breakdown phenomena are known to present a reliability problem in static MOS RAMs. Such breakdowns have been observed in silicon-gate MOS devices of both polarities. They differ from field-dependent oxide breakdowns in that the breakdowns occur with a log-normal distribution of times after application of the field. A dominant mechanism in time-dependent breakdowns is the emission of sodium ions from the metal oxide interface under positive bias. The ions then migrate under influence of the voltage toward the oxide-silicon interface, where they cluster around crystal defect sites. This is shown schematically in Fig. 15.20. The density of ions may build up until the oxide breaks

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Figure 15.20
Time-dependent dielectric breakdown: Sodium ion
emission from the gate metal drifts toward the
silicon-silicon oxide interface. The buildup of charge
in the interface traps result in oxide breakdown [1].

down, although if the defect or trap density at the interface is low, other degradation effects may be observed as a result of the ion concentration at the interface. Since a time delay occurs before the logarithmic (time) buildup of the breakdown, these potential failures can go undetected by the usual voltage overstressing tests, and thus are difficult to screen from the main population of devices.

The buildup of sodium ions at the oxide-silicon interface tends to reduce the field inversion voltage in n-channel transistors, resulting in a narrowing or even inversion of the channel, giving an anomalous current flow. p-Channel devices are also susceptible to cation migration. Any positive charge buildup will increase the conducting channel width and will thus not tend to degrade device performance unless the alkali ion contamination is present in large amounts, and punchthrough from source to drain occurs along the interface. If the oxide contains a large density of relatively immobile negative ions, then under high-temperature reverse bias the anions move toward the metallization and decrease the surface charge, thus lowering the surface potential. This is negative-ion instability, and its influence is dependent upon the purity of the thermally grown oxide.

The buildup of charge at the interface may be great enough to cause field

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inversion of the underlying silicon and create a conducting channel between adjacent diffusions. The result is a parasitic transistor.

Surface or interfacial charge spreading from biased metal conductors is the other major mobile charge failure mechanism prevalent in linear integrated circuits. It is a leading cause of parametric instabilities of bipolar linear ICs assembled in sodium-free hermetic packages. The interface of chip passivation layers, especially if a mismatch in layer resistivities exists, acts as a path for carrier conduction between metal interconnects. Over a period of time, the passivation close to the metal charges to a potential approaching that of the metal. The same phenomenon also can occur on the top surface of the passivation.

A parasitic MOSFET can develop in this situation, a situation often occurring within linear chips. The parasitic device produces a leakage current between p-type areas and adjacent isolation regions if the accumulated oxide charge is equivalent to a potential exceeding the turn-on voltage of the underlying collector surface (see Fig. 15.21).

Circuit techniques, such as the use of channel stoppers or metal field plates, often fall short of their intent by underestimating the pervasiveness of the phenomenon. The process engineer can also solve this problem by designing a process with a surface epitaxy collector turn-on voltage, Vth, high enough to prevent underlying bulk inversion.

The MOS Vth formula, as applicable to the epitaxy field region of a linear process, reduces to:

Figure 15.21
Cross section of linear IC input transistor structure showing formation of
parasitic transistor [3].

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(1)

which suggests two ways of achieving this. Either Qss (using a low-temperature oxidation step) or Qb (using surface doping enhancement) can be increased to attain the desired safe Vth value. In this formula, Qss is the fixed surface state charge density, Qb is the charge per unit area in the surface depletion region beneath the gate at the onset of inversion, and Cox is the gate oxide capacitance.

Hot Carrier Effects

The reduction of device channel and gate dimensions without a corresponding scaling of the voltages results in increased fields in the channel of an IC. Increased carrier energy results in a greater probability for surmounting the energy barrier at the silicon channel and for tunneling into the dielectric, thus creating hot carriers.

Hot carriers are those electrons and holes in the channel and pinch-off regions of a transistor that have gained so much energy from the lateral electric field produced by the source-drain voltage, or due to thermal currents, that their energy distribution is much greater than that which would be predicted if they were in equilibrium with the lattice temperature. As these carriers gain energy and penetrate the gate dielectric, the first critical level that they reach (~1.5 eV in silicon) is the ability to impact-ionize (create an additional electron-hole pair), which is manifested by source-drain (i.e., channel) current multiplication and substrate current creating a small gate current. If they continue to gain energy, they can reach a second plateau (~3 eV), where they can be injected over the energy barrier into the SiO₂. They become trapped in the oxide as shown in Fig. 15.22. Hot carriers can also tunnel quantum mechanically directly into the oxide at lower energies.

Depending on the sign of the carrier's charge and the direction of the electric field in the oxide at the point of injection, the electron or hole is either drawn toward the gate or driven back toward the channel (see Figs. 15.22 and 15.23). The direction of the oxide field above the channel is a function of both the gate and the drain voltage. While in the oxide, a percentage of the injected carriers will be trapped. These trapped charges can lead to transistor parameter shifts and subsequently to device malfunction. For example, electrons trapped above the channel of an n-type transistor can locally raise the threshold voltage and reduce the drain current. Holes trapped near the interface can lead to the formation of interface states that reduce the differential transconductance of a transistor. The reduced gain can subsequently lead to device failure.

There are three types of hot carriers, depending on where they originate: channel hot carriers, substrate hot carriers, and avalanche hot carriers. Channel

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Figure 15.22
Diagram of MOSFET structure showing the scattering into the gate
oxide of hot electrons, which may then be trapped [1].

hot carriers are those carriers that, in traversing the channel, experience an unusually low number of lattice collisions and thereby can accelerate to high energies. Substrate hot carriers are those carriers that are thermally generated in the substrate (below the inversion layer) and drift under the influence of a vertical electric field toward the interface. Avalanche hot carriers are those created in the avalanche plasma and that result from multiple impact ionizations under the influence of strong lateral electric fields.

Figure 15.23
Impact ionization and hot carrier injection. (Reprinted by
permission of Intel Corporation, copyright Intel Corp., 1991.)

Page 614

Figure 15.24 illustrates the three hot electron creation and injection mechanisms.

Channel and avalanche hot carrier mechanisms, which require large lateral electric fields in the channel, are precipitated by decreasing channel lengths as previously discussed.

Threshold aging, due to hot carrier phenomena, is also increased by increasing channel doping and oxide trapping efficiency and decreasing source and drain junction depths, temperature, and the value of the gate bias below the value of the drain bias.

Temperature increases the creation of substrate hot carriers. However, avalanche hot carrier creation usually dominates over the other two mechanisms.

Charge trapping is not the only mechanism by which hot carriers participate in time-dependent MOSFET instability. The introduction of hot carriers at the silicon-silicon dioxide interface can create additional interfacial trapping sites.

Hot carriers can be the cause of several reliability problems. The substrate current produced by impact ionization can induce bipolar latchup in transistors or four-terminal latchup in CMOS structures. Additionally, hot carriers injected into gate oxide can lead to the formation of interface states and trapped oxide

Figure 15.24
Three possible hot electron injection mechanisms in an n-channel MOSFET.

Page 615

charge. Over a long period of time, the charge buildup due to the trapped charge causes instability in the form of threshold shift or transconductance degradation, leading to device failure.

The number of trapped electrons depends upon the density of available traps in the silicon dioxide. This trap density can be increased by the radiation damage as a result of the radiative processes involved in the fabrication of VLSI devices, for example, electron-beam lithography and evaporation of aluminum producing soft x-rays, and reactive-ion etching. Furthermore, the hot electron effect is of increased concern as device geometries get smaller. Hot electrons can affect device threshold voltage, subthreshold current; and breakdown voltage, causing transistors to deteriorate and fail. Thus submicrometer geometry VLSI and ULSI circuits are more susceptible to hot electron damage than older generation (larger geometry) device structures.

What can be done during IC design and manufacturing to minimize the incidence of hot carrier injection? Integrated circuit manufacturers are doing the following:

1. Limits on the source-drain voltage must be imposed in order to inhibit the generation of hot electrons. This can be achieved through circuit design and device redundancy. Hot carrier degradation is a function of transistor geometry and bias voltages (which determine the electric fields) and of oxide quality (which affects the trapping characteristics). In order to understand their processes and minimize the incidence of hot carrier injection, IC manufacturers conduct extensive evaluations/characterizations of various transistor geometries to define and design minimum hot-carrier-susceptible structures. Different transistor geometries with varying channel lengths are stressed at ambient temperatures with different combinations of gate and drain voltages and are characterized for threshold voltage shift, transconductance reduction, and substrate current. Safe operating voltage conditions are determined for each device type channel length using the characterized acceleration factors and the 60-meV negative activation energy.

2. The substrate current for a typical CMOS inverter is associated with hot carrier injection and can be used to predict total device degradation as a function of supply voltage, device type width, channel length, load capacities, frequency, and input rise and fall times. In a typical VLSI wafer fabrication, failure rates are kept to satisfactorily low levels by keeping the threshold voltage and transconductance shifts within the natural tolerances of the technology. Substrate current levels that were associated with minimal hot carrier degradation can then be used as control limits during production to ensure that no devices with this wearout mechanism are manufactured.

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Metallization

Aluminum is the predominantly used interconnect metal. It forms good low resistance contacts to both n⁺ and p⁻ type silicon when alloyed at about 550°C for 10 min, and it is readily deposited by either resistance heating or electron-beam evaporation. Because the number of metal film layers is increasing (IC manufacturers use anywhere between two and five metal layers), and they occupy almost all the die surface topography, and because more than 50% of ASIC wafer processing is in the interconnect (metallization) system, the quality of the metal layers is critical to proper device fuctioning and long-term reliability. As such, the preponderence of VLSIC and ASIC problems/failures deals with those issues that affect the metal interconnection system. These are now presented.

Aluminum Stress Voids

As the complexity and number of layers of leading-edge ICs increase, it is certain that stress induced from deposited thin films will become an even greater concern. There are basically two types of stress: tensile, which will cause a stress-free wafer to become saucer shaped, and compressive, which will cause a domed appearance. Stress is also sometimes further defined as intrinsic, which develops during the film nucleation and growth process, and extrinsic, which results from the differences in the thermal coefficients of expansion of the deposited film and the underlying material.

How a deposited film comes to be tensile or compressive, and why that stress can change with temperature and/or time, is not always clear. It is perhaps best understood by examining how atoms and process by-products arrange themselves during deposition to form a crystalline lattice. If the rate at which atoms are free to move by diffusion is low compared to the rate at which they're arriving by the deposition process, they are more likely to reach their normal lattice site and produce a stress-free film. If, however, they are not free to move, and are jammed into place (such as with sputtering), the film tends to be compressive. Tensile films are formed when a process by-product is present during the deposition and later driven off as a gas. If the deposited atoms are not sufficiently mobile to fill in the holes that these departing by-products leave behind, the film will contract and be in tension.

The mobility of depositing atoms and the behavior of process by-products is dependent not only on the type of material, but on the deposition technique and deposition parameters. Aluminum, for example, has a low melting point and a correspondingly high diffusion rate even at room temperature, so it is usually fairly stress-free, even when sputter-deposited. By comparison, tungsten has a relatively high melting point and a low diffusion rate, so it tends to be compressive when sputter-deposited. But if tungsten is deposited by CVD, it is usually tensile as a result of vacancies left by process by-products. By comparison, nitrides deposited

Page 617

by plasma CVD are usually compressive due to the presence of hydrogen atoms within the lattice. But by thermally driving the hydrogen out, the films can be made to be highly tensile. A similar situation exists with some oxides, which can be porous enough to absorb or give off a large amount of water vapor. If they're full of water, they're compressive; devoid of water, they're tensile.

While controlling stress in these films is quite complex, it is now fairly well understood and achievable for most common films.

Stress voiding in aluminum interconnect lines is one of today's most serious reliability problems. First widely acknowledged in 1984, the problem has precipitated extensive experimental and theoretical investigations, with much controversy, and some confusion. Recent research shows that stress voids are not due solely to the stresses typically found in silicon nitride passivation layers or the neighboring dielectric, as has been commonly thought. The intrinsic stress in the dielectric is not a factor. The important role of the dielectric is simply that of constraining the metal; differences among dielectrics are primarily due to differences in elastic moduli. The deleterious effect of highly compressive silicon nitride is probably due to the excess hydrogen in the nitride.

Highly compressive nitride increases susceptibility to stress induced voiding. But it's not the compressive stress itself that causes the trouble; it's the hydrogen that can diffuse out of the nitride, into the aluminum, and make it more susceptible to voiding. As a consequence of either mechanical stress or electromigration, the presence of excess vacancies makes metal lines under passivation thermodynamically unstable with respect to void formation. Whether or not voids actually form depends on the driving force and the available sites for the heterogeneous nucleation of voids.

For the case of stress due only to thermal contraction, the driving force is limited and voiding can be suppressed by limiting the availability of heterogeneous nucleation sites. When the mechanical stress is due to high temperature reaction, however, the driving force can be much larger, and voiding more difficult to suppress. Vacancy concentrations produced by electromigration can be much higher than those due to thermal contraction stresses; consequently, material that is void-free after processing can develop voids under electromigration conditions.

Electromigration in Aluminum

Electromigration (EM) is the motion of the interconnect metallization due to momentum exchange from the electron current. A divergence of the metallic ion flux leads to void formation in the conductors and ultimately to open-circuit failure. A convergence of the ion flux can lead to hillock formation or a buildup of metal in local regions. This can result in short circuits to adjacent or overlying conductors. Contacts of aluminum-silicon to silicon can fail by voiding the metal or spiking. Spiking is the diffusion of silicon into aluminum, followed by the diffusion of aluminum into the silicon void; this eventually shorts the underlying

Page 618

p-n junction. When Si from the Al-Si metallization is driven by EM to the contact area, silicon nodules result.

Electromigration (discussed in Chapters 6 and 14) in aluminum is well understood, and design procedures have evolved in order to eliminate its occurrence in normal circumstances in aluminum-silicon devices. However, problems may arise due to poor process control, resulting in incorrect metal thickness, undercutting of the metallization during delineation, or simple scratches and smears. Such defects cause nonuniform current densities in the metal, leading to electromigration-induced failures. These processing defects can often be eliminated by screening at elevated temperatures and subsequent failure analysis.

Electromigration occurs at elevated temperatures under the influence of a temperature gradient or current density in excess of about 10⁵ A/cm², which is quite small considering the line widths of VLSICs. Electromigration is due to the thermal activation of aluminum ions, which are then transported by momentum exchange with the conduction electrons. The activation energy of the process is about 1 eV and is therefore easily accelerated by thermal means. The failure modes are characteristically cracks, voids, and nodules in the metal lines, causing open circuit failures. The cracks occur at the points of highest density, such as sharp bends or constrictions in the metal lines, and grow perpendicularly to the directions of current flow. Figure 15.25 shows how the electromigration mechanism forms voids near the negative contact and hillocks near the positive contact of the biased aluminum metal line. Figures 15.26 and

Figure 15.25
Aluminum metallization under high-current-density operation. Voids form along the
metal line and move toward the negative contact. Hillocks form toward the positive
contact as aluminum atoms start to pile up on defects. (Courtesy of Hi-Rel Labs, Inc.)

Page 619

Figure 15.26
Voids formed in a conductor. (Photo courtesy of Hi-Rel Labs, Inc.)

15.27 are scanning electron microscopy (SEM) photographs that depict voids in metal lines resulting from metal migration.

Hillocks are formed on deposited aluminum lines when metallized wafers are heated above the aluminum deposition temperature. They are due to a discrepancy in the linear expansion between the aluminum and the oxide. The hillocks grow by self-diffusion of aluminum (recrystallization of aluminum) to relieve the compressional stress caused by thermal expansion, normally resulting in voids elsewhere in the aluminum line. The growth of these hillocks can cause cracks in deposited oxide or passivation layers, leading to failures due to oxide shorts or contamination and corrosion of the metal. Figure 15.28 shows an aluminum extrusion hillock caused by electromigration.

When photoresist is applied over the oxide, it fails to adequately cover the larger hillocks. Subsequent oxide etch and resist strip steps then expose the hillock to unwanted contact with the next metal layer as shown in Fig. 15.29.

Data provided by Intel (Fig. 15.30) show typical failure distributions for aluminum alloy metallizations with and without a refractory barrier metal layer. The figure shows that sandwich interconnects (aluminum alloy on top of a refractory metal) have both longer T50 and reduced standard deviation. This improved reliability is a result of the redundant current path provided by the parallel conductor, as shown in Fig. 15.31.

The current and temperature acceleration factors are determined from the

Page 620

Figure 15.27
Corroded aluminum intermittent open due to voiding.

change in T50 with stress condition. Open- and short-circuit failure in aluminum-silicon alloy interconnects have a thermal activation of 0.5 eV, while aluminum-copper has a significantly higher activation energy (0.7 eV). Leakage in p-n junctions under silicon contacts is accelerated using a 0.8-eV activation energy, resistive contacts due to nodule growth have 0.7 eV activation energy, and open contacts due to voiding of the metal sidewall have the same activation energy as metal line failures (either 0.5 or 0.7 eV).

The solution to the problem of electromigration is twofold: (1) manufacturing process characterization and design and (2) manufacturing process optimization. An IC manufacturer must characterize (both temperature and current acceleration factors) a new metallization interconnect system and/or manufacturing process. The manufacturer must determine the maximum current allowed for each line width from metal line test structure measurements of various thicknesses and widths. These data, together with a design estimate (usually by computer simulation) of the current expected to be carried by the metal line, allow the designer to select those metal lines that are sufficiently wide to carry the required current reliably.

The density of the hillock formation in aluminum depends on the area of

Page 621

Figure 15.28
Hillock formation. (Photo courtesy of Hi-Rel Labs, Inc.)

the metal line; narrow lines have a significantly lower hillock density then wide lines. One way to control this problem is to keep all metal lines below a certain width so that the hillock density will not cause a yield problem. This may be difficult to do, especially for power-supply buses that must be wide in order to reduce the necessary current density in the metal. Electromigration and hillock resistance are improved by

Deposition of aluminum onto heated substrates

Deposition of a low-temperature oxide cap

Lower deposition temperatures of conventional LCPVD-grown oxide

Use of plasma-deposited oxide

Adding such elements as Cu, Ti, Pd, and Si to aluminum to form alloys

Fabrication of multilayer metal structures consisting of aluminum and other layers, such as Ti (titanium), Cr (chromium), and Ta (tantalum) layers sandwiched between aluminum layers; Ti (titanium)-W (tungsten)

Page 622

Figure 15.29
Oxide etch and resist strip steps expose the hillock to unwanted
contact with the next metal layer.

layers deposited below or on top of the aluminum film; and selectively deposited tungsten over the top and sidewalls of patterned aluminum lines

Open Metal at Oxide Steps

All ICs have metallization lines crossing the edges of oxide or dielectric. This edge (step) is likely to be a site of poor metal coverage. Generally, the oxide is preferentially etched to provide a beveled edge rather than a sharp step and thereby reduce the chance of a break in the metal line. If the thermal oxide has a layer of PSG upon it, cracks or breaks are much more likely to occur. This is a significant failure mechanism. The microcrack occurs at a steep upper step and is formed during the evaporation. The step is steep since the PSG etches at a much faster rate than thermally grown oxide, and produces an undercut structure (Fig. 15.32). The aluminum metallization may thus be incomplete over this step. The problem is aggravated by thin metal, narrow linewidths, or thick oxide or PSG layers. The most likely failures are tunneling over the oxide step (Fig.

Page 623

Figure 15.30
Electromigration time-to-failure distribution for aluminum-silicon with and without
barrier layer. (Reprinted by permission of Intel Corporation, copyright Intel Corp.,
1991.)

15.33) or breaks in the metal as a result of temperature cycling or due to electromigration in the thin high-current-density region creating a void.

Microcracks may be avoided by removing all the PSG layer prior to evaporation, using thick aluminum, rotating the substrate, using line or multiple sources during the evaporation; or shaping the slope of the step (tapering the edge). A new technique involves aluminum deposition under bias. This results in an even (uniform) thickness of the metal layer even across the oxide step, eliminating the microcrack problem. If all the PSG is removed, then the device may suffer from surface instability unless a passivation layer is deposited subsequently. Microcracks are difficult to detect by optical means since they are

Page 624

Figure 15.31
Cross section with refractory metal layer. (Reprinted by permission of Intel
Corporation, copyright Intel Corp., 1991.)

not usually normal to the surface. They are more readily observed by scanning electron microscopy as shown in Figs. 15.34 through 15.36.

Aluminum-Silicon Interactions

Inadequate control of conditions during alloying to form the ohmic contacts can give rise to several failure mechanisms.

A microcrack at an oxide step is a visible catastrophic manufacturing defect. However, a more insidious and prevalent defect today (1994) is that of metal thinning or poor step coverage at a contact, which could facilitate the

Figure 15.32
Schematic diagram of microcrack structure in aluminum metallization at an
oxide step [1].

Page 625

Figure 15.33
Tunneling of metal over oxide step, probably as a result of inadequate process
control (temperature) in laying metal down. (Photo courtesy of SEAL.)

occurrence of electromigration, ultimately leading to an open circuit. The root cause of this defect is poor contact definition (i.e., sidewall slope). Three different examples of this are shown in Fig. 15.37, with 90%, 90%, and 95% metal thinning (respectively, top to bottom). The three manufacturers of these VLSI circuits consider them to be acceptable structures and not deleterious to the long-term reliability of the ICs. I disagree and find them to be unacceptable.

Another problem results from overalloying due to excessive temperature or time or both. Generally, alloying is performed at 500550°C for 10 min, below the eutectic temperature (577°C), for aluminum-silicon, and the reaction takes place by solid-state diffusion. The aluminum penetrates the silicon and the metal-semiconductor interface moves downward. There is often appreciable dissolution of silicon in aluminum, precipitated some distance from the contact cuts. This can lead to the formation of silicon nodules (Fig. 15.38) and nonuniform current flow in the metal lines, eventually resulting in an open circuit. Overalloying results in pits at the contacts where the aluminum has penetrated the contact. Constrictions in the metal line width can lead to void formation at

Page 626

Figure 15.34
Classic microcrack at contact window.

the edges of the contact cuts. Excessive heat treatment during subsequent processing steps can lead to this mechanism of failure.

A failure mechanism related to overalloying arises from the tendency of aluminum to spread laterally between the silicon and the thermally grown oxide during alloying. This may lead to shorts and high local current density and field, and the associated reliability problems (see Fig. 15.39).

At very high temperatures, the silicon may form a eutectic with the aluminum, which will destroy the device. Alternatively, the metal can react with the thermal oxide or PSG layer and reduce the thickness of these layers. This increases the probability of gate oxide breakdown, at lower applied voltages,

Page 627

Figure 15.35
(a) Microphotograph of MOS IC with glassivation removed showing aluminum
metallization to polysilicon contact. This photo shows separation between the
contact window metallization and the metal line (open) due to process-induced
microcrack phenomena. (Photo courtesy of Reltronix Corp.) (b) Classic
example of poor step coverage. (Photo courtesy of Hi-Rel Labs, Inc.)

Page 628

Figure 15.36
Another microcrack example.

and the failure of the device. It is unlikely, however, that a device or circuit would be subjected to such a high temperature (>577°C) under normal processing or operating conditions.

Underalloying results in lifted aluminum conductors and bonding pads (contacts) as shown in Fig. 15.40.

Peculiarities of VLSI Metallization Systems

The need for small-geometry structures in fabricating VLSI circuits presents some quality and reliability concerns due to the use of device scaling techniques, vertical structures, multilevel interconnection/isolation techniques, the refractory metal or silicide compounds used, and the complexity involved in fabricating these devices, specifically,

Electromigration

Hot electron and breakdown effects

Wiring complexity and pattern sensitivity

Ohmic resistance and interconnections

Power dissipation in the gates

Page 629

Table 15.2 lists the problems most commonly encountered in using the current generation (1994) of CMOS VLSI circuits and ASICs, irrespective of who the manufacturer is. These problems/defects (outside of outright microcracks at the oxide step) normally don't show up in the infant mortality stage, but later in useposing reliability risks. Some of these have already been discussed while some have not. Only those germane to multilevel VLSI structures are now discussed.

Multilevel Structures

Aluminum is used extensively as the metallization in all levels in large-scale integrated circuits. As the line width is decreased, the current density increases and problems related to electromigration arise. Line widths of about 1 mm are taken as the lowest practical limit; below this, problems due to hot electron effects and non-Boltzmann conduction may also arise. This imposes restrictions upon the circuit design to avoid constrictions and current bunching. Metal silicides are used as the first-level metal contact in some ICs in order to avoid the electromigration difficulties. A multiple metal layer system multiplies and exacerbates the problems and sources of error in a single-layer metal system.

In multilevel structures the metallizations are separated by sputter or chemical-vapor-deposited layers of silicon oxide or PSG. The oxides are usually deposited under dry conditions, since it has been found that steam-grown oxides contain impurities that considerably reduce the breakdown voltage. The layers are generally about 100 nm thick. The interconnections between levels are made through windows cut into the oxide, known as vias. The slopes on the sides of the windows are angled so that the upper level of metal does not have to cross a sharp step. This eliminates the problem of microcrack formation in the metal at the oxide step, as discussed earlier. A similar problem occurs when second-level metal and deposited oxide cross the first-level metallization. The microcracks can be avoided by using a low-angle tapered edge in the delineated underlying metal. This technique is widely used in multilevel integrated circuits, and is shown schematically in Fig. 15.42. Any contamination or oxidation of the exposed aluminum in the vias before the next layer is deposited will result in a higher resistance contact due to reduced effective area. This may give rise to the hot spots and high current densities, which may lead to electromigration-related failures in the vias due to open metal.

Polysilicon gates are often used in multilevel CMOS devices in preference to aluminum metallization in order to improve the long-term reliability. Aluminum gates deposited by resistance-heating evaporation frequently contain ionic impurities that are mobile in the gate oxide, and thus the gate is subject to time-dependent breakdown wearout. The mean time to failure decreases as the oxide thickness is decreased, making this an important reliability consideration for scaled CMOS structures. A comparison of the maximum time to failure of MOS capacitors with aluminum and polysilicon electrodes has shown that the polysilicon electrode devices do not exhibit such a time-dependent breakdown

Page 630

phenomenon. The use of polysilicon gates carries the performance penalty of a lower speed-power product as a result of the high resistivity of the polysilicon, giving a large gate time constant in comparison to metal gate devices.

Dual-level metal (DLM) and triple-level metal processes were developed to reduce the amount of chip area devoted to interconnect structures. However, inherent in the switch to these multilevel processes are additional processing problems and failure mechanisms. The following discussions pertain to these mechanisms as applies to the dual-layer metal process.*

Short Circuit Problems. Shorts can be a serious problem in a DLM process. Shorts can be from metal 1 to metal 1 (type A), metal 1 to metal 2 (type B), and metal 2 to metal 2 (type C). Type A shorts are not unique to DLM processing, so they are not discussed here. Type B shorts can be caused by hillocks in the metal 1 layer. This was discussed previously.

Figure 15.37
Metal thinning caused by poor contact definition: (a) 90%, (b) 90%, and (c) 95%
metal thinning.

*Portions of these sections excerpted with permission from Ref. 4.

Page 631

Page 632

Figure 15.38
Silicon nodules from dissolution of silicon in aluminum.

Figure 15.39
Schematic diagram of overalloying of the aluminum-silicon contact leading to lateral
spread of the metal under the oxide [1].

Page 633

Figure 15.40
Lifted wire bonding pad due to underalloying of aluminum metallization.

Table 15.2 Currently Encountered Problems

VLSI circuits

Aluminum thinningpoor metal step coverage

Silicon nodules

Misaligned metal at contacts (vias)

High phosphorus content of passivation layer

Metal notches (Fig. 15.50)

ASICS

Open vias

Metal smears/scratches (Fig. 15.41), due to handling or probe equipment errors

Contact epitaxy

Metal shift voids

Metal shorts

Metal pattern shifts

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Figure 15.41
Metal scratches on dual-layer metal ASIC.

Figure 15.42
Schematic of multilevel structure with two levels of dielectric showing sloping contacts,
cuts, and vias connecting the metallization levels to reduce the incidence of microcrack
formation [1].

Page 635

Type C shorts can cause virtually zero yield if they are not controlled properly. The main cause of metal 2 to metal 2 shorts is what are called stringers or sleeves (see Fig. 15.43) along the edges of topography under the metal 2. This problem is caused by the incomplete etch of metal 2 along the edges of underlying topography, such as metal 1 or polysilicon. This incompletely etched metal then shorts two parallel metal 2 lines together. At these edges the metal 2 is thicker than on a flat surface, so it takes longer to etch. If the metal is wet-etched, this is not a serious problem; due to the isotropic nature of wet

Figure 15.43
(a) Prior to metal 2 etch, the metal thickness t' over a step
is larger than the metal thickness t' on the flat field. (b) After
the metal 2 etch, metal 2 stringers have formed along the
edges of underlying topography [4].

Page 636

etching, these stringers will be removed with a normal overetch. If the metal is dry-etched, however, this can be a serious problem. The dry etch is an anisotropic etch, so the lateral etching of the stringers will be relatively slow. This can result in a serious metal 2 shorting problem. A solution to this problem is to control the slope of the vertical steps; the shallower the slope, the less severe the problem.

Figure 15.44 illustrates two situations that can result in poor metal 2 step coverage. When metal 1 and polysilicon have coincident edges, with metal 2 running over the top, the result can be a severe step that metal 2 may not be

Figure 15.44
(a) With coincidental metal 1 on polysilicon, the resulting
step may be too large for metal 2 to cover completely.
(b) If metal 1 lies outside the polysilicon, the crevice that is
formed may cause a step coverage problem [4].

Page 637

able to cover, as in Fig. 15.44a. Or, if metal 1 and polysilicon edges are close to each other but not overlapping, there may be crevices in the dielectric that are difficult for metal 2 to cover, as in Fig. 15.44b.

Open Circuit Problems. Another possible cause of failure in multilevel metallization systems is the possibility of open second-level metal lines where they cross delineated first-level metal. These metal lines may be open or greatly reduced (thinned) in cross-sectional areas as a result of notches due to photoresist, microcracks at deep steps, the formation of tunnels under the metal filamentation of the metal, or shadowing due to evaporation from a point source at a low angle relative to the substrate. The SEM photograph of Fig. 15.45 and the cross section of Fig. 15.46 show thinning of the second metal layer when passing over the first metal layerclearly a step coverage problem. Figure 15.47 shows a void in the contact area. The via is slightly misaligned and does not fully overlap all of the via contact cut. The deposited passivation slightly filled the contact, creating a void.

Another danger is that metal 2 may cover these types of steps well enough to pass wafer testing, but the metal may be so thin that an electromigration failure can be created at that point. One way to solve these problems is to define the design rules such that these conditions cannot exist, or to eliminate the problem by improving the dielectric step coverage at these points.

Figure 15.45
SEM photo showing thinning of metal at right-hand step where metals
2 layer crosses metal 1 layer in dual-layer metal process. Notice that
all the conditions exist for a microcrack to occur at this point. (Photo
courtesy of Hi-Rel Labs, Inc.)

Page 638

Figure 15.46
Cross section showing 75% thinning of metal 2.

If the via is allowed to overlap metal 1 in the direction of metal 2 continuity, there may be a crevice created at the edge of metal 1 that metal 2 may not cover completely (see Fig. 15.48). This would be caused by the undercut of the oxide under metal 1 during the via etch. If the via is allowed to overlap metal 2 in the direction of metal 1 continuity, the metal 1 line will be attacked by the metal 2 etch during the overetch; this may cause an open and is, at best, a serious reliability problem (see Fig. 15.49). The best solution to this problem is to not allow vias to overlap contacts.

Metal Notching. Metal notching (mousebites) as shown in Fig. 15.50 is due to a number of causes, some of which are

Corrosion

Galvanic corrosion: Si-Al-Cu wafers are left in dump rinser for an extended period of time (i.e., 15 min)

Photolithography effects: metal surfaces are extremely shiny with a high amount of reflectivity

Compressive stresses of passivation layer

Page 639

Figure 15.47
Cross section showing void in the contact area.

The notches of Fig. 15.50 were caused by this latter condition: compressive stresses of the passivation layer. It is interesting to note that though the cause of the metal notches is the same, the ICs shown were manufactured by two different companies using different CMOS processes on two different continents.

If taken to the extreme, metal notches will result in an open metal line.

Step Coverage Problems. The step coverage of metal 2 into a via can be a problem. The slope of the via walls must be controlled to allow maximum

Figure 15.48
When the via is allowed to overlap metal 1, metal 2 may not
cover the step that is created [4].

Page 640

Figure 15.49
When the via is allowed to overlap metal 2, the metal 2 etch will attack the
metal 1 during the overetch and create either a yield or a reliability
problem [4].

coverage by metal 2. The native aluminum oxide on the metal 1 in the vias can cause an electrical open if it is not removed. This removal is usually done immediately prior to the metal 2 deposition by the use of RF sputtering of the substrate (back-sputtering). This removes the aluminum oxide and does not allow it to regrow, because the substrate is under vacuum and metal 2 deposition immediately follows. Step coverage can be improved by doping the aluminum with copper and/or using various deposition techniques, one of which is described in Ref. 5.

Aluminum electromigration is of more concern in a dual-level metal process than it is in a single metal process for two reasons. First of all, metal 1 is usually thinner in the DLM process to improve metal 2 step coverage. This can create higher current densities in metal 1 if care is not taken. Second, because of the step coverage problems that have been previously discussed, metal 2 may be thinner at certain locations, thus creating areas where the current density may be too high.

These problems may be overcome by controlling the design so that the maximum allowable current density is calculated based on these existing conditions; or these situations can be improved through process innovations. Alternatives to Al-Si alloys, such as Al-Si-Cu, have demonstrated improved electromigration characteristics, but this particular alloy is difficult to etch; others may prove to be more suitable, or new etch techniques may be developed. The metal 2 electromigration problem can be significantly improved by minimizing the number of steps and maximizing the metal 2 thickness over these steps.

Device Scaling. Device-scaling techniques (also see Chapter 6) are employed to improve the performance and density of devices and for economic reasons (increase the number of gross dice per wafer and thus revenue per wafer). High-performance CMOS technology has been developed by reducing the channel length, gate oxide thickness, and junction depth while retaining the same

Page 641

Figure 15.50
Examples of metal notching. (a) 16-Mbit Static RAM; (b) 2-Mbit Flash memory.
Courtesy of ICE Corp., STATUS 1994.)

Page 642

supply voltages to maintain equipment/system compatibility. Integrated circuit power supply voltages are being scaled as well. The reason is twofold:

1. Practical physical limits have been reached. As feature sizes shrink below 0.5 mm, a 5-V power supply is not practical (Fig. 15.51)thus the change to 3.3 V and lower. In the late 1990s it is expected that ICs with operating voltages of 2 V and less will be required.

2. To reduce power consumption as driven by the portable PC market. Since power consumption is proportional to the square of the supply voltage, lowering the voltage from 5 to 3.3 V can reduce the power by as much as 70%.

Examples of IC design/process scaling roadmaps are presented in Tables 15.3 through 15.6. Notice that as the voltage is scaled, the delay increases (Table 15.3), but as the technology is scaled for the same power supply voltage, the delay improves. This is demonstrated three times as the voltage is scaled from 5 to 3.3 to 2.5 to 1.5 V in Table 15.3. Table 15.4 depicts a gate array process roadmap from LSI Logic Corp. Notice the aggressive feature size reductions and the increase to five metal layers as the power supply voltage is reduced from 5 to 3.3 to 2.4 to 2.0 V. Lastly, Tables 15.5 and 15.6 show a CMOS scaling trend chart to the year 2000 and the Semiconductor Industry Association's (SIA) technology roadmap to the year 2007, respectively. Implicit in all of these tables is the dramatic reduction in gate oxide thickness and resulting increased concern for wafer fabrication-induced defects/errors.

Gate oxide breakdown is thus a primary failure mechanism in such devices

Figure 15.51
Gate oxide thickness versus gate length versus supply voltage. (Courtesy of
ICE Corp., STATUS 1994.)

Page 643

Table 15.3 Example of Power and Speed Improvement by CMOS Technology Scaling

Technology
(mm)

Vcc (V)

Delay/stage
(Fin = Fout = 3) (ns)

1.0

5.0

1.1

1.0

3.3

1.7

0.5

3.3

0.6

0.5

2.5

0.7

0.25

2.5

0.3

0.25

1.5

0.4

Table 15.4 LSI Logic Process Roadmap

Process Name

LLC70

LLC60

LLC50

LLC35

LLC25

Drawn gate length (mm)

0.70

0.60

0.50

0.35

0.25

Channel length (mm)

0.55

0.45

0.38

0.25

0.20

Metal layers

2/3

2/3

4/3

5/4/3

5/4/3

Metal pitch (mm)

3.8

2.4

1.4

1.0

0.8

Supply voltage (V)

5/3.3

5/3.3

3.3

2.4

2.0

Maximum die size (mm)

17

20

23

26

30

IV1 performance (ps)

120

100

85

70

55

Prototype (year)

1991

1992

1993

1995

1997

Source: ICE Corp., STATUS 1994.

Table 15.5 CMOS Scaling Trends

19931994

19961997

19992000

Line widths

0.5 mm

0.35 mm

0.25 mm

Power supply

3.3 V

3.3 V

2.02.5 V

Gate oxide thickness

11 nm

9 nm

67 nm

Gate length (n-channel/p-channel)

0.5/0.6 mm

0.35/0.35 mm

0.25/0.25 mm

Switching speed (fan-out = 1)

95 ps

68 ps

45 ps

Drain structure

NMOS

FOLDa
Graded diffused drain
Conventional

PMOS

Conventional
Lightly doped drain
Conventional

Gate structure
n⁺ Polysilicon
n⁺ Polysilicon NMOS
p⁺ Polysilicon PMOS
n⁺ Polysilicon NMOS
p⁺ Polysilicon PMOS

aFOLD, fully overlapped lightly doped drain.

Source: ICE Corp., STATUS 1994

Page 644

Table 15.6 Semiconductor Industry Association Technology Roadmap

Technology Issue

1995

1998

2001

2004

2007

Feature size (mm)

0.35

0.25

0.18

0.12

0.10

Gates/chip

800K

2M

5M

10M

20M

Bits/chip

DRAM

64M

256M

1G

4G

16G

SRAM

16M

64M

256M

1G

4G

Chip size (mm²)

Logic/microprocessor

400

600

800

1000

1250

DRAM

200

320

500

700

1000

Wafer diameter (mm)

200

200400

200400

200400

200400

Number of interconnect levels (logic)

45

5

56

6

67

Maximum power (W/die)

High-performance

15

30

40

40120

40200

Power supply (V)

Portable

2.2

2.2

1.5

1.5

1.5

Number of I/Os

750

1500

2000

3500

5000

Performance (MHz)

Off-chip

100

175

250

350

500

On-chip

200

350

500

700

1000

Source: ICE Corp., STATUS 1994.

due to the increased field as a result of scaling the oxide thickness (the gate oxide is typically less than 70 nm). High-voltage screening can be used to eliminate weak oxides, which could otherwise give rise to reliability problems.

Device scaling has a major impact on reliability. Wear-out failure mechanisms are rapidly accelerated by scaling, specifically,

Electromigration

Hot carrier injection

Oxide wear-out

Contamination

ESD

Interdiffusion

Fatigue due to operating thermal cycling

As geometries scale below 1 mm, it becomes necessary to make some significant modifications to all processing steps, especially the DLM (or multilayer metal) process. The topography gets troublesome as geometries become smaller. Dimensional control becomes more difficult for small geome-

Page 645

tries on rough terrain. The metal stringer problem described earlier can be severe when using dry metal etching on fine metal lines over steps. Limiting the current density in the metal lines to avoid electromigration failures can be a problem as the metal lines become narrower. And an entirely new problem is created as the spaces between steps to be covered by metal 2 approach twice the intermetal dielectric thickness. The dielectric on the edges of these steps can touch or nearly touch each other and form voids or crevices that are nearly impossible for metal 2 to cover (see Fig. 15.52). This is a problem that does not exist at all on larger geometry processes. It is also possible that small contacts can create the same problem when metal 2 passes over them.

This problem can be controlled by defining the design rules so that these spaces are not allowed to exist on the wafer. However, this can present a serious constraint to the designer. If automatic alignment is used for the masking, the alignment may be sensitive to the slopes and topography of the contacts, metal 1, vias, and metal 2. This can make implementation of automatic alignment on a dual-level metal process difficult.

All of the problems discussed in this section can be significantly improved by surface planarization, which was discussed in Chapters 2, 6, and 11.

One disadvantage of planarizing in general is that automatic alignment depends on surface topography for light reflection. A planar dielectric will nearly remove the steps that are normally used for alignment of the metal 2 mask (during alignment of the metal 2 mask, the metal is on the wafer and prevents most of the light from reaching the dielectric; the automatic alignment system keys off of the steps in the surface of the metal). This could lead to some very cumbersome alignment techniques, or it could lead one to revert back to manual alignment for some levels in a DLM process.

Figure 15.52
A crevice is created as the space between steps is nearly twice the
dielectric thickness [4].

Page 646

Other Metallization Systems

Alternatives to the aluminum-gold system have been employed, in particular for operation at high chip temperature, in order to reduce the degradation problems associated with intermetallic reactions; among them are a tungsten- or molybdenum-gold system. The use of platinum of Pt-Ti as a barrier layer between the gold and the contact metal is becoming increasingly popular. This is the basis of beam-lead metallization on silicon devices (see Fig. 15.53).

The refractory metals are chosen for their adhesiveness to the oxide layer and their unreactive nature in comparison with aluminum. They act as a barrier layer between the gold and silicon. The gold overlay provides the low-resistance interconnect between devices, and presents no intrinsic bonding difficulties. The molybdenum-gold system has been widely used and the degradation mechanisms are known. One problem is the undercutting of the molybdenum layer during delineation of the system. Molybdenum, unlike aluminum, is not self-passivating and its oxide is water soluble, leading to the possibility of solution entrapment in the undercut and thus galvanic corrosion. The molybdenum will dissolve at the anode due to self-biasing, creating voids or opens in the metallization. Conducting dendrites of corrosion products have been observed to cause shorts between metal lines. Tungsten is expected to show better reliability in this respect since the oxides are far less soluble in water, being affected only by alkaline solutions. The reliability of these systems is greatly improved by hermetic packaging and suitable passivation. Silicon nitride deposited by reactive ion

Figure 15.53
Diagram of the beam-leaded structure [1].

Page 647

etching is often used as the passivation layer, protecting the molybdenum from oxidation at temperatures up to 1200°C.

Gold migration through pinholes in the contact metal can cause degradation. Gold diffuses very quickly in silicon, and the eutectic temperature is quite low at 373°C, so local hot spots can result in rapid dissolution of silicon and failure of the device. Poor adhesion of the gold to the molybdenum lines is observed at high temperature and electrical stress. Scratches and similar processing defects also contribute to reliability problems of the system.

Beam-lead metallizations such as are used for TAB applications are gaining acceptance due to their high reliability. For example, a Ti-Pt barrier is employed between the plated gold beams and the contact metal. The thick beams serve as the interconnect metal; the devices are mounted in a flip-chip manner by thermocompression bonding of the beams to the goldplated circuitry on the header. The contact metal may be aluminum, especially in multilevel systems, although metal silicides are becoming increasingly popular for the ohmic contacts. The reliability of platinum and several refractory metal silicides as contact metallizations has been investigated. A passivation layer of silicon nitride is usually deposited to hermetically seal the metallizations as a protection from corrosion, and to getter any alkali ions present in the underlying oxide.

Pinholes in the platinum barrier layer can result in gold-titanium intermetallic formation at high temperatures. This results in high contact resistance due to void formation. Poor process control can lead to contamination between the metal layers which will result in adhesion problems. The improvement in reliability is due to the elimination of wire bond failures and purple plague, achieved by directly bonding the beam-lead contacts to the package header. The beam-lead configuration reduces parasitic inductance commonly associated with wire bonds. Indeed, the beams' dimensions can be tailored to match their inductances and capacitances to the circuit.

Other metallization structures such as silicides and those used in the TAB structure sandwich (Al-TiW-Au) were previously discussed in Chapters 2, 3, and 6.

Intermetallic Reactions

Intermetallic reactions arise from the need to make a connection from the chip to the outside world. The most common wire bond is made by gold thermocompression bonding achieved by a ball or wedge bond of fine gold wire to the aluminum contact pad. Operation or screening of the device at elevated temperatures frequently results in the formation of gold-aluminum intermetallic compounds at the bond. This is known as purple plague due to the color of the predominant compound AuAl₂. Figure 15.54 shows a SEM photo of the purple plague phenomenon.

Page 648

Figure 15.54
SEM photo of purple plague.

The presence of silicon acts as a catalyst to the reaction, increasing the degradation of the contact. The intermetallic compound is hard and brittle but strong and conductive, and in itself does not degrade the performance of the bond. The presence of voids under the bond, due to the Kirkendall effect, tends to weaken the bond strength and increase the resistance. Accelerated growth and coalescence of the Kirkendall voids are also promoted by conditions that cyclically stress the interconnection. Temperature cycle screens, for example, create such stress conditions in interconnections. The voids tend to agglomerate and cause the bond to lift, resulting in device failure. The voids form due to differing rates of diffusion of the aluminum and gold. Opens can occur in the aluminum some distance from the bond, due to mass transport of ions, and at constrictions in the aluminum lines. It is generally accepted that if the device is

Page 649

stored or operated at temperatures below 150°C then the gold-aluminum system provides a reliable bond.

Equation 15.1 and the graph of Fig. 15.55 show the effect of junction temperature on the rate of formation of gold and aluminum intermetallics.

MTTF = A exp (EaKT) (15.1)

where A is a constant, Ea = 1.0, K = 8.63 × 10⁻⁵, and T is absolute temperature (K). The plot of Fig. 15.55, which is the relative mean time to failure (MTTF) in hours, has been normalized to 1 at 125°C. Figure 15.56 illustrates a cross section of gold wire bond on aluminum metallization with a layer of intermetallics.

A basic cause of purple plague problems is inadequate process control. Two examples serve to illustrate this point. One is inadequate attachment of the die, which leads to excessive die temperatures during device operation. The other is excess deformation of thermocompression wire bonds, which enhances the susceptibility of the bond to purple plague problems.

An alternative is to use a single-metal system: aluminum-aluminum bonds made by the ultrasonic bonding technique. The aluminum wire contains 1%

Figure 15.55
Intermetallics mean time to failure.

Page 650

Figure 15.56
Cross section of wire bond showing purple plague.

silicon or magnesium to harden it, and no intermetallic formation is observed. The strength and reliability of ultrasonic bonding have been found to be better than gold thermocompression bonds for high reliability applications; however, aluminum wire-bonding systems are not needed in plastic ICs.

The reliability of bonds in general is dependent upon the incidence of processing errors. Over-or underbonding produces weak bonds, which can cause failure through mishandling or thermal stress. These bonds are easily screened, either optically or by centrifuge testing, which stresses the wire lead. Thus the weak samples can be eliminated from the main population.

Summary of VLSI Circuit Defects and Failure Mechanisms

Many potential sources of defects were non-issues at SSI, MSI, and LSI levels. However, at the submicrometer geometries encountered in VLSI circuits, combined with the complex vertical thin-film sandwich structures developed to obtain the desired chip density/performance requirements, these defects become serious issues. Table 15.7 closes this chapter by summarizing the failure mechanisms/defect issues that were discussed and are peculiar to VLSI circuits.

Page 651

Table 15.7 Summary of Die-Related Failure Mechanisms Peculiar to VLSI Circuits (Submicrometer Geometries)

VLSI circuits exhibit increased susceptibility to

Oxide faults

Pinholes in thin oxide layers resulting in increased leakage current

Hot carrier effects/channeling: acceleration of carriers in MOS conduction channel into gate oxide, producing threshold shift, drain current degradation, and breakdown voltage degradation

Layer separation

Caused by thermal mismatch between aluminum or copper-silicon alloys and die substrate

Low-temperature oxide film picks up moisture from the atmosphere, swelling and becoming compressive; metal deposited on this film literally explodes, often rupturing passivation layer as well

Metal interconnect and stress voiding

Metal microstructure has a first-order effect on stress along line length

Passivation type has a first-order effect on stress through line thickness

Stress distribution correlates with metal voiding susceptability and rate

Mechanical stress

Device geometry may impact reliability; devices with smaller widths have reduced lifetimes and higher stress levels

Variations in device hot carrier lifetime of over two orders of magnitude have been observed within a given wafer and correlated with physical stress

Metallization (small pitch multilevel metal systems) defects

Stress cracking:

(1) Narrow lines cracked after sitting on shelf for 12 years due to built-up mechanical stress; large differences in thermal expansion properties between metal lines and silicon substrate and passivation layer thermally induced stress; e.g., INTEL, TI, AMD, Mitsubishi, and Matsushita

(2) Aluminum overdoped with Si to prevent spikes causing dissolution and open lines; e.g., MOSTEK

(3) Aluminum notchespassivation (nitride, oxynitride) stress causing notches, especially on thin metal lines

Step coverageopen circuits (020% step coverage over multilevel metal systems)

Electromigrationdue to decreased line widths, closer on-chip metallization, thinner metal (increased current density), and smaller package lead spacing

Silicon nodule formationexcess Si content in aluminum leading to increased contact resistance and susceptibility to electromigration

Via opens

Metal thinning at contacts (vias)

Failure mechanisms of TiN/Pt and TiN/Cr structures with Al metallization possibly involve nitride decomposition and formation of AlN and pinholes

Metal misalignment

(table continued on next page)

Page 652

Table 15.7 (Continued)

EOS/ESD events

Increased device sensitivity

Latch-up

Metallic and ionic contaminates and gas and chemical impurities resulting in electrolytic corrosion and other manufacturing defects

Bond pads must be protected from ionic contamination during the assembly operation

New wear-out mechanisms

Electromigration

Hot carrier injection

Oxide wear-out and breakdown

Contamination

ESD

Interdiffusion

Fatigue due to operating thermal cycling

References

1. M. J. Howes and D. V. Morgan, eds., Reliability and Degradation, Semiconductor Devices and Circuits, John Wiley and Sons, New York, 1981. Reprinted by permission of John Wiley and Sons.

2. R. G. Wagner et al., Extent and cost of EOS/ESD damage in an IC manufacturing process, EOS/ESD Symposium Proceedings, Orlando, Florida, September 1993.

3. B. Hollins, Processing linear devices for performance and reliability, Semiconductor Int. February (1984). Reprinted with permission.

4. M. R. Gulett, Dual-Metal CMOS for semicustom or custom designs, VLSI Design January (1985).

5. S. R. Wilson et al., 4 Level metal layer, high performance interconnect system for bipolar and CMOS circuits, Solid State Technol. November (1991).

Selected Readings

1. H. H. Hoang, and J. M. McDavid, Electromigration in multilayer metallization systems, Solid State Technol. October (1987).

2. W. L. Smith et al., Evaluating voids and microcracks in Al metalization, Semiconductor Int. January (1990).

3. D. Pramanik and V. Jain, Barrier metals for ULSI: Processing and reliability, Solid State Technol. May (1991).

Page 653

4. R. Buck, The mystery of the cracked dice: A detective story, Semiconductor Int. June (1992).

5. J. Finn, Stress voids: How to measure and verify at the wafer level Semiconductor Int. June (1992).

6. Extensive documentation of electromigration, time-dependent dielectric breakdown (TDDB), hot carriers, and other VLSI circuit failure mechanisms may be found in the annual proceedings of the International Reliability Physics Symposium.

Page 655

16
Packaging- and Assembly-Related Causes of IC Failures

Overview

The package, as discussed previously, provides the physical support for the IC, enables electrical connection to be made to the external circuitry, must present an inert and dry atmosphere to the surface of the IC, must provide a thermal path for heat generated by the IC to be safely conducted to the external environment, and must provide protection against the external environment.

As with wafer fabrication, package reliability concerns itself with the various materials, interfaces, and techniques used in the assembly process. These include

The package cavity macroenvironment

The interconnections: wires, bonds, solder

The thermal loads

Material stability

Conductor complexity

Hermetic seal integrity

Package-induced mechanical stresses

Page 656

Table 16.1 Assembly- and Package-Related Failure Mechanisms

Open/shorted wires

Lifted/broken wire bonds

Misplaced wire bonds

Multiple wire bonds

Lifted chips

Improperly sealed packages

Die attach defects

Excessive seal material

External lead defects

Overbonding/underbonding

Residual process chemicals

Human-derived chemical agents from operators (spittle)

Moisture

Outgassing polymers (poorly cured organic adhesives such as epoxy die attach)

Poor lead dress

Corroded wires

Die-attach considerations

Platings, carriers, composites

Feedthroughs

Each element of the packaging process provides some form of protection for the device. Electrical failures are commonly due to some form of corrosion (precipitated by moisture), which may be related to the integrity of the surface passivation layer or the hermeticity of the external package. Mechanical failures arise from mishandling of the device, or physical shock resulting in a breakage of the device.

Table 16.1 presents a listing of commonly encountered assembly/package- related failure mechanisms for all types of ICs/packages. A hierarchical (Pareto) list of gate array failures, for a specific ASIC manufacturer (a subset of Table 16.1), is shown in Table 16.2. As can be seen, assembly and package related failures dominate, accounting for three-fourths of all IC failures. Tables 16.3

Table 16.2 Gate Array Failures (%)

Assembly

41

Package

37

Overstress (EOS/ESD)

8

Cause unknown

8

Wafer fabrication

6

Page 657

Table 16.3 Predominant Gate Array Package-Related Failures

Cause

Corrective action

Bond pad corrosion
Optimize plastic molding cure time.

383 PPGA die corrosion
Use sandwich passivation.

383 PPGA substrate metal open
Implement chemical desmear process.

and 16.4 provide the backup detail for Table 16.2; they list the top three package-related and assembly-related root causes of failure, respectively. This data is then used to drive permanent corrective action and thus continuous improvement.

Figure 16.1 diagrams the different causes that possibly result in a package failure. It is obvious that errors in package design and assembly processing can lead to package-related failures. More subtle is the fact that not all package-related mechanisms have their root cause in the package. It is possible that errors in the wafer process or die design interact with the package and lead to failure. Then there is the issue of board assembly-induced defects. PC board assembly processes can stress the package and lead to subsequent failure, especially with the proliferation of surface-mount technology (SMT). With SMT the IC and the PC board interconnect must be viewed as one system (entity). Consequently, problems with the application and use of these devices must be considered. These include

Assembly problems (attachment to PCB)

Handling problems (mechanical damage, ESD, etc.)

Solder attachment reliability problems

Solder mechanical support problems

Workmanship problems

Package failure is also determined by the environment. Environmental stresses include temperature, humidity, chemical stress, mechanical stress,

Table 16.4 Predominant Gate Array Assembly-Related Failures

Cause

Corrective action

208 PQFP Die paddle tilt causing stitch bond neck break

Modify molding compound and specify maximum die paddle tilt.

Stitch neck break

Optimize bonder parameters and wire loop height.

Ball neck break

Optimize bonder parameters and wire loop height.

Page 658

Figure 16.1
Block diagram of root causes of failures. (Reprinted by permission of Intel
Corporation, copyright Intel Corp., 1991).

electrical stress, or any combination of these. Traditionally, the environmental stresses indicated in Figure 16.1 are the stresses a device undergoes in its service life or a controlled accelerated simulation of that stress. In recent years, customers' assembly processes, particularly surface-mount processes, have been found to contribute to package failures.

Finally, the interaction of the physical failure mechanism with the circuit on the die leads to a specific electrical manifestation: the failure mode. It often requires detailed knowledge of the circuit to interpret the failure mode in terms of a failure mechanism.

The most prevalent packaging- and assembly-related failure mechanisms are now discussed.

Surface Passivation and Corrosion

The passivation layer, which is the last step in the wafer fabrication process, is frequently a glass or other dielectric layer deposited onto the device surface. Chemical vapor deposition (CVD) of PSG is often used as the passivation layer and acts as a getter for any mobile sodium ions that may be present in the underlying silicon dioxide. Plasma-deposited silicon nitride is also used as a passivating layer because it is an effective barrier for alkali ions that may be left on the device surface after the final wash. However, silicon nitride can give rise to a change in the surface potential, which in turn affects the threshold voltage of MOSFET and certain bipolar devices. A layer of Al₂O₃ is found to be an acceptable passivation for such devices. The dielectric passivation layer can

Page 659

introduce further charge trapping and storage effects and give rise to interface conduction due to the activation of traps. These effects can contribute to unreliable operation and can play a part in the corrosion process.

At times, adhesion difficulties have been experienced with the dielectric layers. Because the CVD films are in tensile stress, poor adhesion may cause localized lifting or cracking of the passivating layer, which can result in enhancement of the corrosion of the metallization. This is a particular problem where the conductor passes over topographical steps in the underlying oxide.

An alternative passivating material that is often used in low-power devices, especially those encapsulated in molded plastic packages, is RTV silicone. This is a plastic coating that bonds chemically to the surface of the device, and thus prevents any interface conduction. The organic plastics used for passivation purposes are often made from proprietary recipes, which have a large number of ingredients and can be a source of contamination as well. These impurities may attack the device surface directly or become activated under humid conditions.

Failures due to corrosion of the metallization are frequently associated with defects in the passivation, such as cracks and pinholes. These defects act as sites for the entrapment of contaminants or moisture, which is instrumental in the corrosion. The failure modes are generally due to electrical opens caused by voiding of the metal, or shorts due to either conductive particles or corrosion products between the metal traces.

Aluminum has a stable oxide and is therefore self-passivating. In the absence of ionic contamination it is a stable metallization system. In the presence of ionic contaminants such as sodium and chlorine, the oxide can be broken down and the aluminum attacked under the application of electrical bias. The phosphorus content of the silicon dioxide layers used in the passivation is an important factor in the reliability of the devices. The phosphorus is added both to provide mechanical stability of the glass coating and as a getter for mobile sodium ions. However, it also affects the tensile stress of the film. Too little phosphorus causes cracks in the passivation layer, while too much phosphorus results in aluminum corrosion. The cracking of the passivation increases the susceptibility of the underlying aluminum to corrosion by impurities. An excess of phosphorus in the glass promotes leaching of P₂O₅ from the PSG by moisture, resulting in the formation of phosphoric acid, which readily attacks aluminum as shown in Figure 16.2. In phosphorus-related electrochemical corrosion, the cathode is attacked, distinguishing it from chloride-induced corrosion. Additionally, the use of phosphorus-doped glass causes charge leakage from the gates of MOS ICs.

Improvements in device passivation have produced protective films of high integrity and moisture imperviousness, dramatically reducing aluminum line corrosion, making the corrosion of unpassivated aluminum pads the most common failure.

Page 660

Figure 16.2
Phosphoric acid attack on die metallization due to a combination of
excess phosphorus in the glass and high water content in the package.
(Photo courtesy of Hi-Rel Labs, Inc.)

Galvanic corrosion can occur in metallization systems of dissimilar metals, for example, the molybdenum-gold system, or in aluminum metallizations with gold bond wires. Corrosion occurs at exposed regions such as bonding pads and can proceed along the passivation-metal interface. Molybdenum oxide is water soluble, and this can lead to undercutting of the gold, solution entrapment, and consequently corrosion. Aluminum-gold reactions are evident as intermetallic formation, and were discussed previously.

Moisture, which is probably the single most damaging agent affecting the lifetime of ICs, is required for corrosion to occur. How does moisture get to the die? Moisture is often trapped in the cavity of a hermetically sealed IC during the assembly process or absorbed over time by plastic IC packages directly through the plastic material or through separations between the plastic and the lead frame. Additionally, certain materials that are used in the IC fabrication/assembly process inherently contain moisturepolymers used for die attachments, gold-plated surfaces, and even the plastic used for the package itself. Human effluvia (spittle) deposited on the IC surface during the die attach-wire bond-assembly process is also a cause of moisture. The environment external to the package is another source of moisture. Moisture can enter a package through polymers used in the seals, through the package material, through cracks in either

Page 661

the package or the seals, or through small voids between the plastic material and leadframe in molded plastic packages. Furthermore, moisture may induce crack growth in package materials, destroying the hermetic seal.

Once in a package, moisture attacks the die at its weakest (exposed or unprotected) pointthe wire bond at the die bonding pad. Moisture-related mechanisms usually occur in one of two ways: from metallization being eroded from bond pads in conjunction with impurities (such as halogens), or as the result of an electrochemical reaction in which corrosion of the aluminum occurs. The former is seen after extended pressure-cooker tests, the latter after extended temperature-humidity-bias (THB) tests. The chemical reactions involved in both mechanisms have been well documented.

Electrochemical Migration

The technology of metallization in integrated circuits is based on either aluminum or gold. The presence of moisture within the device package has long been known to lead to electrolytic corrosion of aluminum. This corrosion results in a well-documented failure mode. The chemistry of gold suggested that metallization schemes using this noble metal would be free from susceptibility to such electrochemical attack.

However, it has been found [1,2] that ICs using a Ti/W/Au metal system are subject to failure mechanisms based on electrolytic corrosion. The migratory gold resistive short (MGRS) failure mode is one example of this mechanism and results in the formation of filamentary or dendritic deposits of gold between adjacent stripes on the IC chip. This reaction requires the presence of a sufficient amount of water, reactive elements such as the halogens, a bias voltage between adjacent stripes, and the activation of the cathodic (-) stripe. Gold ions are transported from anode to cathode through a film of moisture adsorbed on the surface of the chip; halide ions are probably involved in the transfer.

The failure is seen as the abrupt decrease of resistance between two or more adjacent metal stripes. Integrated circuits with MGRS exhibit excessive currents and leakage current instabilities. These instabilities are observed as the applied voltage is increased. The shorting currents are on the order of milliamperes. SEM micrographs of failed parts reveal that fernlike or dendritic gold deposits have formed a bridge between metal stripes.

The dendritic deposits appear to progress from the negatively biased stripe (cathode) toward the positive one (see Fig. 16.3). The general form or morphology of the growth is quite specific and similar to that of deposits found in electrochemical silver migration. This well-known phenomenon results from the surface transport of silver which is driven by large electric fields. This surface transport is strongly dependent on the presence of moisture and on the nature of the substrate surface.

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Figure 16.3
Example of dendrite growth due to electrochemical migration.

This failure mechanism can become very prevalent in VLSI circuits, both internal to the package and at the external leads, as long as the conditions for electrochemical migration are present: reactive elements, a continuous layer of adsorbed water between neighboring gold conductors, and an applied voltage for a period of time. The following VLSI circuit characteristics will increase the incidence of electrochemical migration in the future.

1. The increased use of thin film vertical sandwich structures (such as Ti/W/Au) in both silicon and gallium arsenide devices

2. Closer on-chip metallization spacing

3. The use of smaller package lead spacing for large pin count devices (25 mil and 50 mil lead separation)

Die Bonding Issues

Dice in IC packages are attached to substrates using materials that provide the mechanical and thermal connection to the substrate. The IC die is mounted upon a metallic header or lead frame or ceramic substrate by means of a low-melting-point solder such as gold-silicon or gold-germanium eutectic alloy, or by a glass

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or epoxy bond. The strength of the alloy bond may be reduced by the occurrence of solid-state diffusion reactions, leading to the formation of brittle intermetallic compounds. The composition of the glass must be carefully controlled in order to reduce the incidence of impurities. Small concentrations of oxide impurities can change the reaction rate and temperature range of the devitrification process that produces the bond, resulting in a weak or brittle bond. In all the systems, the temperature must be controlled to ensure the complete alloying of the eutectic solder or devitrification of the glass and the thermal curing of the epoxy, otherwise a weakened bond will result.

The coefficient of thermal expansion (TCE) rates of the materials must be reasonably close so that different operating temperatures do not result in thermal stresses that may cause die fracture or attachment failure. For smaller dice (<5 mm/side), various bonding materials have been used successfully. However, with larger dice (>10mm/side) becoming common, fractures of die adhesively bonded or soldered to lead frames or ceramic chip carriers are increasingly occurring. The fractures result from high stresses not only in the die, but also in the bonding material. The two areas of concern in die attach reliability are therefore die fracture and disbonding of the die.

Integrated circuit die bond materials and process selection are based upon the nature of the reliability issues involved. In a plastic package, die corrosion may become an overriding factor in materials selection. For high-power dissipation devices, heat dissipation and elimination of hot spots become key issues. In spite of such specialized considerations, the common concerns with die bond reliability are primarily twofold: disbonding failures (interfacial rupture) and die cracking (silicon fracture). These are now discussed.

Disbonding

Disbonding failures are caused by either a high degree of voiding under the die, or the interface between the solder/die or solder/substrate not being chemically bonded.

Void formation can also lead to interfacial rupture. One source of disbonding is the formation of low-strength, brittle phases at the Si-alloy interface. Adhesives with a large solvent content can lead to void formation during cure, and adhesives containing metal additions are subject to random metal migration leading to reduced thermal conductivity and strength. Figure 16.4 shows the effect of voiding on die bond integrity.

In general, for soft adhesives (Pb-based solders or organics), failure usually occurs in the die attachment material. Being softer, it acts as an absorber of strain between the die and the substrate. For hard adhesives (Au-based eutectics or solder glass), any high mismatch stress is directly transferred to the die, resulting in the possibility of die fracture. An examination of the failed interface

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Figure 16.4
The effect of voiding on die bond integrity: (a) large
void formation can lead to reduced thermal conductivity
and strength, resulting in disbonding; (b) small voids
provide adequate thermal conductivity and strength,
resulting in less stress on larger dies; (c) for larger
dies, the lack of voids for a high-strength adhesive
can result in excessive stress, producing die cracking.

becomes necessary to identify the source of the problem. Various causes of chip disbonding are

Solder and/or die backside oxidation

Nonbonding impurities on the solder surface

Formation of brittle intermediate phases

Substrate metallization adhesion failure

Solder fatigue or creep rupture

Insufficient amount of adhesive or solder

Extensive voiding under the die

Figures 16.5 through 16.7 depict scanning electron microscope (SEM) photos of die-bonding problems. Figures 16.5 and 16.6 show poor die attach conditions, both of which can result in voids between the die and the lead frame, resulting in hot spot formation and catastrophic device failure. Figure 16.5 shows a poor die attach where the die and preform are not aligned. Figure 16.6 shows two flaws: insufficient die attach solder, and a wire bond too close to the edge of the die. The

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Figure 16.5
SEM photo shows poor die attach. This can
result in poor thermal dissipation and possible
metal migration. (Photo courtesy of Hi-Rel Labs,
Inc.)

Figure 16.6
SEM photo showing both insufficient die attach solder and
wire too close to die edge.

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second condition could result in a short circuit between the wire and the die. Figure 16.7 shows complete die disbonding with all bonding wires still intact.

Die Cracking

Die cracking has emerged primarily as a large-die VLSI problem. This problem is more insidious compared to disbonding, since the crack propagation may be delayed until a sufficient number of thermal cycles have been experienced by the system. This represents a serious reliability hazard, since the power cycling of devices in field applications results in thermal cycling. Three key features of this failure mechanism are

1. The cracks usually show up after temperature excursions (thermal shocks, thermal cycling, etc.).

2. The crack typically emanates from the bottom of the silicon chip near the die edges and corners.

3. Two types of cracks are observed, vertical and horizontal.

The vertical cracks emanate due to the presence of voids in the die bond region, and the horizontal cracks from elevated interfacial stresses near the die

Figure 16.7
Lifted die; disbonding. (Photo courtesy of Hi-Rel Labs, Inc.)

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edges. The fracture mechanism for the semiconductor material in the die is characteristic of ceramic or glass materials, where the surface finish can affect the fracture strength. For eutectic bonded dice, cracking can originate from hot spots formed due to void formation and nonuniform stress in the bond. Die cracking in adhesive bonded die can also be due to void formation and gross mismatch in TCE values between adhesives and the ceramic substrate.

The die cracking problem can be analyzed based upon the basic fracture mechanics principles. Thus, silicon failure can be described as

microcrack (flaw) in Si + stress fracture

That is, since silicon is brittle, its fracture usually requires stress-assisted crack propagation initiated at a preexisting flaw, or microcrack, on the external silicon surfaces.

The microcracks in silicon arise as a natural consequence of damage to the silicon surface during wafer backside preparation and wafer sawing. In most applications, an ohmic contact from the die backside to the substrate is needed for proper operation of the device. This requires removal of the process contaminants from the backside as well as removal of any diodes formed inadvertently on the backside during the device fabrication process. To achieve this, the wafer backside has to be abraded or mechanically polished to remove about 2050 mm of silicon after the IC fabrication has been completed, resulting in mechanical damage of the die backside and introducing microcracks in silicon. Sandblasting the die backside to remove a layer of silicon is worse from the viewpoint of creating microcracks on the die backside and increasing the die cracking jeopardy than is mechanical grinding.

The occurrence of horizontal cracks in the silicon has been attributed to the high shear stresses near the die edges when bonded to a substrate with higher thermal expansion coefficient relative to silicon. The thermal stress of a bonded joint is highly dependent upon the bond line thickness for shear-constrained systems. Thus, the shear stresses in silicon are dependent upon the adhesive or solder bond thickness. For reliable VLSI die attachment, this means that the bond line thickness needs to be optimized for individual bond materials.

Fracture propagation vertically from the die backside requires a tensile stress field to be present in silicon near the microcracks. The primary stresses in silicon arise from the thermal expansion mismatch between the die and the substrate. If a perfect die bond is assumed (no voids or nonuniformities), basic stress analysis calculations show that the silicon backside goes into compression upon cooling from the die attachment temperature. Since the compressive strength of silicon is extremely high, vertical die cracking of perfectly bonded devices is most unlikely. In order to explain the vertical die cracking behavior observed, the secondary stresses due to the presence of voids in the die-bond region have to be accounted for.

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A good VLSI die attach process requires a void-free, uniform die bond. In the case of gold-silicon bonding, it is very common to have some regions of die left unbonded, especially at the edges, with the problem getting worse as the die size increases. To understand the reasons underlying this behavior and determine how to alleviate the problem, one must understand the metallurgical principles of soldering. Although the following discussion is based upon the Au-Si metallurgy, the principles involved can be applied to other solder die-bond metallurgies as well.

Eutectic Die Bonding

The Au-Si die bonding process is carried out at temperatures above the eutectic temperature (373°C). Typically, the reaction is initiated by using an Au-Si preform of composition close to the eutectic composition, although pure gold preforms are used in the industry as well. In the case of pure gold preforms, the silicon from the die backside reacts with gold at the die-bond temperatures to initiate the eutectic liquid formation. In either case, at the bonding temperature (typically >400°C), the liquid solder continues to consume the silicon from the die backside and gold from the substrate (if available) in order to achieve equilibrium. Since the silicon supply is virtually unlimited, silicon from the die backside dissolves into the solder until the liquid reaches a saturation composition. From the viewpoint of such a bonding process, it is imperative that the supply of silicon from the die backside be unimpeded in order to obtain a good diffusional bond.

Upon cooling, the bond consists of Au-Si hypereutectic phases (Si-rich eutectic microstructure) and represents a typical diffusional bond. No detectable solubility of gold and silicon into each other occurs below the eutectic temperature, but metastable gold silicides are known to exist. Thus, although the microstructure observed indicates some mechanical interlocking of gold and silicon phases, it is very likely that some degree of chemical bonding also exists.

Wire Bonding

Gold wire ball bonding is the most widely used wire bonding material/technique for plastic molded packages and for hybrid/MCM circuits. Aluminum alloyed with silicon or magnesium is also widely used in both hermetic (ceramic) and nonhermetic (plastic) packages. The predominant causes of wire bond failure are deformed/improperly formed bonds and aluminum corrosion at the die pad-wire bond interface.

The method used to bond the wires to the metallic bonding pad (usually aluminum) is very important when investigating the quality of the wire bonds, since the way in which the bonds are formed has a direct bearing on subsequent failures. The two most common methods of bonding are thermocompression and ultrasonic techniques. Thermocompression uses a combination of heat and force

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to cause the metal atoms of the wire to diffuse into the metallization on the silicon or substrate, thereby creating a bond. The depth and area of the diffusion determine the strength of the bond.

The high temperature used for thermocompression bonding, typically 250340°C, cannot be tolerated for aluminum wire bonding, due to a hard oxide that forms over the aluminum. For aluminum bonding, an ultrasonic technique is used, where the wire is placed in direct contact with the metallization and the bonding tool and wire are vibrated to scrub off the oxide and create sufficient heat to form a bond. Gold is commonly bonded by what is known as the thermosonic method, which combines the characteristics of thermocompression and ultrasonic bonding (heat, pressure, and vibrational energy) to create the bond. The advantage of this technique is that the temperature is relatively low, 125150°C.

Another important consideration when evaluating a wire bond is the shape of the bond formed, the two types being ball bonds and wedge bonds. In many instances the wire is bonded to the die with a ball bond and to the lead frame with a wedge bond, resulting in what is called a ball/wedge-wire bond, as shown in Fig. 16.8. It is important to note that the term wire bond is used to refer to the wire span and both bonds, whereas bond refers to the wire-metallization interface only.

Wire-bond failures, which are one of the largest causes of IC packaging failure, can be caused by some malfunction or error in the manufacturing process, or subsequent corrosion once the device has been put in the application. Manufacturing faults include poor bonding machine control and poor metalliza-

Figure 16.8
A ball/wedge wire bond is the most commonly used wire bonding system. The
neck and heel regions are typically the weakest parts of the wire bond.

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tion control, whereas significant intermetallic compound formation usually occurs later during device operation. Proper lead dress must be maintained. The wire loops must not be so high that they can either short to the package lid or snap during a vibration or acceleration usage condition (see Fig. 16.9), or sag so they short out to the die (Fig. 16.10), or be so taut that thermal expansion and constriction in usage can break the wire.

Poor bonding machine control can result in misplaced bonds and excessive force or temperature or ultrasonic energy, creating undue stress in the wire, a problem called overbonding. The opposite of this is underbonding, which results in poor bond adhesion. As device geometries shrink, there is a high risk of wire bond misplacement causing a short circuit between the bond pad and internal metal runs. In Fig. 16.11, the tail of the bond wire extends over the metal run. In this case, all bonds are offset, indicating that the automatic bonds either shifted or were not properly programmed. Results of induced stresses are deformed ball bonds (Fig. 16.12), metallurgical cracks in the heel of wedge bonds, and crystallographic damage to the silicon underneath the bonding pads. Although some of the defects in the wire may be annealed out, many cannot be and cause failures at a later time, such as wire breakage or bond failure. Crystallographic damage (commonly called cratering) is a common defect that can result in shorts or degradation of the electrical properties of the device.

Figure 16.9
High loops in wires can result in shorts through the metal lid.
(Photo courtesy of Hi-Rel Labs, Inc.)

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Figure 16.10
Sagging wires can easily short to the raw silicon
exposed in the scribe grid at the edge of the die.
(Photo courtesy of Hi-Rel Labs, Inc.)

Figure 16.11
Wire bond misplacement.

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Figure 16.12
SEM views of misplaced and deformed ball bonds (625×; 60°).

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The most delicate part of the assembly process is the wire-bonding operation. To minimize the human-induced defects during manual assembly operation, the wire-bonding operation has been automated. The high-speed, high-accuracy automatic wire bonders in use today have made possible the creation of consistent, uniform, and reliable wire bonds. However, automatic wire bonders are not without their problems. Improperly set up wire bonders make thousands of poor (but uniform) wire bonds in a very short period of time, as was mentioned in relation to Figs. 16.11 and 16.12 and is shown in Fig. 16.13. In Fig. 16.13, all three photographs show wire bond misplacement due to automatic wire bonder issues. In Fig. 16.13a also notice the close bond pad spacing; this is the trend with high-pin-count packages and requires high bond location tolerances. Figures 16.13b and 16.13c are the same photograph with (c) being an exploded view of (b). In Figs. 16.13b and 16.13c the misalignment is due to a slight shift of alignment in both x and y axes of the automatic bonder. Each bond is shifted the same degree; thus it is not a random problem.

Since many bonders have a visual check on the die and pad location, the problem appears to be a glitch in the computer program rather than a misalignment of the die. Note also that the bond lift appears to be excessive. This might have been due to a nondestructive pull test or a wire dress step. Thus, it is critical that proper attention be paid to bonder setup and calibration.

Then there is the issue of intermetallic growth, which has historically been a major concern to wire bond integrity. Gold and aluminum are known to interdiffuse readily to form intermetallic phases such as the so-called purple plague (AuAl₂). Imbalance in the atomic fluxes of Au and Al is balanced by a vacancy flux. The vacancies coalesce to form Kirkendall voids. These voids lead to a mechanical weakening of the bonds as measured by bond shear testing or traditional bond-pull testing. This effect can be seen in Fig. 16.14, which shows an Arrhenius plot of the time to 10% failure by a combination of cratering (fracture involving the silicon substrate) and fracture through the brittle intermetallic phase. The plot shows that a single mechanism with an activation energy of 1.26 eV is active over the entire range 160350°C.

Purple plague was a primary failure mechanism in the 1950s and 1960s but was essentially solved. However, with the advent of multiple-material vertical sandwich VLSI structures for contacts, wire bonding, and MCM attachment, purple plague periodically appears. The technical literature provides a thorough explanation of the materials issues and interfaces involved, as did an earlier chapter (Chapter 15).

Then there is the issue of wire bond pad contamination. Contaminants on bond pads can affect bond reliability. Silicon dust from inadequate wash after saw can accelerate gold-aluminum interdiffusion. Residual passivation from underetched bond pads can inhibit intimate contact of gold and aluminum.

For high-pin-count packages to have reasonable yield, some form of

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in-process quality monitoring is essential (see Chapter 4). Most bonders today are equipped with wire bond monitoring systems that employ a small current to perform continuity checks and to detect nonsticking conditions and broken wires. Catching these problems early enables timely shutdown of problematic machines.

In more advanced bonders, bond process analyzers are used to monitor real-time force and power at the point of bonding. Such machines automatically shut down if these parameters are outside the preprogrammed control window. Such closed-loop process monitoring will ensure uniformity and quality for each bond wire.

Polymer Materials

Epoxies and other polymers are used for die attachment (bonding), as seals in hermetic packages, and as the package encapsulation material itself (molded plastic package). However, there exist some problems with their use. First, these polymers may evolve a number of chemical agents that attack the various materials used in the construction of the package, including the bonding wire

Figure 16.13
Wire bond misplacement: (a) close bond pad spacing; (b)
misalignment due to shift of both x and y axes of automatic
bonders; (c) enlargement of (b).

Page 675

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and the IC die itself. Second, polymers used for package seals do not prevent moisture from reaching circuit metals. In fact, moisture tends to reside at the polymer-metal interface. Third, epoxies represent random mixtures, which are subject to incomplete cure. Fourth, polymers have glass transitions that are capable of introducing large mechanical stresses. And lastly, polymers introduce different thermal expansivitiesas much as a 20-fold difference between silicon and epoxy resin. The resulting thermal strain can lead to mechanical failure, strain-induced increases in permeability, and strain-induced chemical reactions. If not properly addressed, these problems could result in serious reliability degradation as well as catastrophic device failure.

The Physical Package

The packaged IC's reliability is directly related to its ability to function in its environment. Environmental concerns for the finished IC include corrosion, hermeticity, reaction thresholds, transport mechanisms, and moisture.

Often sharp notches or cracks develop (due to a variety of reasons such as mishandling, high pneumatic pressure in the autohandlers cracking the packages, improper package assembly techniques and the like) in the finished product.

Figure 16.14
Arrhenius plot of time to 10% bond pull failure for gold bonds to aluminum.
(Reprinted by permission of Intel Corporation, copyright Intel Corp., 1991.)

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These serve as mechanical stress concentrators, producing fatigue cracks or fast fractures. Then chemical agents, such as moisture, migrate to these stress concentrators, causing either rapid local corrosion, corrosion of a slower nature, environmental fatigue, or stress corrosion cracking. Both hermetically sealed and nonhermetic (plastic) packages are subject to these stress concentrators. For hermetic packaged ICs, some of the typical faults that result in leaks in the package include cracks in the glass insulators, surface contaminants at the seals resulting in poor wetting and adhesion, contaminants in metal platings at the seals, the formation of intermetallic compounds, and intermetallic segregation at the grain boundaries.

Plastic packages provide a lower cost encapsulation alternative to hermetic packages. However, their ability to protect the die from hostile and foreign substances has been a point of continuing controversy. Originally the commercial plastics used for the encapsulation contained a high proportion of impurities, and the devices acquired a reputation of poor quality and reliability. However, improved process and quality control have improved the reliability of plastic-en-capsulated devices to an acceptable level. The following two sections deal specifically with some of the reliability issues peculiar to each packaging category: hermetic and nonhermetic (molded plastic) packages.

Hermetic Package Reliability*

Several representative hermetic packages are presented as illustrative examples of how their construction affects reliability. These are the CERDIP, the glass-body Kovar, and the ceramic packages.

The CERDIP

The CERDIP package is one of the most widely used IC packages. In this package (Fig. 16.15), the chip and lead-frame assembly is sandwiched between two alumina (Al₂O₃) ceramic plates held together by a glass sealant. The coefficient of thermal expansion of the glass must be closely matched to that of the ceramic to prevent thermal stress cracking. The glass sealant provides the hermetic seal.

In the CERDIP package the silicon dice is either epoxy or eutectic die attached to a metallization pad in the bottom cavity. Subsequently, either gold or aluminum wires are bonded between the die and the metal leads of the package. The lid is then sealed by passing the package through a furnace operation, which melts and sandwiches the base and lid together, hermetically sealing the package. After the package is sealed, the leads have a finished coating applied (e.g., tin, tin/lead, etc.), thus completing the physical assembly.

*Used with permission from Ref. 3.

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Figure 16.15
The structure of the CERDIP package [3].

The ceramic itself is impervious to almost all gaseous contaminants and moisture, provided it has been properly sintered. The ceramic also provides good electrical insulation and high thermal conductivity. The package has proven to be very strong, although brittle and especially susceptible to torsional stresses, and also thermal shock such as provided by tin-dipping of the electrical leads, for example. This can lead to cracking of the frit seal and the consequent loss of hermeticity.

The most outstanding characteristic in the assembly of the CERDIP package, a characteristic that differs from all others, is that the final lid seal is also the sealing member to the leads which exit the package. In essence, the leads are final sealed into the package by the same process which seals the lid. Consequently, the sealing cycle must be carefully controlled.

The glasses that may be used for this purpose must all be at the comparatively low working range of about 430°C. In order to achieve this lower working point, the glasses have a very high lead oxide content. This is true in both nucleating as well as vitreous glasses. When the package has been sealed and the leads are being prepared for the finish coating, it is necessary to remove the oxide from the leads. This oxide was previously developed for the purpose of making a good glass-to-metal seal. The oxide is removed by means of a commercially available chemical-reducing agent, which has a stripping action. These stripper formulations do an excellent job of reducing the lead oxide but also have a reducing effect on the lead oxide on the surface of the glass. In fact, it is not only possible to reduce the surface resistivity between leads, but possible to have a dead short. Nucleating and vitreous glass are two high-lead (lead oxide) glasses.

Nucleating glasses offer much higher mechanical strength and are therefore more desirable in that regard than the vitreous type. However, nucleating glasses have chemically combined water content, which is given off during the lid

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sealing operation. The moisture continues to be given off after the closure has been made, while the glass is still within the working molten range. Consequently, undesirable moisture is trapped within the sealed package. The formation of the final seal presents yet one other major considerationthe use of oven or hot cap sealing.

All glasses, regardless of the method used to attain the fluid stage, will develop and retain stresses upon cooling. The intensity, polarity (compressive or tensile), and distribution depend upon the cooling (annealing) cycle, the material characteristics, and the physical design of the bodies involved. Since the last two conditions are dictated by the needs of the IC's functional electrical parameters, the cooling cycle is the variable to be addressed. The use of an oven process is more desirable than hot cap because all parts of the package tend to be heated with less of a thermal difference between parts. Since stress is greatly dependent upon that temperature difference, the result is less strain. However, that very characteristic of less thermal difference means that the silicon die and its wire bonds are also exposed to an elevated temperature; this is an undesirable feature. The hot cap method introduces the heat directly down through the top plate, into the glass and partially into the bottom plate, maintaining a lower ambient temperature at the die site. The die and wire bonds do not see the previously mentioned higher temperature. The result is that greater stresses are induced, higher strain exists, and the possibility of lids falling off is present.

The Hard Glass Package

The hard glass package consists of two components: borosilicate glass and Kovar. As shown in Fig. 16.16, the typical hard glass package is composed

Figure 16.16
Loaded glass/hard glass package [3].

Page 680

of a glass body through which Kovar leads penetrate. The base may be Kovar, alumina, or beryllia. The glass itself may be loaded with fine alumina powder, or remain plain. The seal ring is Kovar and presents a solderable surface so that the lid can be sealed with a typical solder, such as gold-tin. Since all glass seals on this package are formed before the installation of the silicon die, they can be formed at as high a temperature as necessary, and this is in the range of 10501100°C. The final lid-sealing temperature, using gold-tin as the solder, is usually carried out at about 320°C, well below the critical temperature for silicon die processing.

Again after the package is sealed, the Kovar leads must have a finish coating, lead plating (e.g., gold or tin is applied). While the Kovar metal provides a superior glass-to-metal seal as compared to the Alloy 42 lead material of the CERDIP, it is much more susceptible to corrosion than the stainless-steel-like material Alloy 42.

In order to have an acceptable seal around the leads, a meniscus must be formed. Consequently, during handling the meniscus may fracture, exposing bare unplated Kovar and resulting in subsequent corrosion failure. In addition, the presence of residual strain in the glass can cause ultimate failures due to thermal shock. Whereas CERDIP's possible failure mechanisms included chemical attack because of the high oxide content in the glass, this is not a significant factor in the glass package. The primary failure mechanisms are due to mechanical and thermal stress. The fracturing of the meniscus may result in a leaking seal or may result in failure due to corrosion. Both of those failure modes may be catastrophic in nature.

The Ceramic Package

The ceramic package is primarily an alumina composition of approximately 9295% Al₂O₃ and has a metallization system of either molybdenum or tungsten; the common feature of the ceramic and metallization is that they are fired at a temperature of approximately 15501600°C. Any normal subsequent processing does not affect the package in any way. This package family is probably the most stable package type available today.

The ceramic package has many variations, such as side braze (DIP), bottom braze, top braze, chip carrier (leaded and leadless), and pin grid array. All are based upon the same materials, processes, and design principles. Figures 16.17a and b show cross sections of the side-braze and chip-carrier ceramic packages, respectively, for comparative purposes. The structure of these ceramic multilayer packages is based upon a cofired alumina tape process. When fired at a high temperature of 15501600°C, the alumina goes through a shrinkage to final size while the metallization assumes the pure metal form. The multilayers become a single homogeneous monolithic body with buried conductors as an integral part of the body. Once fired, the packages go through a lead brazing operation and

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Figure 16.17
Ceramic package cross sections: (a) side-braze package; (b) chip
carrier package [3].

final platings. As can be seen from Fig. 16.17, the leads on the ceramic packages do not go through any seals; consequently, any flexing or bending of leads cannot affect the integrity of the seals.

In laminated ceramic packages, the silicon die is brazed to the cavity of a ceramic package at about 360°C using a goldsilicon eutectic. When cooled to room temperature the TCE mismatch causes the bottom of the silicon die to be in compression, while the top is in tension. If there are voids in the gold-silicon eutectic brazing material, there is a tendency for stresses in the silicon near the silicon-eutectic interface to become less compressive near the voids. If the void is near the center of the die, the stresses remain comprehensive but less so locally. (See the dotted line in Fig. 16.18.)

In Fig. 16.18, positive stresses are tensile. If the void is near the edge of

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Figure 16.18
Longitudinal stress as a function of distance from chip edge. (Reprinted
by permission of Intel Corporation, copyright Intel Corp., 1991.)

the die, however, local regions of tensile stress can occur. This is shown as the solid line in Fig. 16.18.

Tensile stress is a necessary condition for the initiation and propagation of a crack on the back of the wafer. When tensile stress is present, the nature of the finish of the back of the die determines whether a crack is initiated. Once a crack has started, it will propagate to the front of the die, where it will cause functional failure. The condition of the back of the die (roughness, degree of oxidation, etc.), the temperature, and ambient gas are controlled to optimize the wetting characteristics of the gold eutectic braze.

A similar mechanism in which cracks nucleate from die-edge damage due to partial saw and break die separation has been observed in silver-filled glass-attached pressed ceramic packages.

Ceramic Package Cracking

During solder dipping, large ceramic packages (both DIP and SMT) cracked when the leads and bottom of the ceramic packages were suddenly immersed in the molten solder (>200°C). The cracking was not due to the different TCE values of the materials, but rather to the lack of thermal conduction. The solution was to preheat the parts prior to solder dipping.

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Loose Particles

Certain hermetic packages, both by their construction (welded construction metal TO-3 packages, for example) and by the wire bond-die attach process used are susceptible to loose particles being entrapped in the cavity after sealing. If these particles are conductive in nature, they can cause electrical shorts if they bridge two conductors (wire and die) when subjected to in-use mechanical shock or vibration conditions and result in equipment failure. A pertinent example of the effect of loose particles was the loss of a $50 million Titan III launch vehicle. Loose conductive particles caused failure of the guidance system during the vibration incurred at launch. The appearance of particles is dependent on manufacturing (package assembly) methods, materials used, cleanliness, and control.

Where do the particles come from? Organic materials can change from hard to soft under varying thermal conditions. Temperature changes can cause brittle materials to fracture and metallic interfaces to open and close, breaking material free in the form of particles. Weld flash of certain package types (TO-3) during final seal creates particles.

Although solder balls are one of the most common forms of conductive particles, there are many other sources of materials that can create the typical random shorting-type of vibration test failure or field failure. Figure 16.19 shows a typical field failure. A particle of Kovar from a weld flash was attracted by the electrical field between the base bond wire and the metallized collector guard ring of a discrete NPN transistor. The result was a collector-base short. In this example there was enough current to cause partial melting of the aluminum metallization.

The composition of particleswhich may vary in shape from round balls to sharp-edged sliversis affected by different processes in different ways. For instance, aluminum under moist conditions may develop a film of aluminum hydroxidea greasy material that can cause aluminum particles to adhere to most surfaces. Gold, on the other hand, can cold weld to other materials when physically thrown at the case sides (e.g., by vibration). Motion from many different sources can cause a particle to become lodged in V-shaped slots, only to reappear later when freed by thermal expansion of the slot.

Backfill gas used in final sealing processes can also affect particle mobility. Moisture may act as an adhesive. Oxygen provides lubrication, increasing particle mobility. Although IC suppliers attempt to make the final sealing process consistent for each batch, small variations in oxygen and moisture levels will occur.

In some instances an adhesive (getter) is placed inside the package lid to trap these particles.

Plastic Package Reliability

The molded plastic package is the most widely used package today and for the foreseeable future. The encapsulation is achieved by molding the lead-frame

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Figure 16.19
Photograph of a conductive particle.

containing the die entirely in plastic, primarily epoxy novolac. The plastic must be cured and baked in order to reduce the moisture content.

Stress between a silicon chip and plastic package is generated during the encapsulation process and is due to chemical shrinkage (linking of polymer chains) and to differences in expansion coefficients. The latter involves leadframe material, silicon, and the plastic package material.

In a plastic packaged IC, stress can cause

A parametric shift of device functions

Cracks in the polysilicon passivation or other layers of the chip, especially if such layers are directly underneath large aluminum lines

Deformation or fracture of the chip's metal

Cracking of the plastic package

Cracking of the IC die

Damaging the wire bonds

The shearing forces exerted by the package on the die can damage thin-film structures, particularly near the corners of dice, for example, those encapsulated in PLCC packages.

VLSI devices in plastic packages can experience metal shift during either

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temperature excursions or on-off power cycling of the device. Shear forces tend to displace the wide aluminum bus inward toward the center of the die, producing visible cracks in the passivation over the aluminum. Occasionally the normal force on the die surface can be concentrated at a point by a large filler particle and crack the passivation. This can be controlled by limiting the filler particle size to less than 5 mm or applying a die coat. Since the molding compound encapsulates the die and all the wires, it transmits forces to the die surface and wires that may eventually cause failure during use, including power cycling and exposure to thermal variations. As such it is important to understand both the mechanism of crack propagation and the way in which the die and the wires respond to the forces transmitted to them by the package.

Figure 16.20 shows the forces acting on the surface of a die in a plastic package with an ambient temperature less than the neutral stress temperature of the package (about 170°C). There are two components: a shear force directed toward the die center and vanishing at the die center, and a comprehensive normal force roughly constant everywhere on the die surface and compressive. If a crack starts to propagate from the top edge of the die, it redistributes forces acting on the die surface. The crack will increase the shear stress acting near the edge of the die and change the normal stress from compressive to tensile. The situation is different

Figure 16.20
Shear and normal forces acting on the die surface in a
plastic package. (Reprinted by permission of Intel
Corporation, copyright Intel Corp., 1991.)

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during a solder temperature shock because the shear forces are outwardly directed along the die radius. In any case, these forces drive important failure mechanisms.

The molding compounds used for plastic packages are thermosetting, meaning they flow into the mold cavity with a low viscosity and then begin to set with a complicated yet well-defined solidification sequence. These internal polymerization gradients cause built-in stresses on the die and the wires, which depend on where the wires are relative to the inlet gate for the individual package mold cavity. It has been observed that the largest incidence of sheared ball bonds in temperature cycling experiments occurs opposite the inlet gate.

Wire bond damage is another issue that bears some discussion. Figure 16.21 shows an enlarged view of a wire bond near the top right edge of the die shown in Fig. 16.20. The crack, which has been propagated by temperature cycling, has intersected a wire and sheared it. The normal and shear stresses on the ball bond are enhanced by delamination between the molding compound and the die surface. The bonds may or may not shear. If the bond does not shear, a separation between the molding compound and the bond occurs.

Also, if the bond does not shear, the displacement of the molding compound normal to the die can place a severe stress on the wire at the neck of the ball. This is because the wire tends to move with the molding compound whereas the ball bond remains fixed relative to the chip (if it does not shear). The wire at the neck of the ball is particularly susceptible to deformation because it has been annealed during ball formation.

Figure 16.21
Wire and wire bond damage. (Reprinted by permission of
Intel Corporation, copyright Intel Corp., 1991.)

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If the bonding process introduces substrate damage, such as cracks in the silicon under a bond pad, then shear forces can propagate the crack. The bond then breaks loose with a piece of the silicon substrate attached. This type of failure is termed cratering. Bonding causes more damage for softer glass films under bond pads (such as high-phosphorus glass) and when silicon precipitates nucleate on the Al-glass interface from Al-Si metallization on the bond pad. A thin film of titanium under the aluminum metallization effectively provides resistance to cratering.

With the trend of integration continuing upward, with larger size dice and even finer patterns, thermal mismatch will continue to be a leading quality issue. These errors occur as a result of the intimate interaction of the die surface and the molding compound due to mismatches in TCE between materials. Damage sites include

Delamination

Chip cracking

Cracks in the package

Cleavage of wire bonding

Passivation cracks

Deformation and sliding of the metallization

Polysilicon cracks

Cracking generally occurs near the corners of the chip (die). Resulting failure modes include functional failures, shorts, leakage, or opens.

At Intel, four main factorsincluding layout style, materials, die thickness, and passivation typewere investigated as to their impact on thin-film cracking. Of these, the layout style had the most influence on thin-film cracking during thermal cycling. Thinner die and planarized passivation provided moderate improvements. Characterization of packaging materials was incomplete and not conclusive, and die size influences were not found to be significant, probably since results were dominated by other factors.

At Signetics (now Philips Semiconductor), investigation identified the following contributors to thin-film cracking:

1. Die topography

(a) Number of metal and other interconnecting layers

(b) Interconnection metal hardness

(c) Strength of interlayer dielectrics

(d) Strength of protecting passivation layers

(e) Vertical height of overall topography

2. Die layout

(a) Relative proximity of metal interconnects to corners and edges of die

(b) Total area of interconnect freeboard around die periphery (including scribe line)

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(c) Number and angle of crossover interconnects at or near die corners

(d) Relative distance to bonding pads from die corners

3. Die size: Package stress increases exponentially from the package center along a radius line to the die corner. The longer the diagonal, the greater the stress.

4. Plastic encapsulating material/assembly processes

(a) Residual stress of the plastic (in compression, as a function of ambient temperature)

(b) Adhesion of the plastic material to die and lead frame

Because the damage to the die is fatigue related, the relative movement of the molding compound to the die surface is critical to the onset of damage, relative to any given die technology. The level of delamination of the plastic to the die surface provides a clear correlation to the onset of fatigue-related damage.

The Signetics study also suggests that the greatest improvement to reduce thin-film cracking can be gained by locating critical circuitry away from the die corners and filling the corner of the die with sacrificial anchoring structures. Modest improvements can be gained by thinning the die and using planarized passivation.

The use of a conformal junction coating (applied on top of a chip) and selected die-bonding materials provides stress relief. These provide a buffer between a package and a lead frame. In addition, however, IC suppliers need better tailoring of molding compounds for stress relief. The chemistry of such molding compounds is addressed both through polymers and fillers. Modifying polymers usually involves introducing more flexible cross-linking members or hardener modifications. On the other hand, stress relief at the interface between a polymer and a filler is addressed through more flexible suface treating agents for the fillers.

Thermal dissipation characteristics are inversely tied to stress relief characteristics. While the conventional approaches to stress relief in molding compounds have involved a compromise of heat dissipation characteristics, a function of the fillers used, the suppliers and users of molding compounds are now well aware that such a compromise is no longer satisfactory for state-of-the-art ICs. Judicious design and selection of lead frames does help in thermal management. But, for example, high-performance bipolar ICs have strained the capabilities of conventional heat dissipation with heat sinks.

Where thermal management of circuit-generated heat is a key issue, particularly with large dice, low stress in combination with thermal dissipation has to be a characteristic of molding compounds. Better materials, such as high-conductivity, low-expansion fillers and resin systems that minimize the contribution of the organic phase to lowered conductivity, are being developed to address this issue.

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In the past, epoxy Novolac resins with fused silica fillers provided stable IC plastic packages. But for VLSI circuits, such as high-density memories and large microprocessors, the stress induced by the large sizes of the chip and the package is a major factor that must be addressed to achieve successful packaging.

Moisture

Moisture has been a major concern with the use of plastic packages. The ingress of moisture in a plastic package can cause two primary types of failure: corrosion and package cracking due to popcorning.

Corrosion

The reliability of ICs in molded plastic packages can be affected by permeation of moisture and contaminants through the package, or by reaction with materials that are part of the package itself, leading to corrosion of the chip and bonding wires.

Four conditions must be present for moisture-related failure mechanisms in plastic packages: There must be a path, contamination, moisture, and voltage. These are all present in plastic packages and must thus be controlled to minimize the failure rate. The issue of whether or not there is a path to the die is more important for impurities than for moisture, because the plastic package is relatively transparent to moisture, especially for accelerated temperature/humidity test conditions. There is always a path to the die for moisture. The path to the die for impurities may be along interfaces inherent to the construction of the package or along unintentionally introduced cracks. Figure 16.22 shows that interfaces between lead frame and epoxy and between wire and epoxy provide paths to the

Figure 16.22
Mechanisms of moisture-related package problems.
(Reprinted by permission of Intel Corporation, copyright
Intel Corp., 1991.)

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die. Impurities diffuse along the interfaces between the epoxy and the lead frame. Paths to the die can also be provided by gaps or cracks, which can occur

During plastic material setup and curing (Fig. 16.23)

During mold ejection

During deflash, trim, and form due to dull or misaligned tooling

During solder dip or vapor-phase reflow during board insertion

Due to temperature cycle or thermal shock

Once the moisture and/or impurities have reached the die, the path to active circuitry is provided by

Pinholes in passivation

Passivation cracks due to thermomechanical stressing of the package (thin-film cracking)

Cracks at poor step coverage by passivation

Contaminants may reach these die by one of the paths shown (Fig. 16.22) or they may be introduced with the die or epoxy material. When accelerated by

Figure 16.23
Gap between plastic body and lead frame, caused by improper adhesion of plastic
material to the frame, can allow in moisture and contaminants, resulting in
dendrite growth and corrosion.

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temperature, humidity, and bias, two main types of failure may occur: aluminum metallization corrosion, or a more subtle circuit malfunction.

Figure 16.24 shows a photograph of one of the most common manufacturing caused failureschlorine contamination and the resultant corrosion. This is usually induced when the package is cleaned in a trichloroethane solvent.

The sources of corrosion that result in failure of plastic-encapsulated ICs are summarized in Table 16.5. It is worthwhile to note that some of these are sources of corrosion in hermetic packages as well.

Atmospheric pollutants and moisture have been the major subject of reliability studies, such as salt spray and pressure cooker tests, for many years. Actual ambient conditions can vary, from the humid jungles of Panama to urban industrial environments with high sulfur dioxide and chemical contents to relatively benign telephone central switching offices or computer installations.

Moisture resistance of molding compounds is probably the area where the most dramatic improvements have been made in the past few years. Before the commercialization of semiconductor-grade Novolac-based encapsulants, unacceptable moisture resistance performance kept plastic-packaged ICs out of demanding applications.

Ionic contaminants contained within the molding material, a serious

Figure 16.24
Chlorine contamination and resultant corrosion of die bond pad.

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Table 16.5 Sources of Corrosion in Plastic Packages

Atmospheric pollutants and moisture

Solder fluxes

Plastic encapsulation material

Ionic impurities

Halogens from thermal degradation

Other corrosive elements

Incomplete curing

Impurities in die-attach epoxies

problem in earlier epoxies, have been greatly reduced with the introduction of epoxy Novolac. However, there can still be an order of magnitude difference between various epoxy Novolacs in time to failure of plastic-encapsulated ICs under bias at 85°C, 85% relative humidity.

The addition of brominated flame retardants to epoxy Novolac have raised the possibility of the release of corrosive elements by thermal degradation; methyl bromide, which is reactive with aluminum, is a major thermal degradation product of a flame-retarded compound. Studies by Intel have shown that for chip temperatures of 160°C and above there is a substantial acceleration (20-fold) of failure rates for flame-retardant relative to the non-flame-retardant epoxy. However, for chip temperatures of 140°C and below, bromine-containing flame-retardant decomposition has negligible effects on bond degradation.

However, TTL devices encapsulated with a flame-retarded Novolac, as compared with an earlier Novolac, demonstrated improved reliability under moisture stress.

Thermal degradation products of epoxy resins, other than those from flame retardants, must also be considered as a possible source of contamination. For example, ethyl chloride is reactive with aluminum.

Corrosive agents may also be formed by such reactions as hydrolysis of ester groups present in cured resin, or chain scission by reaction with corrosive gases from the atmosphere. Furthermore, incomplete curing can lead to the formation of corrosive elements, as in the case of organic acids formed from acid anhydride hardeners. Many molding systems, in fact, are formulated with an excess of either resin or hardener.

Plastic-encapsulated ICs include other materials besides the molding compound itself that are sources for impurities. For example, silver-filled die-attach epoxies contain extractable chlorides that corrode bonding wires and chip-bonding pads in the presence of moisture. Furthermore, die-attach epoxy and polyimide die coatings are sources of moisture right at the chip.

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The various corrosive elements identified may enter the plastic package along the leads, through cracks in the package, or directly through the bulk package material. Furthermore, moisture carries with it ionic impurities, such as sodium, chlorine, and bromine picked up from the plastic and its filler, that corrode the IC metallization. Diffusion along the leads is dependent upon the initial bond strength of the plastic to the leads. Silicones exhibit higher rates of diffusion than epoxies due to the absence of chemical bonding in the former. Furthermore, mold-release agents incorporated in molding compounds aggregate at the lead surface, resulting in weaker package bonds. Omission of an internal mold-release agent improves adhesion of epoxy Novolac. However, it was found that moisture diffusion was actually slower with the mold-release agent, due to its hydrophobic nature. Of greater importance, the higher glass transition temperature obtained with epoxy Novolac has decreased the thermal mismatch with the leads so that, even under temperature cycling, diffusion along the leads is no longer the principal cause of moisture ingress.

Additionally, all plastic materials absorb, and are permeable to, moisture. Permeability is affected by such parameters as molding temperature, cure time, and filler content. It should be pointed out, however, that permeation rate is not necessarily an indicator of device failure rate.

The need for better moisture resistance in plastic packages has been driven, in part, by trends to lightweight, thinner package designs. Factors in achieving improved moisture performance include purity and the extent and nature of the epoxy cure reaction (such as catalyst selection).

Also affecting plastic device reliability are changes in properties of the plastic caused by environmental factors (such as loss of salt spray protection at elevated temperatures) and corrosive pollutants found in industrial environments.

Aluminum metallization corrosion is well understood and can occur in two ways:

Moisture combines with phosphorus from phosphosilicate glass (PSG) to form phosphoric acid. This can cause corrosion with or without bias. Under bias, cathodic corrosion of aluminum occurs. PSG can be exposed to moisture by misaligned passivation openings or cracked passivation.

Ionic chlorine and bromine are efficient catalysts for anodic corrosion of aluminum. Typical sources of chlorine are chemical deflash, old-generation molding compound, oxide stripper (for cleaning leads after burn-in), and handling. Bromine is used as a flame retardant and mold release agent.

Metallization corrosion is no longer an important failure mechanism in plastic packages. The phosphorus content of glass exposed to moisture is carefully controlled and chlorine and other ionics have been greatly reduced in new-generation molding compounds and processing.

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Newer epoxies (Novolac refinements) are being made as pure and ion-free as possible and with temperature coefficients of expansion that closely match those of the IC die, bonding wire, and lead frame, resulting in fewer corrosion failures and less thermal and mechanical stress. Various die coatings in addition to the passivation layer are used to seal the chip and wire bonds from the aforementioned corrosion and mechanical and thermal stress mechanisms.

Monitors and qualification procedures incorporating steam and 85/85 stressing are put in place to catch any problems before customer ship.

Now that aluminum metallization corrosion has been controlled, plastic- encapsulated devices last much longer in moisture stress, and fail by subtle circuit malfunctions such as ionic migration through passivation defects leading to discharge of an internal circuit node. For example, in the 1970s typical mean times to failure were 500 to 1000 hr in biased 85/85 with pad corrosion. Today (1994), mean times to failure of greater than 5000 hr in this stress are common and transistor degradation is the usual failure mechanism. However, corrosion of the exposed aluminum bond pads is still a major concern with the use of plastic molded packages.

Package Cracking Due to Popcorning

Large plastic surface-mount technology (SMT) IC packages have cracked or exploded during IR soldering on the PC board. During handling, transportation, and storage, the plastic package material absorbs and diffuses moisture within. The moisture at the interface between the chip bonding pad and plastic is vaporized in cavitiesparticularly the small gap under the lead-frame paddleby heating (above solder melting temperature) during reflow soldering. The vapor pressure deforms the plastic below the chip pad, stressing the plastic and cracking the package. Figure 16.25 illustrates this popcorn mechanism.

Figures 16.26 and 16.27 show two different ways in which popcorning can take place in a quad flat package (QFP), and Fig. 16.28 shows the crack mechanism development in an SOJ package. The main factors influencing the propensity to crack have been found to be

Peak temperature reached during soldering

Moisture (percentage weight gain) content of molding compound

Dimensions of die paddle

Thickness of molding compound under paddle

Adhesion of molding compound to die and/or lead frame

Integrated circuit manufacturers of these crack-sensitive parts bake the ICs in forced-air convection ovens (anywhere between 35 and 125°C depending on the manufacturer) for about 24 hr. The ICs are then immediately packed in heat-sealed moisture-barrier bags with desiccant. Units should be used within 48 hr of opening the bag or rebaked. The units should be rebaked only once, because

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Figure 16.25
Early analysis of mechanisms of SMT package cracking.

each bake cycle causes the growth of Cu₆Sn₅ at the interface between the solder on the lead frames and the copper lead frame. Excessive growth of this intermetallic phase can lead to poor solder wetting during the solder reflow cycle. See Ref. 5 for details of protection methods for moisture-sensitive ICs.

External Package Moisture-Induced Failure Mechanisms

Moisture can accelerate galvanic and metal migration failure mechanisms, which affect the external lead finish of packages. For example, incompatibility between the package lead finish and the socket (if used) can lead to a substantial difference in electrochemical potential and consequent galvanic action. It is therefore recommended that gold-finished sockets be used with gold-finished hermetic

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Figure 16.26
How a QFP crack can develop.

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Figure 16.27
Another way a QFP crack can develop.

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Figure 16.28
SOJ crack development.

packages, and tin-finished sockets should be used with devices that have tin or solder-lead finishes.

A similar galvanic failure mechanism can occur on gold-finished hermetic packages independent of the socket. If a pinhole or scratch in the gold exposes ferrous base metal or silver/copper eutectic brazing material, a strong electro-chemical corrosion cell can be activated. A passive nickel barrier layer beneath the gold eliminates the possibility of this failure happening.

Tin, solder, and especially silver are capable of migrating under the influence of humidity and electric fields. Side-braze packages are plated with nickel and gold to prevent exposed silver from the silver/copper eutectic brazing material. On CERDIP packages, an out-of-control electroplating process can cause lead shorting due to tin migration. Tin migration is also a possibility in saturated steam exposure. These problems are infrequently observed. However,

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with the trend toward ever finer lead pitches, the potential for this failure mechanism will increase.

Human Causes of Error

During IC fabrication and assembly there are many in-process points of human interaction. Each of these presents a real possibility of introducing errors, mistakes, or contamination into the finished product at that point of handling. Some of the causes of human-induced manufacturing defects are

Human-derived contamination

Spittle

Perspiration

Cosmetics

Operator error

Fatigue

Boredom

Carelessness

Distraction

Attitude

Improper training or lack of training

High personnel turnover

Handling the ICs

To eliminate these human-induced manufacturing defects and increase throughput, wafer fabrication and assembly lines are being automated. However, not all operations lend themselves to automation at the present time, due to both technological and cost constraints. Take the case of visual inspection during assembly. Electrical testing of ICs is not sufficient to ensure that a device will remain good. The constituent elements of an IC can be plagued with reliability problems that must be detected visually; while a device may seem to function properly electrically, flaws that must be detected visually affect the long-term reliability of that device. Thus, there is a need for some form of optical-microscopy-aided visual inspection near the end of the IC manufacturing process (during assembly and packaging). This visual inspection cannot be automated. Furthermore, visual inspection presents a dilemma because as device geometries continue to shrink there is no effective and efficient means of performing the required visual inspections. (The optics may have to be replaced with other means of detection such as electron beam, sound, or ultraviolet, for example.)

This leads to operator fatigue. Operator fatigue, which causes a high personnel turnover rate, is the primary factor in assembly inspection inconsis-

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Figure 16.29
Rupture of oxide to contact area (arrow) due to ESD. (Photo courtesy of SEAL.)

tency. Furthermore, the human element of assembly inspection (and electrical test, marking, and packaging) creates a handling problemmechanical damage or electrostatic discharge damage. In fact, the more a given IC is handled, the greater the probability that it will incur some form of damage.

Thus, as IC complexity increases, inspector training time, fatigue, and personnel turnover will increase for manual inspection. What is required, in addition to upgrading inspection to an automation-assisted manual task, is a change of emphasis. Process control should be emphasized, rather than after- the-fact inspection.

A human-derived failure mechanism that is both increasing in frequency of occurrence and just only beginning to be understood is electrostatic discharge (ESD). This failure mechanism was addressed in some depth in Chapters 11 and 15. A classical ESD failure is shown in Fig. 16.29 in which there is oxide rupture to a contact area (as shown by the arrow). The rupture appears to come from the diffusion area.

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Summary

A listing of the issues discussed in this chapter is presented in Table 16.6.

Table 16.6 VLSI Package-Related Failure Mechanisms Summary

Die cracking

Due to presence of voids in die bond area and gross TCE material mismatch

Fatigue-related damage due to movement of molding compound

Increased moisture problems, especially in large plastic SMT devices

Use of materials with wide range of TCE values causes internal stress during assembly, test, and use, leading to material separation and package cracking (popcorning)

Corrosion

Poor glass-metal seals in hermetic packages

Application problems caused by solder dipping and IR PCB soldering

Die cracking

Cracking glass seals

Plastic package rupture

Thermally induced stress failures due to inability of the package to remove heat

Electrical performance degradation due to high inductance, capacitance, and resistance signal paths; inappropriate line termination and thermal conductivity (self-heating)

Switching speed of CMOS ICs degrades with temperature

Leakage current of bipolar p-n junctions increases with temperaturethus, system operating speed is adversely affected by limitations on removal of heat

Particles

Bond failures

Kirkendall voiding due to intermetallic compound formation

Contamination (Na, Br, Cl)

Thermomechanical stresses from material mismatches

Short circuit caused by bond misplacement due to higher pin counts, close line-to-line and line-bonding pad spacing

Improperly formed bonds (i.e., excessive pressure)

Stresses in plastic package causing molding compound movement

Die attach failureslifted bonds and hot spots

Caused by difficulty of assuring a uniform void-free-bond on large die

Handling large SMT packagespotential mechanical damage such as cracked ceramic packages and bent/broken leads (QFPs)

Thin-film metallization and passivation layer shift/cracking

TCE Mismatches between die surface and molding compound

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References

1. A. Shumka and R. R. Piety, Migrated-gold resistive shorts in microcircuits, Proceedings of the 13th International Reliability Physics Conference, Las Vegas, Nevada, 1975.

2. F. J. Grunthaner et al., Migrating gold resistive shortsChemical aspects of a failure mechanism, Proceedings of the 13th International Reliability Physics Conference, Las Vegas, Nevada, 1975.

3. D. Nixen, Package reliability as affected by materials and processes, Semiconductor Int. April (1982).

4. C. A. Nicolaou, Plastic package failure modes, Surface Mount Technol. November (1993).

5. Procedures for characterizing and handling of moisture/reflow sensitive ICs, IPC-SM-786A.

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17
Reliability Improvement

Overview

The trend in IC manufacturing has been toward improved quality due to a better understanding and control of process parameters and device properties, a lower incidence of localized material defects, and a greater attention to detail based on data gathered to drive continuous improvement. The objective of IC suppliers is to design in reliability, although some screening is necessary to uncover certain manufacturing faults to continuously improve the manufacturing process.

Additionally, there are several major limitations in the present IC manufacturing quality system that need to be addressed in order to improve the outgoing quality of the finished product. These are

Inadequate basic understanding of some process steps, including both fabrication equipment and process particulate generation

Failure to fully automate the process control procedures

A lack of electrical test systems to measure IC parameters accurately and repeatably at defect levels of 110 parts per million

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A lack of correlation between final electrical test measurements and critical process parameters

Several tables are presented to crystallize the material presented in Chapters 15 and 16 in several different ways. Table 17.1 is a comprehensive list of primary IC manufacturing factors that can affect the finished IC reliability. This table, which is still valid today, was originally presented in a ASQC (American Society for Quality Control) tutorial seminar given in San Jose, California, in 1978 entitled Factors Impacting IC Reliability Today by J. N. Thielmann [1]. It is reprinted here with permission from the American Society of Quality Control and the author. Table 17.2 summarizes the manufacturing faults by defect category as discussed herein.

The Bathtub Failure Curve

The bathtub failure curve observations and studies have shown that failures for a given piece part or equipment consist of a composite of

Quality

Unrelated to stress; not time dependent

Eliminated by inspection and process improvements

Reliability
Stress dependent
Eliminated by screening

Wear-out
Time dependent

Eliminated by replacement, part redesign, or new source

Design

May be stress and/or time dependent

Eliminated by proper application and derating

This composite diagram, referred to as the bathtub failure curve, provides a framework for identifying and dealing with all phases of the life of parts (ICs) and equipment. The bathtub curve is divided into three sections, based on the time when failures occur:

1. Infant mortality or early life failures, are failures due to a variety of failure mechanisms generally associated with manufacturing defects, such as cracked packages, bad bonds, die surface damage, bad oxide, poor step coverage, etc. Infant mortality failures are both time driven (accelerate chemical reactions with time) and event driven (voltage).

2. Useful life or main failures are those occurring during the prolonged operating period of the IC. Main life failures are considered to be due to basically one failure mechanism, with a single, apparent activation energy.

3. Wear-out failures occur because of aging (longevity exhausted). The wearout region is where the fundamental materials breakdown and wear out.

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Figure 17.1 graphically depicts the infant mortality, useful life, and wear-out distribution regions. The failure rate of each region of the bathtub life curve is caused by parts/equipment failing because the applied stress over time exceeds the strength of the materials/parts/equipment.

The physical/chemical degradation process (steps) that lead to failure is called the failure mechanism. The root cause of a failure situation (stress exceeding strength) may be due to the presence of stress factors and conditions of such a magnitude that accelerate (speed up) the process of degradation (aging); or it may be due to a defect (weakness) introduced as a result of manufacturing variations, or a combination of both.

Significant variability can occur in failure mode distributions as a result of variations in device maturity, the time period over which data was collected, application stresses, device quality, and manufacturing specific variables.

The fundamental principles of reliability engineering predict the manner in which the failure rate of a group of ICs, when subjected to an accelerated life test, will follow the bathtub curve of Fig. 17.1.

All classes of failure mechanisms can be assigned to one or more of the regions as is shown in Table 17.3, which provides a detailed listing of the specific failure mechanisms encountered in each of these regions. Table 17.4 summarizes the failure rate issues delineated by the bathtub failure curve.

Figure 17.1
Bathtub failure curve.

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Table 17.4 Summary of IC Failure Rates

Most well-designed high-quality ICs (or systems) appear to follow a continuously decreasing failure rate for a long time at most common levels of system stress.

ICs should be considered on a family-by-family basis when trying to determine the time dependence of their failure rates. It is possible that one family may yield different time-dependent results than another.

A second failure rate dependence also existsthat of reaction to a variety of stresses. Each stress may follow a different curve for a given IC family.

An IC may be viewed as a collection of many (often more than 10) failure mechanisms, which may have different stress dependences in time as well as a sensitivity to type and level of stress.

In reality, ICs have a few dominant failure mechanisms with many other latent mechanisms present. It is these dominant mechanisms that are normally used to model an IC.

It is easier and cheaper to design a process that yields the desired conformance goalsand so reliability goalsthan it is to try to sort and screen a low-quality process to achieve the same goals.

Source: Ref. 3.

The Arrhenius Equation and Temperature Acceleration

Most IC failure mechanisms involve one or more physical or chemical processes, each of which occurs at a rate that is highly dependent on temperature; chemical reactions and diffusion mechanisms are examples of this. Because of this strong temperature dependency, several mathematical models have been postulated to predict the temperature dependency of various chemical reactions.

The most widely used model is the Arrhenius reaction rate model, determined empirically by Svante Arrhenius in 1889 to describe the effect of temperature of the rate of inversion of sucrose.

Arrhenius postulated that chemical reactions can be made to occur faster by increasing the temperature in which the reaction occurs. The Arrhenius equation is a method of calculating the speed of reaction at a specified higher temperature and provides the basis for

R(T) = A exp -(Ea/KT) (1)

where

A = constant

exp = natural logarithm, base 2.7182818

Ea = activation energy for the reaction (eV)

K = Boltzmann's constant = 8.625 × 10⁻⁵ eV/K

T = temperature (K)

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Today the Arrhenius equation is widely used to predict how failure rates vary with different temperatures. The failure mechanisms are primarily chemical in nature. The activation energy (Ea) is a factor that determines the slope of the reaction rate curve with temperature; it describes the accelerating effect that temperature has on the rate of a reaction and is expressed in electron volts (eV). For most applications, activation energy is treated as a slope of a curve rather than a specific energy level. This is demonstrated in Fig. 17.2, which graphs the results of constant-stress accelerated life tests. The straight line plot in (a) indicates a single failure mechanism, while the plot at (b) having an inflection point indicates the existence of a multiple failure mechanism. A low value of Ea indicates a small slope or a reaction that has a small dependence on temperature. A high value of Ea indicates a high degree of temperature dependence.

Every chemical reaction, diffusion mechanism, and the like has its own unique activation energy, Ea. In an integrated circuit there are several such reactions proceeding simultaneously, each of which is capable of eventually causing a failure. The cumulative effect of several different Arrhenius reactions will result in a device failure rate that exhibits some complex non-Arrhenius, temperature-dependent failure rate.

Specific chemical reactions have specific activation energies; ICs, as components, do not. Nonetheless, activation energy is frequently applied to ICs for temperature-dependent reactions even though there may be no chemical reactions taking place. For ICs, where the distribution of failures remains fairly constant among the various mechanisms or reactions, the cumulative effect of these various reactions is a failure rate whose temperature dependence is approximately exponential over a limited temperature range. Thus, there is a tendency to refer to an activation energy for a given IC family. Even though this is erroneous, it is used to indicate that the IC is exhibiting a failure rate that has a similar temperature dependence to an IC failing because of a single mechanism with the specified activation energy.

Figure 17.2
Relationship of activation energy to failure mechanisms.

Page 718

Thus, the activation energy in Eq. 1 is a measure of the relationship between temperature and time for failure mechanisms in ICs. The relationship of this use of activation energy for IC failures to the semiconductor physics definition of such features as barrier or quantum energy levels (1.11 eV for silicon at 27°C) is not definite except for specific cases such as the energy required to form or break a chemical bond. This equation shows the basis for using burn-in. Increasing the temperature, T, reduces the time to a particular percentage failure for a certain activation energy failure mechanism, with the higher temperature providing the energy necessary for the reaction to occur.

Note that when considering a specific temperature, it could be invalid to compare failure times for different activation energies because the constant, A, may be different for different failure mechanisms with different activation energies. For example, it could be incorrect to assume, at a certain temperature, that a higher activation energy failure mechanism will take longer to cause a certain failure percentage than a lower activation energy because the constant, A, may not be the same.

Activation energies for various IC failure mechanisms range from 0.3 to 2.3 eV. However, for currently produced VLSI circuits, the activation energies are much lower than the 0.71.0 eV that is automatically assumed, due to better process controls and tighter design margins than previous generations of ICs (see Table 17.5).

Examples of Temperature-Dependent IC Failure Mechanisms

Many IC failure are dependent on temperature, which conforms to the Arrhenius reaction kinetic model. Several examples of temperature-dependent IC failure mechanisms are now presented.

Temperature Acceleration Factor in Au-Al Bonding

The degradation of bonding strength due to the formation of intermetallic compounds is a typical failure mechanism that is accelerated by temperature. Presently most ICs use aluminum for the chip metallization and fine gold wires for connections to the external leads. When thermal stress is applied to the interconnections, intermetallic compounds are formed between the gold and aluminum. Also, a Kirkendall void is formed at the boundary of the two materials because of differing diffusion coefficients, resulting in an increase in contact resistance, which sometimes results in an open circuit.

EPROM Data Retention Characteristics

The temperature acceleration in the data retention characteristics of the EPROM is well known. The phenomenon is caused by electrons, stored in the floating gate, escaping to the silicon substrate or to the control gate, causing changes in data. To estimate the data retention time, a steady-state operation test

Page 719

and high-temperature storage test as an acceleration test must be performed. From test results under various temperatures, activation energy is found to be approximately 1.2 eV as shown in Fig. 17.3. The remaining devices will then be entirely in the main life category and accurate reliability predictions can be made.

Burn-in is the concept of eliminating and removing Stage I Infant mortalities from a production lot of semiconductors. It is therefore possible to improve the reliability level of a population of parts by identifying and removing early life (infant mortality) failures from a production lot of parts. Hence, while it is true that burn-in cannot improve part reliability, reliability of a population of parts can be improved by utilization of burn-in and environmental stress screens in order to identify and remove those early life failures.

Burn-in screening, used to remove infant mortalities from the main population of ICs in a lot, combines electrical stresses with high temperature to

Figure 17.3
Typical data retention characteristics of EPROM ICs.

Page 720

activate the temperature-dependent failure mechanisms in a relatively short time. An acceleration factor may be calculated by using the Arrhenius equation.

Modifying the Arrhenius equation for burn-in produces an equation in which failure rate data taken at one temperature may be translated to another temperature with reasonable accuracy.

t=t₀ exp (E/KT) (2)

where

t = MTBF (mean time between failures) at the desired temperature

t₀ = MTBF at the test temperature

exp = natural logarithm, base 2.7182818

E = thermal activation energy (eV)

K = Boltzmann's constant (8.625 × 10⁻⁵ eV/K)

T = test temperature (K)

The acceleration factor may be calculated by

F = exp E/K(1/T₁ - 1/T₂) (3)

where T₁ is the test temperature (K) and T₂ is the desired temperature (K).

Figure 17.4 shows an Arrhenius plot with several thermal activation energies for common failure mechanisms.

Thermal activation energy describes the temperature dependence of a failure mechanism and is the slope of the plot of failure rate or its reciprocal, life, versus the reciprocal of temperature (see Eqs. 2 and 3). Equation 2 can be solved for E, giving

(4)

Modifying the Arrhenius equation for burn-in produces the equation for acceleration factor, which may be calculated by

A = tn/tBI = exp [Ea/k(1/Tn - 1/TBI)] (5)

where

tn = time at normal operating temperature (hr)

tBI = time at burn-in (hr)

Ea = activation energy (eV)

k = Boltzmann's constant

Tn = device operating temperature during normal operation (K)

TBI = device operating temperature during burn-in (K)

Let's take an example. If a device is to be burned in with an ambient temperature of 125°C (398 K) for 168 hr (7 days), the acceleration factor with

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the device operating under normal conditions, with an ambient temperature of 50°C (323 K) may be calculated as follows:

Ea = 0.6 eV (6)

tn = 168 exp[0.6/8.6 × 10⁻⁵ (1/323 - 1/398)] = 9840 hr = 1.1 yrs

The exponential part of Eq. 5 can be considered a time acceleration factor, leading to the common terminologyaccelerated life. In this sense, burn-in is a short accelerated life test. The intent of burn-in is to accelerate the life of the devices to the time when all infant mortality and freak failures have occurred.

A 0-eV activation energy failure mechanism is not accelerated at all by burn-in. If two failure mechanisms are present in a group of devices, and Eq. 2 is known to be or is assumed to be valid for both mechanisms, the failure mechanism with the higher activation energy will be accelerated more by burn-in than the failure mechanism with the lower activation energy. The Arrhenius curves of Fig. 17.4 show the time-temperature equivalence between various burn-in temperatures for various values of activation energy. As just pointed out, note that for low activation energy the acceleration effect of burn-in is not as pronounced as for high values of Ea. However, the screening effect of burn-in can only be assessed if the appropriate value of A in Eq. 1 is known for both mechanisms. Or, if the median life and standard deviation for both mechanisms is known, A will be known and the screening effect can be evaluated.

However, some failures that occur during system use are due to test escapes or quality failures, that is, ICs that may have been burned in and electrically tested and then inserted in the end equipment fail for no apparent reasoneven after years of operation. Some of the reasons for these failures are as follows: (1) The ATE test program did not exercise the device completely (inadequate test coverage from CAD, logic simulation and fault simulation models due to effectivity versus cost tradeoffs, and comprehensiveness of the models and compatability of the models with the ATE), (2) the tester (ATE) malfunctioned and accepted a bad device, (3) the device did not get tested, either intentionally (sampling plan instead of 100% inspection) or unintentionally, or (4) the device had a soft failure mode. Burn-in could be expected, in general, to have little effect on the removal of these types of failures.

In practice, the Arrhenius relationship has been proven to be useful for many failure mechanisms even though not all failure mechanisms are due to chemical reactions. The failure rates due to a given mechanism, determined through accelerated stress tests and extrapolated to operational temperatures, are not necessarily the failure rates that will be observed in the field. More work is necessary to determine the sensitivity of activation energy to temperature. The overall failure rate model theoretically should be a series of Arrhenius models (supplemented with non-temperature-dependent mechanisms) each having a rate constant and activation energy specific to the particular failure mechanism.

Page 722

Figure 17.4
Arrhenius plot.

Page 723

The reliability of an IC is a function of its design, manufacture (including fabrication, testing and screening), and use, and burn-in should be evaluated as an interrelated operation in this entire sequence.

Activation Energy

Failure mechanisms have specific activation energies that determine how strongly their time-to-failure depends on temperature. Once a sufficient amount of stress data is collected, time-to-failure curves for different failure mechanism activation energies can be generated, yielding the acceleration factor for burn-in at increasingly high temperatures.

If an activation energy is known, then one can calculate the acceleration factor between two temperatures. Conversely if the acceleration factors are experimentally determined at two temperatures, the activation energy can be calculated.

The actual design and fabrication process determines the types of defects that will occur and their activation energies. Each manufacturer has its own design architecture for the same type of IC component. But even at different wafer fabrication facilities owned by the same manufacturer, the same design can produce ICs with different sensitivities to various failure mechanisms.

The production of high-reliability ICs requires the use of efficient screens and tests that are designed to remove ICs with infant mortality failure mechanisms. Figure 17.5 shows an example of the high failure rate caused by infant mortality failure mechanisms and the reduced failure rate resulting from removal of these early failures by effective burn-in. The distinction between infant and wear-out failure mechanisms is determined by their relative statistical parameters that may vary greatly for different IC technologies. For example, time-dependent dielectric breakdown (TDDB) is usually an infant mortality failure mechanism for CMOS technology with oxide thicknesses down to 300 Å but is a wear-out mechanism for technologies with gate oxide thicknesses of 100 Å or less.

Burn-in uses the acceleration factors of both temperature and electric field (voltage) to predict the approximate lifetime of an IC and to determine equivalent stress conditions, depending on expected failure mechanisms.

Temperature Stress. A temperature acceleration factor is used to calculate the time required to stress a device at a different temperature level. A higher temperature requires less stress time. For example, if a device is exposed to a high-temperature stress of 140°C for 72 hr, the temperature acceleration factor can be used to calculate the equivalent time required to stress the device at 175°C. For this case, assuming Ea = 0.6 eV, it will only be 19 hr instead of 72 hr.

Electric Field Stress. An electric field acceleration factor (voltage or current) is used to calculate the time required to stress the device at different electric field levels. A higher electric field stress also requires less time.

Page 724

Figure 17.5
IC failure rate versus system operation time without burn-in and with
burn-in at 125 and 150°C.

The effects of both temperature and electric field stress must be taken into consideration since burn-in is designed to catch failures that are both temperature and electric-field sensitive.

Most IC manufacturers use accelerated stress tests to determine product failure rates and calculate activation energies, and to understand how the accelerated conditions are translated to standard operating conditions. For example, Intel uses both temperature and voltage acceleration techniques and requires that the thermal activation energy (Ea) and voltage acceleration factor is determined, or assigned, for each failure mechanism. By using the appropriate Ea, data taken at an elevated temperature can then be translated to a lower standard operating temperature through the Arrhenius equation. (Eq. 5). A graphic

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illustration of the temperature relationship, for several activation energies normalized to 1 hr at 250°C, is shown in Fig. 17.4.

Voltage-accelerated stress test results can also be translated to nominal voltage conditions, in a similar manner, by applying the appropriate voltage acceleration factor (VAF). In general Intel uses a voltage acceleration factor for time-dependent dielectric breakdown failure mechanisms only. This VAF is generally consistent throughout the industry and follows the equation

VAF = exp [C(V(sub>s - Vo)] (7)

where

VAF = voltage acceleration factor

Vs = applied stress voltage

Vo = standard operating voltage

C = a constant that is a function of dielectric type

Intel uses two different C factors for dielectrics and a range of constant factors for junction defects in its calculations that depend on the failure and dielectric type. For gate dielectrics C is defined as being equal to the ratio of the gate oxide thickness (Tox) over 100, Tox/100. The other dielectric C factor used is applied to interlevel time-dependent dielectric breakdown failures associated with random particle defects. This and the C factor for junction defects have been empirically derived from evaluations on memory test vehicles and vary somewhat as a function of the process technology and technology scaling. For logic product technologies, used as the source of the reference data in this discussion, the C factors are 1.8 for dielectrics and .41 for junction defects.

In using these acceleration factors it is important to quantify the voltage and temperature dependencies for the various failure mechanisms. In addition, analysis must be performed on accelerated stress test failures in order to identify the failure mechanism and properly apply the acceleration factors to the product failure rate extrapolations.

Two examples are presented that show this temperature and voltage dependency on a practical level. Figures 17.6 through 17.10 show the effects of temperature and voltage on threshold voltage shift (VTH) and oxide film failure in dynamic RAMs, respectively. Figure 17.6 shows the drain bias (VD) dependency of VTH shift. The increase of VD as VTH changes by tens is caused by the increase of injected electrons into the oxide film.

Figure 17.7 illustrates the gate bias (VG) effect on VTH shift. As VG decreases, the VTH shift is accelerated. The phenomenon is explained by the increase of trapping efficiency due to the decreasing energy of the injected electrons by the reversed electric field in the gate SiO₂ film.

Figure 17.8 shows an example of temperature dependency of VTH shift. Temperature dependency of VTH shift is mainly a temperature dependency of

Page 726

Figure 17.6
VD = VG bias dependency of VTH shift.

effective trap density and is due to the fact that traps are distributed shallowly and widely in the SiO₂ film.

Figures 17.9 and 17.10 show time-dependent changes of oxide film destruction failures in continuous operation life tests of dynamic RAMs. The former shows electric field dependency and the latter temperature dependency.

Figure 17.7
Gate bias dependency of VTH shift.

Page 727

Figure 17.8
Temperature dependency of VTH shift.

Figure 17.9
Stress bias dependency of oxide film failure in dynamic
RAMs.

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Figure 17.10
Temperature dependency of oxide film failure in
dynamic RAMs.

The activation energy of thin oxide film life obtained from Fig. 17.10 is approximately 0.3 eV.

Thus, bias dependency for oxide film destruction is significant, and screening with application of high electrical field proves effective in producing high-quality DRAMs. Figure 17.11 shows an example of how screening for DRAMs at high temperature and high bias is used to predict the instantaneous failure rate of RAMs in normal field conditions. To suppress the instantaneous failure rate to 3 × 10⁻⁸/hr (30 FIT) or less, screening under the same field condition (Ta = 25°C, 1 MV/cm) requires 2.5 × 10⁴ hr, but screening with high electric field at 125°C shortens screening time as follows:

1.8 MV/cm

8.7 hr

2 MV/cm

2.5 hr

2.2 MV/cm

0.75 hr

Table 17.5 is a summary of the most common failure mechanisms found in the current generation technologies and their respective temperature activation energies and voltage acceleration factors.

Problems Encountered in Applying the Arrhenius Equation [2]

The Arrhenius equation has been applied to many failure mechanisms other than those activated by temperature, because of its familiarity and ease of use. Some

Page 729

Figure 17.11
Instantaneous failure rate of dynamic RAMs.

of the problems encountered in the carte blanche use of the Arrhenius equation are as follows:

Real activation energy should reflect failure mechanisms that involve only thermal energy. Activitation energies often include the effects of voltages and currents in addition to temperature. The IC tests invariably involve voltages and currents that depend on many variables and add nonthermal stress to ICs, contributing to reported failure rates, but are often lumped under temperature effects. Engineers usually plan burn-in tests to carefully control and document device temperatures. However, they are not always as careful about voltages and currents.

Activation energy is not necessarily constant over temperature. Studies indicate that activation energy may increase at high temperatures.

Use of overly optimistic activation energies for given failure mechanisms. Many IC manufacturers simply use an activation energy of 0.71.0 eV to derate their test data in the absence of more reliable estimates. These values may have been valid in the past, but studies indicate a much lower value is appropriate for current state-of-the-art devices with better process controls and tighter design rules. Overestimating activation energies leads to failure-rate predictions that are too optimistic under normally encountered operating conditions.

Page 730

Table 17.5 Commonly Encountered Failure Mechanisms

Failure mechanism

Temperature activation energy (eV)

Temperature acceleration factor

Voltage acceleration factor (C)

Failure detection

Gate oxide defect
0.30.4

6.5

Tox/100
HTOL

Metal to poly defect
0.3

6.5

1.53.0a
HTOL

Silicon junction defect
0.50.8

144

0.00.5a
HTOL, 85°C/85%RH

Metallization defect
0.5

22

HTOL

Au-Al intermetallic growth including Kirkendall void

0.51.3

602

HTOL

Masking (poly, diffusion) defect
0.50.7

22

0.0b
HTOL

Electromigration
12 Cu-Al/Cu-Si-Al
0.5 small grain Al

77

0.0b
0.0b
HTOL
HTOL

Ionic contamination (surface, bulk)
0.61.4

499

N/A
HTOL, 85°C/85%RH

Metal corrosion
0.71.0

77

N/A
HTOL, 85°C/85%RH, HAST

Charge injection (slow trapping)
1.01.4

3221

N/A
HTOL, 85°C/85%RH

Surface charge spreading
0.51.02

565

N/A
HTOL

Stress voids
0.4

12

HTOL

Bond related
1.0

499

0.0b
HTOL, T/C, T/S

Intermetallic defect
0.3

N/A

1.53.0a
HTOL

Metal migration (contact degradation)
1.8

N/A

N/A
HTOL

TDDB
0.30.6

N/A

N/A
HTOL

Electrolytic corrosion
0.30.6

N/A

N/A
85°C/85%RH, HAST

Hot carrier trapping
-0.1

N/A

N/A
LTOL

Charge loss (EPROMs), i.e., leakage
0.61.4

N/A

N/A
Low Vcc

Bulk silicon defects
0.30.5

N/A

N/A
HTOL

Polarization (such as phosphosilicate glass)
0.51.2

N/A

HTOL 85°C/85%RH

Aluminum corrosion (penetration of water)
0.55

N/A

N/A
HTOL, 85°C/85%RH, HAST

Drift of Na ions in Si oxide films
1.21.4

N/A

N/A
HTOL

Note: Activation energy ranges are a result of different manufacturing technologies from various IC manufacturers. The temperature acceleration factors calculated were based on conditions of Ttest = 125°C; Tuse = 55°C. N/A, not available; HTOL, high temperature operating life; LTOL, low temperature operating life; T/C, temperature cycle; T/S, thermal shock; HAST, highly accelerated stress test.

aC factors will vary with the processing technology and relative technology scaling. Factors are empirically derived during the technology development cycle.

bC = 0.0 implies no voltage dependence and acceleration factor of 1.

Page 731

Figure 17.12
Failure rate versus junction temperature for selected
activation energies.

Use of a single activation energy as if a single failure mechanism is at work. Multiple failure mechanisms may be operating, and it is often quite difficult to separate them. Figure 17.12 shows how a change in assumed activation energy can lead to gross errors in predicted failure rate. Consider the case where a 200-FIT (failures per billion operating hours) failure rate at a junction temperature of 125°C is associated with each of two failure mechanisms having 0.7 and 0.3 eV activation energies, respectively. The simple numeric average of these activation energies is 0.5 eV. Naively using this value to derate the observed combined failure rate of 400 FIT to an operating temperature of 50°C predicts a failure rate of 1.18 FIT. The correct approach is to separately derate the two failure mechanisms using Eq. 8 and then add the rates to obtain a predicted total failure rate at the operating temperature:

Page 732

(8)

Subscripts o and m in Eq. 8 refer to values at the operating and measurement (burn-in) temperatures, respectively. The 0.7-eV mechanism derated to 50°C gives a failure rate of 1.74 FIT. The 0.3-eV mechanism yields a value of 26 FIT. Summing these failure rates at the operating temperature gives a value of 27.74 FITover 23 times larger than the value predicted with an average activation energy of 0.5 eV.

Synergism can exist between failure mechanisms.

Device technology, size of features, and processing variations dramatically impact the rate of failure for a given mechanism.

State changes in constituents of an electronic device may dramatically change the failure rate and make the Arrhenius approach invalid.

Observations made during accelerated stress testing may be a result of test device preconditioning.

References

1. J. N. Thielman, Factors impacting IC reliability today, ASQC Tutorial Seminar, San Jose, California, 1978.

2. A. Kostic, Pitfalls in reliability calculation, Text and Measurement World, May (1987).

3. J. A. McLinn, Reliability Review 10, December (1990).

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PART V
INTRODUCTION TO SCREENING

One of the purposes of the previous section's chapters was to present the most common IC failure mechanisms and then to show that these failure mechanisms can be accelerated by various means (electrical, climatic, and mechanical), providing an accurate means of reliability predictionshence the need for screening. The continuous striving for perfection, such as zero-defects programs that IC suppliers pursue, do indeed provide continuous reliability improvements. It is hoped that the pursuit of this goal will at sometime, hopefully, in the not too distant future, change the slope of the bathtub curve for ICs such that infant mortality type failures can be eliminated. However, until the time when IC suppliers can and do eliminate or satisfactorily reduce the high percentage of infant mortality failures, screening and/or rescreening is the only alternative to reliability improvement.

This leads one to ask the following questions. What is screening and what is rescreening? As discussed herein, screening is defined as a process of electrical and environmental stresses imposed on 100% of the devices in a lot or group of like devices to identify and eliminate defects. Screening is usually performed by the part supplier. Rescreening is defined as any subsequent screening of a device

Page 734

which has already successfully passed screening and is performed by the user or an independent testing laboratory and is aimed at identifying specific device failure mechanisms. Rescreening may be to the same or a different (upgrade screens) series of screens as the original sequence.

Testing is the process of subjecting an IC (typically not 100% of a lot or of all lots) to conditions designed to determine whether or not the IC meets its specified performance requirements. The conditions of a test may duplicate those of a screen, but often they do not. Tests are typically performed once or periodically (e.g., qualification tests and ongoing reliability tests, or ORT) or as required to meet a specific need (e.g., electrical parameter selection).

Screening a part does not make it more reliable, but the reliability of a population or lot of parts is improved because infant or early life failures are removed from the population thereby making the population more reliable. Reliability is an inherent quality and function of the design and manufacturing processes. As a result, the more mature device technologies tend to produce the more reliable devices. The yields of a mature, high-volume process are also inclined to be higher, but high yields do not necessarily mean high reliability. The extent to which devices are screened and the severity of the screening depend on the type of parts as well as the end application.

These definitions of screening and testing come from the Institute of Environmental Sciences.

Page 735

18
Screening

Introduction

Integrated circuit screening requirements originated in the late 1950s and early 1960s from the requirements of the Department of Defense's Minuteman I Missile Program. In the 1960s and through to the mid 1980s a 100% screening mindset, on the part of the users, prevailed as the means of ensuring defect-free high-quality ICs; screening was the magic elixir. Since then much has changed. The level of integration has increased dramatically, as has the quality of the ICs produced.

Today, screeningmake that testingin conjunction with computer simulation is an integral part of the IC manufacturers' continuous improvement process. Design of experiments and testing are used to identify potential device weaknesses during the IC qualification process and through ongoing reliability testing to produce more robust designs.

The IC manufacturers screen parts to

1. Remove infant mortality manufacturing related defects that usually occur in a small percentage of devices or in a maverick lot within a very short time of use.

Page 736

2. Gather data to determine the effectiveness of various design and process changes.

3. Determine if the applied screen is effective and required any longer.

Screening (or environmental stress screening, ESS) is a temporary measure that is judiciously used to enable IC users' product shipments to be made without compromising and deleteriously affecting end-product reliability until permanent corrective action of the true root cause is implemented. Quality cannot be tested or inspected into an IC; it must be designed and manufactured in up front. The literature contains numerous examples of IC manufacturer-instituted screens as a result of application-driven defects discovered by the device users. These screens were used until the appropriate design and/or process changes were made. Some of these diverse examples are now presented to show that the use of manufacturer-instituted defect screens is not uncommon and to validate my point.

Example 1

Part type:

1DT 64K × 1 SRAM

Symptom:

SRAMs were dropping bits.

Problem:

Some lots received wrong source/drain diffusion, causing hot electron injection and resulting in reduced threshold voltage. The manufacturer's standard temperature test did not uncover this problem.

Screen:

Low-temperature (-40°C) electrical testing aggravates and accelerates this problem.

Source:

Electronic Buyers News, November 1, 1989.

Example 2

Part type:

Intel 8259 and 8288

Symptom:

Parts failed functional test marginally at -55°C.

Problem:

Parts have noise sensitivity at cold temperatures. Greater than 400 mV on Vcc or Gnd will cause parts to fail.

Screen:

Low-temperature functional test.

Example 3

Part type:

Hitachi 4M bit DRAM

Symptom:

Lost (data) bits during system operation.

Problem:

At slow Vcc turn-on ramp rates, faulty on-chip logic would select faulty columns rather than redundant good columns, as a result of critical process parameters being out of control. Testing at normal ATE Vcc power supply levels and ramp rates would not find the problem.

Screen:

Test parts at slow Vcc ramp rate.

Page 737

Example 4

Part type:

82052 UART

Problem:

Output data error.

Cause:

Investigation revealed internal race conditions that occurred only at low temperatures and high supply voltages in system use. Serial data was shifting into the register incorrectly, causing extra bits to be set. Thus, data read from receive register were different from the actual data received.

Screen:

The supplier instituted a low-temperature (-40°C), high-Vcc (5.6 V) screen.

Example 5

Part type:

ACTEL ACT 1010 and 1020 FPGAs

Problem:

FPGAs exhibited postprogramming failure; not all gates were programmed.

Cause:

In some of the on-chip programming paths, the current was too low to program the antifuse element. The failures, which were design dependent, were found to exist even though the ACTEL programming software showed the device having passed programming.

Screen:

100% Functional test was performed on all programmed parts within the suspect data code category until design and software programming changes were made.

Source:

Electronic Buyer's News, February 5, 1990.

Example 6

Part type:

Intel 80486 microprocessor

Problem:

This design incorporated a new three-metal layer process. The floating-point on-chip section produced incorrect numerical results. A mask change was instituted to fix a single layer metal problem.

Problem:

Operation of the 50-MHz version at high frequency and high operating temperature can hang, reboot or return from an application to a DOS prompt.

Screen:

Intel's extensive testing program did not catch these defects. Shipments of the 80486 were terminated until proper design and process changes were made. Intel began using a new set of testing procedures on its test equipment (ATE) to make sure the deficient chips were caught by the test.

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Source:

Electronic Buyer's News, November 14, 1989.

Electronic Buyer's News, September 3, 1991

Example 7

Symptom:

Plastic-encapsulated TO-92 ICs experienced failure in an automotive distributor application.

Problem:

Analysis of failed parts revealed broken bond wires mostly above the neck of the bond. An investigation into the incident revealed the following: The die, once attached and wire bonded, is coated with an RTV silicone; then the entire unit is encapsulated in epoxy. In the process of attaching this device to the PC board, ultrasonic cleaning is performed. The difference in the elastic modulus between the lead frame, die, bond wires, RTV silicone, and epoxy allow movement within the plastic package during the ultrasonic cleaning. The gold wire resonates and breaks. The use of ultrasonic cleaning has been discontinued and the supplier has changed the die coat material to be more compatible (temperature coefficient of expansion and modulus of elasticity) with the epoxy being used.

Screen:

Perform temperature cycling followed by electrical tests on all ultrasonically cleaned parts.

Example 8

Problem:

EEPROM in an embedded credit card application experienced intermittent memory loss.

Investigation:

Filler encapsulant material had large particulates, which lodged vertically in the IC passivation layer. Mechanical stress in the credit card assembly procedure caused these particulates to puncture the passivation layer and damage the EEPROM memory cells located underneath, causing memory loss.

Corrective action:

Changed filler material; problem went away.

Screen:

Perform functional test of credit card.

Example 9

Symptom:

A high incidence of failed PC boards and equipment field failures were experienced by an equipment manufacturer.

A second source for the equipment using the same board design and components did not experience the failure.

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Problem:

The failed boards were traced to ceramic ICs that contained cracked dice. Further investigation revealed that the ICs were mounted onto the PC board with a Gelzer pick-and-place robot that subjected the ICs to between 3000 and 4000 g's of mechanical shock, cracking the die.

The second source did not use a robot for IC insertion.

Screen:

Existing boards were temperature cycled and electrically tested to remove PCBs containing defective ICs.

Let me reiterate the main point. These screens were temporary and were only conducted until the IC manufacturer or equipment manufacturer (Examples 8 and 9) incorporated design and/or process changes that provided permanent corrective action.

ESS Overview

The materials making up an integrated circuit clearly are not in a state of equilibrium with one another, so that a circuit structure is destined to change with time. The application of external stresses will accelerate these changes and is likely to introduce added degradation mechanisms. Manufacturing mistakes (errors) generally leave flaws, which may directly result in either reduced strength or another problem in a critical region of the circuit. In addition, defects often create stress concentrators, which further enhance the rate of degradation.

The goal of environmental stress screening (ESS) is to cause defects resulting from manufacturing mistakes to become detectable failures without doing damage to otherwise good material. Screening is not supposed to directly correct for circuit design or manufacturing problems. The defects of interest to ESS are those that are likely to become service failures if not located by the screening procedures.

The intrinsically delicate nature of advanced integrated circuits makes it reasonable to expect that the environmental screening stresses that prove effective for accelerating the degradation of flawed material to failure may also degrade satisfactory circuit materials. For example, incipient fatigue crack growth mechanisms are probably initiated at particular sites in satisfactory material during the very first mechanical cycle. Similarly, interatomic diffusion proceeds at room temperature and is accelerated as the temperature is raised. In other words, the circuit wear-out mechanisms are likely to be operating and may be accelerated by the externally imposed screening stresses. However, if both the circuit and the stress screen are properly designed, the effective lifetime of a flaw-free circuit should remain safely within the desired operational life of the electronic system. The concept is effectively to trade an acceptably small fraction

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of the total life of a circuit for assurance that a catastrophic failure will not occur within the system's designed performance lifetime.

The actual accomplishment of this goal requires careful consideration and understanding of the expected flaws produced by manufacturing mistakes and the degradation mechanisms by which these flaws can cause failure during the screen. In order to design a screen from engineering principles it is essential to establish a quantitative knowledge of the relationships between degradation to good circuit material and the type and magnitude of stress imposed. Similarly, one needs to have quantitative knowledge concerning the type and magnitude of stress, or stresses, that will cause specific types and sizes of defects to degrade rapidly enough to result in failure during the screen. Table 18.1 summarizes the factors leading to the design of an effective stress screen. Ideally, one could then predict the stresses needed to screen out all manufacturing mistakes and also be able to estimate the fraction of life lost to circuits without defects due to application of the stress screens.

For several reasons, the information required for this quantitative analysis is difficult to obtain. The current knowledge concerning materials interactions is not sufficiently precise for the design of effective environmental stress screens. Circuit features are very small, the material configurations and their interactions are complex, and there is often a wide range of potential defects. For this reason, existing screens are largely based on empirical approaches. However, the application of ESS must be approached from an understanding of the fundamental degradation and failure mechanisms possible for a given device type/technology and a knowledge of which screens are most effective in accelerating those failure mechanisms.

Table 18.2 provides a listing of failure mechanisms and the means of accelerating these failure mechanisms to precipitate (remove) infant mortalities. The acceleration means that result in some specific wear-out failure are listed in Table 18.3.

Table 18.1 Requirements for the Design of an Effective Stress Screen

Knowledge of material performance under a wide range of operating and environmental stresses

Quantitative relationships between defective sizes, magnitudes, etc. and acceleration of degradation mechanisms

Knowledge of threshold levels

Knowledge of degradation mechanisms that cause device failure due to specific defects

Detailed stress analysis with advanced methods

Statistical design and mathematical modeling

Precise testing instrumentation to detect faulty circuit components

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Table 18.3 IC Wear-Out Failure Mechanisms and the Means of Acceleration

Wear-out failure mechanisms

Acceleration stresses

Fatigue crack initiation
Mechanical stress/strain range
Cyclic temperature range
Frequency

Fatigure crack propagation
Mechanical stress range
Cyclic temperature range
Frequency

Creep
Mechanical stress
Temperature

Wear
Contact force
Relative sliding velocity

Diffusion
Temperature
Concentration gradient

Interdiffusion
Temperature

Corrosion
Temperature
Relative humidity

Electromigration
Current density
Temperature
Temperature gradient

Dendritic growth
Voltage differential

Radiation damage
Intensity of radiation

Surface charge spreading
Temperature

Slow trapping
Temperature

Stress corrosion
Mechanical stress
Temperature
Relative humidity

Most Commonly Employed Screens*

The imposed stresses of an environmental stress screen are intended to either accelerate degradation mechanisms associated with the presence of a manufacturing flaw to early failure or otherwise reveal the existence of the defect. Ideally, the probes or stresses will not degrade good devices. However, the stresses needed to screen for defects will likely introduce nonreversible microstructural and chemical modifications in normal IC materials as well. Certain of the material changes induced by some applied stresses are actually beneficial to the durability of the circuit structure. However, most stresses are more likely to produce

*Portions of this section from discussions with Dr. Billy Livesay, Georgia Institute of Technology.

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modifications that effectively consume a part of a device's operating life. For well-designed, mature ICs and a carefully conceived stress screen, the portion of the device life consumed by the screen is minute and overwhelmingly compensated for by greater reliability performance of the system.

The detailed response of circuit materials to the available environmental stresses is crucial to the successful application of a screen. Let us briefly examine the effects that variations in temperature have on the activation of different failure mechanisms:

1. Solid-state diffusion is greatly enhanced as the temperature is increased. The high diffusion rates accelerate such phenomena as interatomic diffusion across interfaces, the growth of intermetallic compounds, recrystallization, and the growth of whiskers, hillocks, and precipitates. Particular dopant species may diffuse more rapidly than atoms of the primary lattice material, thus changing the local chemical composition.

2. Chemical reaction rates are greatly enhanced at elevated temperatures.

3. The materials used to fabricate an IC have different thermal coefficients of expansions; mechanical stresses are thereby imposed on circuit materials at all temperatures, with greater temperature changes introducing correspondingly greater mechanical stress levels. Temperature cycling induces thermal mechanical stresses equivalent to the mechanical cycling, which activates fatigue mechanisms in the microstructures of metals, polymers, and dielectrics.

4. The rapid heating or cooling of ICs introduces differential thermal expansion in circuit materials because of thermal gradients. High values of thermal gradients cause correspondingly high localized mechanical stresses. High thermal gradients are transients that are generally produced in electronic parts by rapid transfers between hot and cold air chambers. Rapid heating with the associated localized differential expansion also occurs in electronic devices subjected to sudden high power levels, such as equipment on-off power cycling.

5. Temperature lowered to below the dew point of the microenvironment within a package can accelerate corrosion processes by condensing moisture at sites on surfaces where chemical residues combine with moisture to become corrosive.

The most common types of IC screens that are used to eliminate both die-related and package-related defects are as follows:

Internal visual inspection [also called precap (or preseal) visual]

Stabilization bake (also called high temperature storage)

Temperature cycling

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Constant acceleration

Hermeticity [also called seal or leak test (fine and gross leak)]

Particle impact noise detection (PIND)

Electrical test

High-temperature reverse-bias (HTRB) burn-in

Burn-in

X-ray inspection

External visual inspection

It is important to realize that different screens are needed to detect different failure mechanisms, because no single screen is effective in precipitating all defects. The criteria used to select screens that are conventional, efficient, economical, and nondestructive are

Determine the dominant failure mechanisms for each technology, part type, and package configuration.

Evaluate the type, magnitude, and duration of the stresses that activate the various failure mechanisms and their associated failure modes. Determine if these stress parameters can be accomplished by using conventional screens.

The screens just discussed, as applicable, are usually performed in a specific sequence (see following section, Screening Sequence) to detect the mix of failure mechanisms most appropriate for the device types being used and for the end-use application. Thus the selection of a screen depends on

The device technology, chip design, maturity, and user history

The expected failure mechanisms

The part history (previous experience with the same part technology)

The IC supplier history (previous experience with a particular supplier)

The intended application, design derating, and criticality of the parts in the end application

Additionally, when developing a screening strategy, one must take into consideration the following:

The stress screens and electrical tests must eliminate or significantly reduce the population of these defective devices.

Handling and testing must not introduce degradation or damage and must not seriously jeopardize part life span.

Screening procedures should be standardized and routine.

Once the failure mechanisms have been identified and understood, then the appropriate screens of Tables 18.4 and 18.5 can be implemented; Table 18.4 presents some common failure mechanisms and the screens used to precipitate the underlying defects to failure, whereas Table 18.5 compares the effectiveness

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of various screens in precipitating the appropriate defects. It should be noted that electrical measurement tests must be performed after screening to detect device failure and ensure device conformance to specification limits. For some of these screens (bake, temperature cycling, constant acceleration, and burn-in), the only means of detecting failure is in the subsequent electrical tests.

In general, the application of elevated temperatures to ICs will accelerate chemical degradation due to improper combination of materials during device fabrication or to the presence of contaminants within the package or circuit materials. Elevated temperatures also relieve residual mechanical stresses within metals of the circuit. Good wire bonds can actually be improved during the bake, while reactions taking place at the interfaces of poor bonds may induce them to life off.

High-temperature storage environments accelerate solid-state diffusion, accelerate the growth of dendrites and whiskers from impurities, accelerate the precipitation of second phases, accelerate surface corrosion mechanisms, and induce mechanical stress (tension or compression) in the layered structures on a chip as well as at bond or solder interfaces.

Mechanical stresses imposed by either direct mechanical or thermal mechanical environments will result in abnormally high stress levels at mechanical flaw locations. Typically, microcracks, hard precipitates, and abnormally thin features become stress concentrators in material structures. Thermal cycling will likely initiate mechanical fatigue degradation mechanisms in all circuit materials, but the processes will be greatly accelerated where mechanical or chemical defects have created a stress concentrator. Thus the cyclical stresses created during temperature cycling are employed to accelerate crack growth mechanisms at such defects to produce failure during this stress screen.

The pure or lightly doped aluminum, gold, and solder alloys are exceptionally weak materials when compared to standard structural alloys. The IC industry succeeds with these materials because internal stresses are generally low and because of the interface-strengthening factors built into the IC device structures. Chemomechanical mechanisms are important here because surface chemical reactions may alter the physical nature of the interfaces upon which mechanical strength of thin materials may be based. Soft materials such as aluminum (Al) and gold (Au) may deform and accommodate mechanical stresses, but brittle materials such as glasses and oxides may fracture. These mechanical factors are becoming increasingly more important for micrometer and submicrometer geometrical IC configurations. The use of thermal mechanical stress screens will have to be carefully evaluated with these developments in mind.

Mechanical stresses are difficult to apply directly to circuit materials for stress screening. The nondestructive bond pull tests employed in some circuits having high bond counts might be considered a special case example. Otherwise a centrifuge can be used to impose a constant acceleration on circuit materials such that their inertial mass essentially tugs on a wire bond or a die attach. High

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accelerations, and inertial forces, can be produced using transient mechanical shock techniques. However, due to the low density of aluminum, the forces on aluminum wires associated with reasonable values of constant acceleration are usually too small to serve as an effective screen for poor wire bonding.

Mechanical stresses are also internally applied by mechanical shakers where the inertial masses of various circuit features and the manner in which they are joined determine the magnitude of stress levels in the materials. Because the masses are small in IC materials, the inertial forces applied with these methods will be correspondingly low.

Thermal and mechanical shock stresses should be very carefully considered before being included as a screen. Severe thermal (liquid) shocks can generate tiny microcracks in good insulators or dielectrics which may then result in failure during the operating or storage life of a device. The growth of microcracks in ceramics is facilitated by exposure to tiny amounts of such chemical agents as water by lowering its attendant surface energies.

Stresses associated with applied electrical potentials become initiators for numerous electrochemical mechanisms and impurity diffusion within dielectrics and semiconductor materials.

Electric currents induce joule heating, thus accelerating diffusion. High-density electron flow also induces directed atomic diffusion mechanisms in metals, commonly known as electromigration. Where the manufacturing defect involves a thinned conductor or else an impurity-loaded interface that results in abnormally high current densities, electromigration mechanisms may be accelerated during the screen to reveal the defect. In the past, screen temperatures and current densities have not been considered as an appreciable amount of the electromigration wear-out life. However, this may not be the case for particular circuits where design parameters have been extended. Electromigration degradation mechanisms involve the simultaneous creation of voids, hillocks, and sometimes whisker growth. The voids reduce conductor area, ultimately resulting in burn-out, while the hillocks and whiskers may punch through and short to adjacent conductors.

Residual gas analysis using mass spectrometer instrumentation has become an important package quality analysis method. The importance of the technique is that moisture-related impurities encapsulated during a hermetic sealing operation or chemical agents outgassing from polymers within the package can cause premature operation or storage failures, but might not be sufficient to precipitate a failure during the environmental stress screen. These types of manufacturing flaws are normally problems associated with either defective processing equipment or bad materials. Thus, lot-to-lot information may be appropriate.

Conventional Screening Procedures

Standard procedures have been developed for screening or rescreening integrated circuits and are contained in MIL-STD-883, Test Methods and Procedures for

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Microcircuits. Method 5004, Screening Procedures, of MIL-STD-883 presents a detailed screening plan that is coordinated and approved within the government and industry. These are the screening methods used by most IC suppliers for the development and control of various screening programs available within their product lines and by users for their rescreening programs.

Screening Sequence

A screening program should have a purpose, an analysis and feedback of gathered data, should drive continuous improvement, and should have a defined end. The sequence of applying the different screens is an important factor for the effectiveness of environmental stress screening. The electrical tests should be performed before and after the screens, because these tests permit the determination of screening effectiveness. In addition, hermeticity screens might best be performed near the end of the sequence. The conditions employed in hermeticity screening are not likely to push defects to failure, but thermal and mechanical stressing can accelerate a microcrack or other defect in a seal so that it can be detected by the hermeticity screening techniques.

Because of the manner in which diffusion mechanisms proceed, the thermally activated processes should be stimulated early in the sequence. Elevated temperatures also encourage chemical reactions to proceed at higher rates. Corrosion processes that reduce thin film conductor widths or that cause lifting of metallization layers are accelerated by temperature. The degradation of contaminated bond interfaces is also accelerated. The cyclical mechanical stresses caused by temperature cycling are subsequently used to encourage these, now larger, defects to proceed to fracturebreaking electrical contact sufficiently to reveal failure. Burn-in subsequent to the high temperature stabilization bake can stimulate separation of excessively thin conductors through overheating or accelerated electromigration. Elevated temperatures also anneal metals, providing benefits to good bonds and metallization layers having residual stresses while they accelerate degradation of the contaminated interfaces in bad bonds. Elevated temperatures and electric currents can cause thin conductors at oxide steps to degrade rapidly and can accelerate the precipitation of large silicon particles where metallization processes are no longer in control. Subsequent thermal mechanical, pure mechanical, or electrical stress pushes these defective sites to failure. The temperature cycling amplitudes normally employed during screening produce mechanical stresses within circuit materials, which activate low cycle fatigue mechanisms at sites of susceptible defects.

The screening sequence employed for a particular IC must take into account the specific materials and configuration involved in construction of the device. The analysis should consider the types of expected failure mechanisms as well as other relevant mechanisms and factors to anticipate how the stresses will cause

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expected defects to proceed to failure. This analysis should provide the engineer with sufficient knowledge to develop an initial screening program. When this screening program is then applied to the devices, the results of the screening (failure analysis data, fall-out statistics, etc.) should be carefully monitored to determine if the assumptions used to design the screening sequence were, indeed, valid for the device/technology, and if the desired results are being achieved in a cost-effective manner. If not, modifications or cessation of the screening sequence may be suggested by these results.

Thus, there must be a rationale for the specific screens chosen and for the order (sequence) in which they are applied. Table 18.6 provides an illustrative example of this for a screening sequence used to evaluate the effectiveness of various plastic package materials to protect the die from corrosion.

Selected Stress Screen Discussion

This section discusses the most commonly used stress screens: temperature cycle, constant acceleration, and burn-in.

Temperature Cycling and Thermal Shock

Temperature cycling and thermal shock are performed by alternately stressing devices at hot and cold temperature extremes. To perform temperature cycling, the units are typically placed in a chamber stabilized at the required high temperature for a specified period of time, then transferred to a cold ambient temperature at a prescribed rate of temperature change for a specified period of time, and finally transferred back to the hot ambient temperature at the prescribed rate of change. This completes one temperature cycle. This process continues until the specified number of temperature cycles have been completed. The temperature extremes, the transition time between temperature extremes, and the time at each temperature extreme will depend on the device type and package type being screened.

The terms thermal shock and temperature cycling are frequently used

Table 18.6 Screening Sequence Example

Task: Plastic package material and die overcoat material evaluation

Screen sequence:

Temperature cycle (-65°C to +150°C)

Provides expansion/compression stresses

Salt atmosphere

Provides corrosive environment

Power cycled (HAST)

Provides acceleration

Electrical tests

Verifies effectiveness of package and die coat in protecting the IC

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interchangeably, but there is an important difference. Temperature cycling is a less severe screen, which uses an air-to-air conditioning medium and may require several minutes of transfer time when transferring between temperature extremes. Thermal shock uses a liquid-to-liquid medium to provide the severe temperature shock environment and does not require a dwell time at room temperature when transferring between temperature extremes. If performed manually, opening the chamber door for a temperature cycle transfer can cause a slight chamber internal temperature change, but opening a chamber door for a thermal shock transfer causes practically no temperature change due to the volume of the liquid medium. Thus, thermal shock is a much more severe screen than temperature cycling and is performed as a package-related device type qualification test, but should not be used as a screening requirement because it can induce failures in ICs such as cracked die, cracked package seals, and broken wire bonds. Failure mechanisms accelerated by temperature cycling or thermal shock are

Improper die attach

Improper/faulty wire bonds

Thermal mismatch of materials, such as die-to-package interfaces

Lid seal anomalies on hermetically sealed packages

Inadequately or improperly cured plastic packages or material, such as epoxy die attach

Cracked dies or substrate mounting

The most commonly used temperature cycling screen is 10 cycles, with a 10-min dwell time at the specified temperature extremes and a 5-min maximum transfer time between temperatures. Up to 1000 temperature cycles are used to evaluate new technologies or new packages or for qualification tests. Most common temperature extremes are -65°C to + 150°C. Modern manufacturing technology, however, often uses either vapor-phase or infrared reflow of solder for board attachment of new-technology ICs. These reflow methods require temperatures of at least 210°C. Thus, the upper temperature limit for the temperature cycling screen is substantially lower than the temperature to which the circuit will be cycled (at least once, assuming no rework) in the system manufacturing environment. Temperature cycling must address this new higher temperature limit requirement to be current with actual usage.

Temperature cycling is normally followed by an electrical screen, centrifuge, and hermeticity screen (on hermetic devices) and visual inspection.

Constant Acceleration (Centrifuge)

Constant acceleration (centrifuge) screening is performed by placing units in a specially designed centrifuge (rotor) fixture and submitting them to a centrifuge speed that results in a predetermined force being applied. This acceleration is typically 30,000 g's for standard device packages and 5000 to 20,000 g's for

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large or oddly shaped packages. Failure mechanisms identified by constant acceleration are

Die lifting or cracking due to poor die attach

Wire-bond lifting for gold but perhaps not aluminum wire bonds

Package defects

Constant acceleration is not effective on solid noncavity-type devices. It is critical for large packages, such as 40- and 64-pin DIPs, QFPs, or microwave packages, that proper support fixtures should be built so as not to damage the devices due to handling or exposure to catastrophic g levels.

Constant acceleration was effectively used when gold wire bonding systems were widely used for hermetic devices. With the change to aluminum wire bonding systems, for most ICs, the value of the screen in precipitating wire bonding problems is questionable. The screen is still effective in locating die lifting and package defects.

Burn-In

The exceedingly fine dimensions and tight tolerances of high-performance integrated circuits result in sensitivity to the slightest of defects in their manufacture. Considerable effort has been expended in reducing the level of manufacturing defects through air, human, and process material filtration as well as incorporating fault-tolerant design and advanced material choices. Nevertheless, manufacturing defects continue to cause both yield and reliability failures.

Burn-in is an effective screening method used in predicting, achieving, and enhancing field reliability of ICs. It is the most effective screen in detecting die-related faults through time, bias, current, and temperature accelerating factors to activate the time-temperature-dependent failure mechanisms to the point of detection in a relatively short period of time. Increasing any of these four parameters tends to accelerate failures by increasing available energy to a threshold that activates various failure mechanisms.

Increasing voltage tends to accelerate failures related to junction breakdown, contamination, metal migration, tunneling, oxide rupture, and simple arc-over. Increasing temperature accelerates contamination and metal migration, activates normal impurity migrations toward high energy concentrations, and stresses weak circuit elements. A higher voltage also increases junction temperature and thus can activate both types of failure mechanisms. Increasing current/current density accelerates electromigration, aluminum migration, various intermetallic diffusions, open circuits due to microcracks and transistor junction anomalies.

During burn-in, the IC is operated under maximum electrical and elevated thermal conditions for a specified timefor 6, 8, 12, 24, 48, 96, or 160 hr, for example. The time-power-temperature relationship determines the acceleration

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factor (the equivalent operating life at 25°C) as well as the burn-in effectiveness (that percentage of the ultimate total number of failures that are detected during burn-in). It is generally accepted that 168 hr of accelerated burn-in at 125°C junction temperature is equivalent to 10,000 hr of normal operation at 50°C junction temperature.

To be effective, burn-in must cause destructive failure to occur, in-house at the IC supplier's facility, to the weakest of the devices, yet not cause undesirable degradation of outgoing devices. In effect, burn-in reduces the outgoing failure rate of production devices.

Burn-in is used to (1) eliminate infant mortalities, and (2) remove process defects, to improve quality and ensure the shipment of parts having a constant and acceptably low failure rate. Ever-increasing reliability requirements, as well as increasing IC densities, force manufacturers to continually improve the fabrication process. They use burn-in to help them monitor the production process and search out failure mechanisms.

There are several different types of burn-in in use, each of which presents a variation of the burn-in stresses created. These are

Steady-state reverse bias or forward bias burn-in

Static burn-in

Dynamic burn-in

Monitored burn-in or test during burn-in

High accelerated voltage tests

To determine which type of burn-in is needed for a given functional, technology, and package configuration, it is necessary to examine the types of possible defects and the extent to which these defects are activated by the various techniques. In addition, the burn-in condition developed for a particular device must be based on an understanding of that device's construction, operation, and topography. One must partition the device and determine how many junctions/gates are reverse biased and how many are actually forward biased to determine which type of burn-in is most effective.

Steady-State Burn-In

Steady-state burn-in can be either reverse biased or forward biased. Steady-state burn-in applies a DC bias to the device at an elevated temperature in a manner predetermined to either forward bias or reverse bias as many junctions as possible within the device. The direction in which the bias is applied will influence the power dissipation, and consequently the junction temperature of the device. Generally, in complex devices it becomes difficult to distinguish between the stresses resulting from steady-state or dynamic burn-in, since it becomes increasingly difficult to identify which and how many junctions are

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either forward biased or reverse biased without a detailed knowledge of the device's internal circuitry.

Steady-state reverse bias burn-in is used for digital and linear circuits, mainly with NPN inputs and outputs. This should not be confused with what some vendors call static burn-in. Steady-state forward-bias burn-in is used for linear ICs and some digital circuits, mainly with PNP inputs and outputs. Some people refer to this as static burn-in.

Steady-state burn-in is most effective in identifying devices with ionic contamination, inversion, channeling, oxide defects (such as pinhole shorts), metallization defects, thermally activated surface-related defects, and wire bond problems. Defects show up primarily as parametric drift, such as excessive leakage current, speed degradation, or threshold voltage shifts, and are detected during electrical measurements.

The majority of these defects result from some type of contamination or corrosion mechanism. Steady-state burn-in is useful in the precipitation of defects caused by corrosives and contaminants since the elevated temperatures make the contaminants more mobile, and the electrical field created by the bias causes preferential drift of the ions into critical areas. However, electrical testing must be performed within a short period of time, typically 24 hr, as a practical matter (although 48 hr is ideal), or the failure mechanism may self-heal. Prior to electrical testing, the devices must be cooled down with bias still applied.

Steady-state burn-in also detects wire bond problems, resulting from intermetallic formation, and oxide breakdown anomalies. The intermetallic compound formation is a time-temperature-dependent failure mechanism. The temperature present in the static configuration is effective in accelerating to the point of precipitation intermetallic defects that are in a fairly advanced state. The electric fields created by the bias in the steady-state burn-in stress defective oxides or oxides of insufficient dielectric strength and thereby cause breakdown at weak points.

Static Burn-In

In static burn-in, the outputs are biased and loaded for maximum power dissipation.

Dynamic Burn-In

Dynamic burn-in, where all clock and address lines are continually sequenced, results in higher dissipation, current densities, and chip temperature than static burn-in. It is the most effective means of burning in LSI and VLSI circuits. Dynamic burn-in identifies random defects such as oxide pinholes. Increased current densities stress defects such as epitaxial and crystal imperfections, metallization, oxide, and junction anomalies. Many of these defects

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require localized thermal stresses to provide activation for the associated failure mechanisms.

While dynamic burn-in is typically performed at high temperatures, its effectiveness in screening contamination defects is impaired by the lack of a constant electric field to provide preferential alignment of ionic contaminants. The dynamic operation causes the electrical bias. These changing electrical fields could actually cause ionic contaminants to drift to a noncritical area on the device, allowing for screening escapes.

In fact, steady-state burn-in is appropriate for locating defects in certain MOS devices because they have higher field and lower doping levels, thus allowing easy identification of these failures.

The two most common types of dynamic burn-in configurations are parallel excitation, where all devices are connected in parallel and driven by the same source, and ring counterexcitation, where the devices are connected in series with the output of one device driving the input of the next.

The screening and burn-in procedures employed for VLSICs are often found to be inadequate. This is because it is very difficult to apply consistent levels of electrical and thermal stress to each of the individual gates on the chip. Consequently, some devices pass through the screening only to suffer time- or stress-dependent failure in service. In order to make reliability predictions, the chips often incorporate several test circuits, such as MOS capacitors and transistors, so that, for example, the integrity of the oxide or the threshold voltage of the transistors may be examined. Thus, for VSLICs the process is being monitored rather than relying on product screening to eliminate infant mortalities.

Test During Burn-In

A subset of dynamic burn-in is test during burn-in (TDBI), which is being used primarily for dynamic and static random access memories (DRAMs and SRAMs) due to their long electrical test times. Normally, electrical testing is performed after burn-in to detect failures. Since it is a serial process, one tries to reduce test time to reduce cost. However, out of necessity, with VLSI devices, test time must be increased to effectively validate good parts due to their sheer complexity. Test during burn-in solves this problem and allows long test time at reasonable cost to thoroughly assess the inherent quality level of the memories tested.

Test during burn-in is similar to dynamic burn-in with the addition that the devices under test are cycled with a functional test pattern (such as the galloping pattern) and combined with an electrical test capability that allows the forcing functions (Vcc) of the device to be varied and the outputs to be monitored. This allows testing that would otherwise take too long during final test, thereby allowing a more complete test of the device. Test during burn-in allows the detection of soft errors and marginal/intermittent failures, via continuous

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monitoring, as well as catastrophic failures which would not have been caught by standard dynamic burn-in.

However, these are not mainstream concerns. The IC suppliers are concerned with these intermittent failure issues (which occur randomly) only during product/process development and prototype testing (pilot production), and these should thus not be viewed as being representative reasons for performing burn-in.

Additionally, TDBI was postulated to prevent the recovery or self-healing of certain failure mechanisms (such as ionic contamination) by not removing power after burn-in and performing the appropriate electrical test right in the burn-in system. However, the lower cost steady-state reverse bias burn-in is as effective if electrical testing is performed within about an 8-hr window after removal of power.

A typical test during burn-in screen is performed in the following manner. Devices are operated at an elevated temperature (125°C) and voltage (77.5 V) for an extended period of time, while subjecting all devices under test to functional testing using complex test patterns (n3/2 or n²).* This is followed by operation of short duration at a lower temperature (70°C) and voltage (5.5 V), during which parametric testing is performed. This cycle is repeated for 48 hr or longer. Since the time to burn in the devices has already been committed, the electrical testing when performed in this parallel manner is essentially free. However, the required equipment (i.e., functional tester in conjunction with a temperature programmable burn-in chamber with access to each device) is more expensive than normal dynamic burn-in equipment. Figure 18.1 shows a graphical representation of a variation of this test during burn-in sequence.

Accelerated (High) Voltage Oxide Stress Tests

High-voltage oxide stress tests are not true burn-in screens per se. However, they are so categorized because of their voltage, time, and temperature device-accelerated aging features.

It has been shown that the primary failure mode for CMOS ICs is oxide breakdown caused by process and manufacturing defects. Therefore, to control the reliability of the product, the process must be controlled to yield consistently high quality gate oxides. The use of thinner gate oxidesnecessary with shrinking geometriesis emerging as a major cause of semiconductor wearout, even under conventional burn-in screening conditions.

Figure 18.2 shows the temperature dependence of oxide breakdown failures

*For a discussion of memory patterns, see E. R. Hnatek, Electrical testing 4-kilobit memories present a challenge to testing, Computer Design, May: 117125 (1975), and R. Scholl, Effective screening techniques for high density memories, Institute of Environmental Sciences, Proceedings of the Third National Conference and Workshop on Environmental Stress Screening of Electrical Hardware, Philadelphia, September 1013, 1984 pp. 8892.

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Figure 18.1
Typical profile of test during burn-in.

for CMOS RAMs (for any CMOS device for that matter). When CMOS DRAMs were subjected to a 48-hr 160°C dynamic burn-in, it can be seen from Figure 18.2 that this burn-in did accelerate the failure rate to some extent. However, its effect in accelerating oxide breakdown failures was not as high as desired. This is because oxide breakdown failures have a thermal activation energy of 0.3 eV so that the temperature dependence is relatively small.

A typical high-voltage stress test involves cycling through all addresses using selected memory data patterns for 2 s both high and low (logically speaking) with 7.5 V Vcc being applied (for a 5-V rated part, for example). As a result, IC manufacturers use high-voltage stress tests to uncover oxide defects in CMOS ICs; often they use high-voltage stress tests in conjunction with either dynamic burn-in or TDBI.

Burn-In of VLSI Circuits

The burn-in of VLSI circuits and ASICs is a complex matter. (I've discussed these complexities in the previous chapters.) No longer is it appropriate to talk about such single and fundamental concepts as static or dynamic burn-in or high-voltage stress tests as currently used. Instead, burn-in must be approached from the perspective of providing both stress coverage and test coverage in conjunction with the activation energies associated with the various potential and unique failure mechanisms peculiar to a particular functional IC and their associated accelerating factors.

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Figure 18.2
Temperature dependence of oxide breakdown failures.

Stress coverage answers the question, do the acceleration factors of the burn-in stress (voltage, current, temperature) reach all internal portions of a given VLSIC or ASIC? Test coverage answers two questions: Can all faults be modeled? And are all internal circuit nodes controllable and observable? Test coverage is required to identify those failures precipitated by burn-in.

Both stress and test coverage are required. Burn-in (stress) by itself is not valid for VLSI circuits. It is at best 50% effective in precipitating defects to failure. Test coverage is needed to identify and remove those failures precipitated by burn-in. Table 18.7 shows the relationship between test coverage and stress coverage as relates to percentage of escapes. Figure 18.3 depicts the relationship between outgoing defect level in ppm graphically as a function of test coverage for different levels of test yield.

Table 18.8 summarizes the failure mechanisms accelerated by the various popular burn-in conditions based on activation energies for these failure mechanisms.

Burn-In Used as Process Improvement

Burn-in is often used by the IC supplier as a monitor to identify and correct process and design-related failure mechanisms as changes (improvements) are made. The burn-in time is then decreased and other defect mechanisms are detected and corrected in a process of continuous improvement. Table 18.9 is an example of this process. Failure analysis and corrective actions are a must for burn-in tailoring.

Page 768

Table 18.7 Test Coverage/Stress Coverage Relationships

Fail (%)

Test coverage (%)

Stress coverage (%)

Escape (%)

0.5

100

100

0.0

0.5

95

100

0.03

0.5

90

100

0.06

0.5

80

100

0.13

0.5

100

90

0.06

0.5

100

80

0.13

0.5

100

50

0.50

0.5

95

90

0.08

0.5

95

80

0.26

0.5

95

50

0.55

0.5

90

50

0.61

Electrical Testing

Electrical testing is the final step in the screening process. Noncatastrophic failures induced during the stress stage are detected during electrical testing. The electrical parameters used to identify failures have to be chosen in light of the anticipated failures. The temperature(s) at which parametric measurements are to be performed are also selected after consideration of the expected failures.

Figure 18.3
Relationship of defect level to test coverage effectiveness as a function of test yield.

Page 769

Table 18.8 Burn-In Screening Effectiveness as a Function of Failure Mechanisms Detected

Failure mechanism

Static B-I forward bias

Static B-I reverse bias

Dynamic B-I pulsed

High-voltage stress B-I

TDBI

TDBI + high voltage

Leakage current

X

X

X

Surface instability/ionic contamination

X

X

Step coverage

X

X

Oxide defects

X

X

X

X

Stress coverage

X

X

Epitaxial and crystal defects

X

Metallization defects

X

X

Junction anomalies

X

X

Inversion

X

Channeling

X

Wire bond problems

X

X

Tunneling

X

Metal migration

X

X

Refresh problems for DRAM (charge storage)

X

X
(at low temp)

Charge-related defects

X

Page 770

Table 18.9 Example of Burn-In Time Reduction Based on Experimental Results

Original setup

New setup

Process

TOX (Å)

hr

Temp. (°C)

V

hr

Temp.

V

1.5-mm NMOS EPROM

325

6

125

8.5

1

140°C

9.3

1.5-mm CMOS EPROM

325

168

125

5.25

1

140°C

7.6

1.5-mm CMOS EPROM

250

6

125

7.0

1

140°C

7.6

1.5-mm CMOS FLASH

110

48

125

7.0

1

140°C

7.6

Source: Sukyo and Sy, Development of a burn-in time reduction algorithm using the principle of acceleration factor. Intel International Reliability Physics Symposium, April 1991.

Burn-in failures are usually detected by performing parametric measurements at different intervals of time. The DC parametric tests must include worst-case input levels, input leakage current, output voltage, and current, along with source current. Functional testing must also be performed along with a full range of AC dynamic tests. These tests include as a minimum propagation delays, transition times, and minimum and maximum operating frequency.

It is important that all of these tests be performed at ambient, minimum, and maximum operating temperatures along with rated minimum and maximum supply voltages. Furthermore, each of these tests is necessary to assure that all defects are detected because some failures are detected by a multitude of tests, while other defects are only sensitive to certain temperatures, voltages, currents, or operating speeds. Indications of internal damage are either excessive or minimal supply current readings.

The degree of success of a given screen is equally dependent on both the stress phase and the electrical test phase. Well-designed stress screens are useless unless a comprehensive electrical test is performed after the devices have been screened.

Monitoring the Screening Program

The effectiveness of each screen must be monitored on a continuing basis to assure a meaningful program. Basically, a balance must be achieved between two limits. A program that yields few or no defects should certainly be reviewed for its effectiveness. On the other hand, a program that causes failures due to overstressing of parts does not accomplish screening objectives either. Thus, a screening program should be constantly reviewed to ensure that the desired results are being achieved in a cost effective manner. Furthermore, other channels of information, such as engineering analysis and field usage, should be periodically reviewed for impact upon existing screening procedures.

Page 771

APPENDIX: PERIODIC TABLE OF THE ELEMENTS

Page 772

Page 773

Page 775

Index

A

Accelerated Stress Tests (ESS), 285, 713, 717, 721, 724, 725-728, 732, 741-744, 747-755, 759-770

Activation energy, 547, 553, 620, 716-732

Aerosols, 365, 376, 378, 431

Alignment errors (mask registration), 438, 576, 584, 589, 651, 661

Alignment guides (mask), 36

Alloying, 604, 624, 625, 626, 628, 631, 712, 747

Alpha particles, 61, 66, 67, 160, 219, 251, 261, 741

Aluminium alloying, 73

Arrhenius equation, 546, 547, 551, 675, 716-732

ASICs (Application-specific integrated circuits), 13, 313, 316, 632, 656, 766

Assembly, 11, 25, 107-151, 153, 187, 195-197, 295, 296, 303, 304, 436, 479-488, 554, 556-559, 560-564, 574, 578-581, 583, 647, 649, 650, 655-702, 708-712, 714, 743, 747-753, 755, 757, 760, 761, 763, 769

ATE (Automatic test equipment), 100, 322, 323, 325-328, 335, 336, 601

accuracy, 501-503, 510

autohandlers, 676

calibration, 100, 101, 496, 512, 518, 519, 521

edge placement, 506-508

software, 100, 101, 346-348, 494, 496, 498, 512-517

software errors, 496, 498, 512-517

sources of error, 495-512, 517-522

test head capacitance, 503-506

At-speed testing, 508, 509

Autodoping, 60, 61, 62, 251, 252

Page 776

B

Bacteria, 393, 396-405, 456, 491

Ball bonding (wire), 138, 647, 669, 747

Ball grid array (BGA) package, 305-307

Barrier layer/material, 143, 268-284, 289, 619, 646, 647, 715

Bathtub failure curve, 704, 713-715, 733

Beam lead, 646, 647

Bipolar processes, 10, 14, 61-66, 78-82, 262, 263, 264, 265

Bird's beak, 257, 291

Bonded (glued) wafers, 221, 222, 223

Bonding pad contamination/corrosion, 647-650, 652, 668, 676, 701, 743, 747, 755

Bridging faults, 330, 331, 333, 334, 741

Built-in self test (BIST), 5, 315, 319

Bulk defects, 587-589, 705, 712, 714, 730, 754

Buried layer, 61, 62, 63, 65, 66, 251, 443, 584

Burn in, 589, 718-724, 729, 732, 746, 747, 748, 754, 761-768, 769, 770

C

Carbon contamination, 253, 373, 398

Causes of IC failure, 565-732

Cavity package, 108, 111, 112, 113, 115, 116, 118, 119, 120, 392, 483, 646, 668, 677, 695, 698, 699

Centrifuge testing, 578-581, 650, 743, 745, 747, 748, 752, 757, 760, 761

Ceramic package, 15, 109, 111, 115, 116, 118, 119, 680-682, 701, 739

cracking, 682

CERDIP, 15, 677-679, 698, 709

Channeling, 454, 455, 769

Channel stopper, 56, 611

Charge density (particle), 368

Charge spreading, 611, 769

Charge traps, 583, 594, 614, 615, 659, 725, 726, 730, 741, 744, 769

Chemical cleaning (wafer), 413-418

Chemical stress, 546-547

Chemical vapor deposition (CVD), 50, 57, 68, 69, 224, 244, 250, 252, 253, 254, 276, 277, 278, 282, 283, 287, 409, 430, 431, 444, 616, 617

Chip carriers, 15, 125-131, 132, 562, 680

Chip on board (COB), 111, 302-304

Chip on flex (COF), 303, 304

Circuit initialization, 328, 339

Circuit layout, 31, 33, 494

Circuit simulation, 30, 31, 225, 321, 325-328, 329, 337, 494, 495, 509

Clean rooms, 356, 363, 365, 366, 367, 368, 370, 377-390, 391, 406, 407, 414, 425, 429

Clean station, 386-388

Combinational logic circuit, 314, 339, 340

Computer-aided design (CAD), 30, 31, 32, 205, 343, 493-495

Computer-aided testing (CAT), 344, 345

Computer-based sources of error, 493-524

Concurrent engineering, 311, 318, 324

Contact misalignment, 256, 589, 637

Contact printing

Contacts (vias), 263, 268, 269, 271, 272, 273, 274, 275, 276, 279, 280, 284, 583, 590, 591, 637, 638, 647, 712, 714

Contact window defects, 269, 583, 584, 591, 593, 594, 595, 632, 637, 651, 742, 747

Contamination, 77, 245, 351-492, 576, 577, 589, 619, 633, 644, 647, 690, 712, 714, 747, 749, 756, 761, 763

airborne, 364, 365, 376, 378, 379, 381, 382, 430, 491

assembly, 371, 479-488, 581, 583, 659, 683, 684, 701, 712, 743, 750, 752, 753

chemical, 354, 364, 366-369, 371, 405-408, 414-417, 430, 456, 491, 584

control, 419-488, 489-492

equipment, 354, 362-365, 367, 369, 371, 414, 429-488

gas, 354, 371, 408-413, 430, 447, 456, 491

Page 777

[Contamination]

human, 354, 362, 363, 364, 366, 370, 371, 376, 414, 419-428, 456, 482, 483, 491, 656, 660

ionic, 76, 77, 109, 310, 364, 365, 367-369, 392, 393, 414, 415, 480, 481, 482, 485, 582, 584, 585, 601, 603-612, 634, 652, 659, 691, 693, 714, 730, 741, 764, 769

metal, 251, 254, 255, 362, 373, 378, 414-416, 430, 432, 447, 456, 491, 598, 652

organic, 369, 370, 371, 398, 399, 400-405, 436, 480, 483

particulate, 354, 356, 358, 362-371, 376, 377-487, 489-492

starting wafer, 371-376

wafer fab, 362-371, 376, 377-487

water, 371, 391-405, 416, 491

Control chart, 185, 186, 195, 196, 197, 200, 201, 202, 203

Copper-doped aluminum, 263, 264, 285, 286, 289, 290, 484, 552, 555, 603, 640

Copper leadframe, 297, 299

Corrosion, 77, 392, 436, 441, 476, 480, 481, 482, 483-487, 538, 539, 546, 550, 552, 578, 582, 583, 584, 603, 604, 605, 607, 619, 638, 646, 647, 657, 658-661, 680, 689-694, 701, 707, 709, 712, 714, 730, 741, 744, 745, 748, 749, 750, 755, 756, 759, 763

Cracks/cracking, 538, 541, 542, 543, 544, 546, 549, 557, 558, 560, 576, 580, 581, 583, 587, 588, 605, 618, 644, 651, 652, 659, 661, 663, 664, 676, 677, 678, 682, 684, 685, 686, 687, 688, 690, 693, 694-698, 701, 707, 712, 739, 742, 743, 744, 751, 755, 756, 759, 760

Cratering, 670, 675

Critical mask levels, 353, 354, 356

Crystal defects, 248, 374, 450, 540, 549, 551, 589, 598, 604, 609, 712, 763

Crystal lattice structure, 538, 539, 540, 549, 551

Crystal slip, 62, 67

Crystal topographic damage, 670

Current density, 266, 284, 285, 618, 620, 621, 629, 633, 640, 645, 744, 757, 763

D

Data sheet specifications, 321, 322

Defect density, 351, 352, 353, 354, 356, 357, 373, 391, 448, 449

Defect model (test), 311, 312, 330, 331, 332, 333, 335

Defect oriented tests, 156, 157, 311, 312, 334

Defects (physical), 4, 11, 156, 157, 311, 312, 330, 334, 335, 336, 351-523, 544, 554, 557, 565-732, 739-744, 746, 747-757, 760, 761, 763, 767, 769

clustering, 356, 358

manufacturing, 356, 570-572, 576-652, 705-712

Deformed/misformed wire bonds, 557, 668, 670, 671, 672, 686, 701, 712

Degradation, 527, 532, 537, 538, 540, 542, 553, 558

Deionized water, 394-405, 411, 482

Delamination, package, 686, 687, 701

Delamination/separation, metal layer, 651, 712, 741, 759

Delay fault, 333, 334

Dendrite, 560, 582, 583, 661, 662, 690, 744, 756

Deposition, thin film layers, 53-76

Design, 25, 30-35, 207-225, 313, 316, 323-325, 493-495

cost, 21

cycle, 21

numbers of, 20, 21

Design errors/defects, 334, 495, 566-569, 754, 767

Design-for-test (DFT), 5, 20, 315, 319, 329, 341-343, 500

Design of experiments (DOE), 735

Page 778

Design rules/feature size, 13, 206, 208, 212, 215, 378, 379, 493, 494, 495, 637, 729

Design tools, 30, 31, 32, 205, 225, 321, 325-328, 329, 343, 493-495, 509

Design verification testing, 320

Die attach (bonding), 135-137, 187, 195, 196, 295, 296, 511, 578, 579, 583, 656, 662-668, 676, 701, 708, 712, 714, 743, 749, 751, 752, 760, 761

Die coat, 150, 685, 688, 692, 694

Die cracking, 663, 666-668, 682, 684, 687, 701, 739, 741, 743, 751, 752, 760

Dielectric breakdown, 448, 593-603

Dielectric defects, 545, 593-603, 751

Dielectric formation, 25, 29, 30, 39, 43, 44

Dielectric layers, 29, 30, 39, 43, 44, 48, 49, 51, 55, 56, 57-60, 68, 76-78, 143, 144, 255, 280-282, 286, 448, 449, 453, 454, 547-549, 593-603, 608, 617, 635-640, 645, 646, 647, 658, 659, 725-728, 741, 751

Die-related defects, 565-652, 705-707, 712, 741, 742, 747

Die shrink (scaling), 66, 209, 258-267, 628, 634, 640, 642-645, 765

Diffusion, 49-51, 243, 244-246, 252, 430, 431, 442-444, 744, 759

Diffusion barrier, 268-284, 289, 290

Diffusion furnaces, 246-247

Disbonding, die (see Lifted die)

Dislocations, 78, 248, 253, 254, 256, 373, 538-540, 550, 551, 553, 554, 576, 712

Dissolution, 552, 625, 712

Dopants, 28, 29, 49, 50, 51, 61, 252, 253, 454

Doping, 28, 29, 49, 50, 51-55, 243-247

DRAM cell, 208, 209, 210, 216-220

Dry etching/processing, 240-242 (see also plasma etching)

Dual-in-line package (DIP), 15, 113, 118-122, 123, 127, 466, 677-682, 698, 709

Dynamic burn in, 754, 763, 764, 765, 769

Dynamic random acess memories (DRAMs), 2, 8, 10, 11, 12, 17, 207-220, 238, 251, 282, 295-298, 314, 315, 358, 359, 548, 725-728, 736, 764, 766

E

EEPROM, 738

Electrical characterization tests, 169-171, 321

Electrical noise (clean room), 377, 385

Electrical overstress (EOS), 599, 600-603, 652, 656, 747

Electrical test (test), 15, 18, 19, 20, 25, 99-106, 151-172, 309-349, 496-512, 517-522, 576-581, 601, 746, 747, 748, 756, 759, 768, 770

Electrical test errors, 22, 101, 496-512, 517-522

Electric field stress, 723, 724, 725-728

Electrochemical (galvanic) corrosion, 552, 582, 583, 607, 638, 659, 660, 661, 662, 695, 698, 711, 712, 730, 755, 757

Electromigration, 72, 180, 183, 185, 190, 261, 263, 267, 271, 279, 280, 284-286, 289, 290, 335, 439, 468, 493, 552, 553-555, 582, 583, 584, 603, 617-622, 623, 625, 628, 629, 633, 637, 640, 644, 645, 651, 652, 707, 712, 714, 730, 741, 744, 748, 757, 759

Electron beam lithography, 228, 231-234, 615

Electron beam probing, 101-105

Electron mobility, 210, 211, 250, 251

Electro-optic sampling, 106

Electrostatic (triboelectric) charge, 356, 368, 369, 371, 375, 391, 431, 450, 455, 456, 466-476, 477

Electrostatic discharge (ESD), 4, 39, 441, 466-476, 477, 494, 584, 599, 600-603, 644, 652, 656, 700

Engineering work station, 30, 31, 32, 205, 326, 328, 343-346, 493-495

Page 779

Environmental stress, 657, 658

Environmental stress screens (ESS), 576-581, 733-770

Epitaxy, 25, 60, 61-67, 251-254, 266, 431, 449

Epoxy package materials, 529, 532, 676, 684, 689, 690, 692, 693, 694

EPROM data retention, 718-723

Error Correction Circuitry (ECC), 315, 340

Error sources, 3, 4, 22, 565-585

Etch (photoresist), 48, 49, 240-242, 409, 430, 432, 436, 438, 441, 442, 481, 486, 583, 594, 595, 596, 604, 605, 635

Etch pits, 251, 410

Evaporation, metal, 57, 68-73, 286, 431, 615, 616

F

Failure mechanisms, 56, 72, 73, 76-78, 180-185, 190, 197, 202, 203, 227-292, 310, 334-410, 433, 438, 439, 444, 448-452, 454, 459, 468, 479, 537, 544, 546, 548-550, 553-555, 560, 565-732, 739, 741-744, 747, 748, 749, 751, 752, 756, 757, 759, 761, 763, 765-767, 769

Failure mode, 567-572, 576-581, 659, 713, 741-743, 747, 748

Failure rate, 716, 731, 732

Fatigue (cracks), 541, 542, 543, 557, 644, 652, 688, 739, 744, 756, 759

Fault coverage, 5, 19, 313, 330, 331, 336, 337, 338, 341

Fault models, 311, 312, 330, 331, 332, 333, 335

Fault simulation, 313, 315, 328, 329, 337, 338, 344

Feature size, 13, 66, 206, 209, 212, 215, 258-267, 352, 642, 644

Fick's laws, 551, 552

Flash memory, 641, 770

Flat package, 15, 111, 112, 113, 115, 116, 117, 118, 119, 305, 306, 657, 694, 696, 697, 701

Flip chip bonding, 140-142, 150, 151, 153, 302, 304-307, 562, 647

Fowler-Nordheim tunneling, 596

Friction, 465, 470, 472, 557, 558

Functional tests, 99, 100, 152, 154, 158-162, 171, 311, 323, 337, 338, 736, 737, 738

G

Gallium arsenide (GaAs), 211, 250, 251, 254, 297, 300, 372, 375, 376, 413, 416, 417, 445-448, 477, 483, 662

Gas distribution system, 412-413

Gate arrays, 17, 263, 643, 656, 657, 737

Gate oxide, 243, 310, 334, 335, 410, 467, 468, 548, 582, 585, 592, 593, 597, 599, 601, 741

Gate oxide shorts, 310, 334, 335, 410, 468, 582, 585, 597, 599, 601, 741

Gettering, 254-256, 604, 605, 659, 715

Grain structures, 537, 549, 550, 551

Guardband testing, 503, 504, 509-512

Guard ring, 66

Gull wing leads, 133, 134, 562, 564

H

Handling (mishandling) damage, 4, 11, 584, 656, 657, 676, 699, 700, 701, 746

Hard glass package, 108, 109, 115, 679, 680, 698

Hermeticity failures, 482, 714, 747, 748

Hermeticity (leak) tests, 581, 746, 747, 748, 753, 754

Hermetic package (see Cavity package)

Hermetic (cavity) package defects, 677, 683, 684, 714, 748, 760

Highly accelerated stress test (HAST), 730, 755, 759

High-temperature reverse bias (HTRB) tests, 576, 577, 581, 746, 610, 754

High-temperature storage tests, 576, 577, 578, 579, 745, 719, 747, 748, 750

Hillocks, 73, 263, 264, 271, 279, 280, 290, 444, 451, 554, 560, 582, 583, 617-622, 634, 712, 748, 757

Histograms, 198, 199, 597

Page 780

Hot carriers, 78, 197, 202, 265, 310, 493, 548, 582, 589, 591, 595, 612-615, 628, 629, 644, 651, 652, 712, 714, 730, 741

Human causes of error, 601, 699, 700, 748 (see also Contamination, human)

I

IC manufacturing sequence, 25, 39-42, 78-98

IDDQ (quiescent current) tests, 156, 157, 310, 331, 333, 334, 508, 519, 597, 600

Impact ionization, 613, 614

Infant mortality, 704, 713, 714, 715, 719, 721, 723, 733, 735, 740, 762

Input protection circuits, 601-603

Integrating design and test, 313, 316, 323-325, 337, 339

Interfaces, material, 532, 539, 542, 550, 551, 566

Intermetallic compounds, 139, 480, 540, 541, 542, 558, 560, 561, 579, 583, 646-650, 660, 670, 675, 701, 714, 718, 730, 743, 750, 751, 763

Ion beam lithography, 238

Ionic contamination (see Contamination, ionic)

Ion migration, 604-612

Isolation, 257, 258, 259, 260, 291

J

J leads, 134, 562

Junction shorts/spikes, 268, 285, 290, 410, 584, 589, 590, 742, 761

K

Killer defects, 356, 461

Kirkendall voids, 480, 648, 675, 701, 718, 730

L

Laminar flow, 382, 384, 387, 388-390, 404, 474

Laser probing, 105, 106

Latch-up, 61, 66, 67, 222, 493, 584, 591, 592, 600, 614, 652, 755

Latent defects, 597

Layout, 31, 33, 493-495

Lead-on-chip (LOC) package, 295-298

Leakage current, 334, 335, 359, 369, 467, 582, 589, 597, 600, 604, 605, 607, 611, 741, 742, 763, 769

Life cycle (product), 21

Life tests, accelerated/operating, 285, 576-581, 713, 717, 721, 726, 730, 748

Lifted die (disbonding), 656, 663-666, 761

Lifted metal (delamination/layer separation), 628, 651, 712, 741, 747, 759

Lifted wire bond pads, 632, 708, 748, 756, 761

Lifted wire bonds, 544, 574, 579, 583, 648, 656

Lift-off (metallization), 270, 271, 289, 439

Linear (analog) ICs, 31, 32, 36, 37, 38, 162-169, 599, 602, 603, 606, 611, 759

Line edge roughness, 233

Lithography (see Photolithography)

Logic simulation (see Circuit simulation)

Loose particles (assembly), 581, 583, 659, 683, 684, 701, 712, 743, 750, 752, 753

Low operating voltage, 8, 10, 178, 208, 209, 264, 265, 642, 643, 644

Low-pressure CVD (LPCVD), 224, 244

Low-temperature tests, 736, 737

M

Manufacturing errors/defects, 351-523, 739-740, 744, 767 (see also Error sources)

Mask alignment/registration, 36, 45, 46, 47, 225, 232, 237, 238, 438, 440, 576, 584, 589, 645, 651, 661

Mask (photomask) defects, 432-441, 449, 589, 590, 712, 730, 748

Mask making, 35-38

Masks (photomasks/patterns), 33, 34-38, 44, 45-49, 63, 64, 232, 235, 236, 237, 432-441, 494, 495, 508

Page 781

Material properties/characteristics, 526-538

Materials, 27-29, 108-110, 136, 137, 248-258, 270, 273, 275-279, 281, 525-564, 566, 579, 663, 688, 740, 744, 756

Measurement

accuracy, 168, 320

repeatability/reproducibility, 168, 517-522

uncertainty, 509-512, 521

Measurement (test) errors, 22, 101, 499, 500, 503-508, 512, 514, 517-522, 721

Mechanical cleaning, 417

Mechanical defects (deformation), 248, 374, 439, 450, 451, 479, 540, 541, 549, 551, 553, 582, 583, 589, 598, 604, 609, 622-628, 632-634, 637, 651, 663, 666-668, 682, 684, 686, 687, 701, 712, 714, 739, 741, 743, 747, 751, 752, 759, 760, 763

Mechanical strength/durability, 555

Mechanical stress, 542-544, 545, 546, 557, 558, 616, 617, 618, 638, 639, 651, 666, 667, 677, 680, 681, 682, 684, 685, 686, 742, 744, 756, 757, 759

Memory test, 158-162

Memory test patterns, 158, 764, 765

Metal impurities, 251, 254, 255

Metal layer quality, 616

Metal layer separation (lifting, delamination), 628, 651, 687, 688, 701, 712, 741, 747, 759

Metallization/interconnection, 68, 70-76, 256, 257, 258-292, 450-454, 549-555, 582, 583, 603, 604, 605, 607, 616-652, 658-662, 684, 693, 712, 714, 730, 741, 742, 747, 748, 749, 750, 751, 754, 755, 763, 769

Metal migration, 265, 550, 553, 554, 618, 707, 712, 730, 741, 747, 748, 761, 769

Metal notching, 256, 544, 546, 583, 589, 633, 637, 638, 639, 641, 651, 712

Metal opens, 585, 589, 618, 622-628, 634, 637, 638, 639, 640, 646, 648, 741, 747

Metal shift, 632, 684, 712

Metal shorts, 449, 584, 589, 632, 634-637, 646, 741, 748

Metal tearing, 439

Metal thinning, 256, 624, 629, 630, 631, 637, 638, 651, 712, 747

Microcracks, 451, 479, 582, 583, 622-628, 633, 634, 637, 707, 714, 741, 747

Microenvironment, 391, 392

Migration gold resistive short (MGRS) 583, 647

Minienvironment, 391, 392

Misalignment, mask, 438, 576, 584, 589, 651, 661

Moisture, 76, 109, 120, 296, 392, 480, 481, 482, 483-487, 494, 529, 538, 546, 549, 552, 582, 583, 604, 605, 651, 656, 659, 660, 661, 662, 676, 677, 679, 683, 689-699, 701, 741, 743, 748

Molecular beam epitaxy (MBE), 253

Multichip modules (MCMs), 13, 18, 100, 111, 150, 151, 293, 298, 299, 301, 302, 669

Multidisciplined (cross-functional) team, 311, 318

Multilevel interconnect (metal) structures, 8, 10, 73, 74, 75, 261, 262, 263, 267, 271, 274, 275, 283, 284, 289, 448, 449, 453, 454, 621, 629, 633-645, 747

Multilevel resist, 256

Multiple stuck at faults, 333

N

Nondeterministic (random) test vectors, 328

Nonhermetic packages (see Plastic package)

Page 782

O

Observability, 317, 338, 342

Open circuit defects, 332, 334, 335, 367, 554, 575, 582, 583, 585, 589, 601, 618, 622-628, 633, 637, 638, 639, 640, 646, 648, 659, 689, 701, 741, 742, 743, 747, 748

Open wire bonds, 656

Operational amplifier testing, 162-169

Operator error, 601, 699, 700, 748

Optical lithography (see Photolithography)

Overlay accuracy, 232, 234, 237, 238, 239

Overmolded pad array carrier (OMPAC) package, 305-307

Oxidation, 25, 29, 30, 39, 43, 44, 48, 49, 243, 244, 258, 259, 260, 267, 430, 431, 444-448, 610

Oxide

breakdown, 592, 626, 642, 712, 725-728, 765, 766, 767

defects, 265, 310, 334, 335-410, 448-449, 468, 479, 582, 584, 585, 592, 593, 595, 597, 601, 607, 615, 619, 620, 642, 644, 651, 652, 712, 714, 725-728, 730, 741, 763, 765, 766, 767, 769

layer, 39, 43, 44, 48, 49, 243, 280-282, 568, 604-615, 622-628, 642, 643, 741

quality, 310, 615

shorts, 310, 334, 335, 410, 468, 582, 585, 597, 601, 619, 712, 741

thinning, 592

undercut, 592, 593

wearout, 265, 310, 582, 584, 595, 597, 615, 644, 652, 714, 741, 765

Oxynitrides, 548

P

Package-related defects, 574, 583, 655-702, 708-712, 743, 748, 749, 760, 761

Package (hermetic) sealing, 571, 581, 656, 677-683, 701, 709, 710, 743, 748, 749, 751, 753, 754, 755, 760

Packaging, 11, 12, 13, 15, 16, 17, 18, 107-151, 293-307, 466, 555-564, 574, 668, 676-699, 743

materials, 108-110

Parametric tests, 99, 100, 154, 155, 160-169, 171, 311, 768, 770

Parasitic capacitance, 249-251, 261

Parasitic transistor, 582, 591, 595, 611

Passivation/glassivation (die), 55, 56, 76-78, 143, 144, 286, 289, 553, 555, 587, 603, 604, 608, 611, 617, 618, 623, 637, 638, 646, 647, 651, 658-661, 684, 685, 687, 688, 690, 693, 694, 701, 712, 741, 747, 751, 755

Pattern shift (mask distortion), 63, 64, 65, 251, 252, 450

PC board assembly, 11, 560-564, 657

Photolithography, 25, 44-49, 213, 227-242, 431, 638, 712

defects, 290, 367, 368, 432-441, 449, 576, 582-584, 589, 590, 604, 605, 638, 647, 651, 659, 661, 690, 712, 730, 741, 748, 763

Photomask defects, 432-442, 449, 589, 590, 712, 730, 748

Photoresist, 46-48, 230, 231, 239-242, 256, 258, 430, 436, 438, 481

defects, 432-441, 712, 747

Pin electronics (ATE) skew/drift, 328

Pin grid array (PGA), 15, 125, 126, 657, 680

Pinholes, 290, 367, 368, 433, 438, 576, 582, 583, 647, 651, 659, 690, 741, 748, 763

Pitting, 251, 255, 410, 587, 590, 593, 603, 625

Planarization, 56, 60, 256, 257, 258, 271, 291, 439, 453, 454, 645

Plasma-enhanced CVD (PECVD), 253, 254

Plasma etching, 241, 409, 432, 436, 438, 441, 442, 486, 594, 595, 596

Plastic deformation, 542, 553

Plastic package, 109, 112, 117, 118, 120, 121, 127, 150, 151, 295-300, 392, 483, 668, 677, 760

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[Plastic package]

cracking, 684, 685, 686, 694-698, 701, 743, 755, 760

defects, 683-698

p-n junctions, 25, 51, 582

Polycide, 277-279

Polyimide (organic insulators), 281, 282, 290, 529, 537, 692

Polymers, 529, 533, 660, 674, 688, 757

Poor wire bonding machine control, 669, 670, 673-675

Popcorning, 689, 694-698, 701

Precipitates, 540, 552, 712, 747

Procedures, cleanroom, 388-390

Process control, 443, 454, 458, 618, 624, 647, 649, 676, 700, 705-711, 714, 729

Process monitors, 172, 177-203, 318, 465, 596, 597, 676

Production lead time, 207, 208

Projection alignment (mask), 46, 47, 440

Protective garments, 422-428

Proximity printing (mask), 46

Purified water, 392-405

Purple plague, 139, 579, 647-650, 675

Purpose of testing, 310-312

Q

Quad flat package, 15, 112, 117-119, 305, 306, 657, 694, 696, 697, 701

Quality, 330, 334, 335, 338, 494, 615, 616, 767, 768

historical perspective, 1-4

Quiescent leakage current tests (see IDDQ tests)

R

Race conditions, 341, 342

Radiation damage, 584, 605, 615, 744

Rapid thermal processing (RTP), 444-448

Reactive ion etching (RIE), 218, 219, 242, 257, 259, 260, 271, 289, 291, 430, 615

Redundancy, 314, 315, 336, 340

Refractory metals, 76, 268-280, 288, 619, 624, 628, 646

Relative humidity tests (85 C/85% RH), 661, 692, 744, 755

Reliability, 20, 289, 290, 293, 314, 334, 454, 565-583, 589, 609, 625, 626, 629, 634, 638, 644, 647, 650, 651, 689, 693, 703-732

defects, 177, 185

Resist (see Photoresist)

Reticle, 36, 236, 440

S

Salicide, 27

Sawing, wafer, 106, 587, 667, 676, 682, 712

Scan design, 342, 343, 346

Scratches, metal, 76, 77, 335, 577, 618, 631, 632, 647, 742, 747, 749

Screening

effectiveness, 736, 740, 749-755, 770

sequence, 758, 759

Scribe and break, 106, 107, 587, 682

Sequential logic circuit, 314, 339, 340

Short channel effects, 222, 290, 291

Shorted wire bonds, 656, 701

Shorts, 268, 269, 335, 367, 368, 444, 449, 552, 576, 582, 583, 584, 589, 599, 600, 601, 617, 626, 630, 634-637, 646, 659, 670, 687, 701, 741, 742, 743, 748

Signal integrity (ATE), 500, 501

Silicides, 68, 73, 249, 261, 267-269, 273, 275-280, 283, 286-288, 290, 291, 548, 628, 633, 647

Silicon dioxide (also see Dielectric layers), 29, 30, 39, 43, 44, 48, 49, 51, 68, 76-77, 280-282, 448, 449, 453, 454, 593-603, 659, 725-728, 741

Silicon doped aluminum, 285, 286, 289, 290, 649, 650, 651, 678

Silicon-germanium, 220

Silicon nitride, 55, 56, 77, 78, 143, 144, 255, 281, 282, 286, 594, 608, 617, 646, 647, 658 (see also Passivation)

Silicon nodules, 286, 582, 618, 620, 625, 631, 632, 651, 712

Page 784

Silicon-on-insulator (SOI), 212, 213, 214, 217, 218, 220-225, 249, 250

Simulation (see Circuit simulation)

Single stuck at fault (SSAF) model, 330, 331, 333, 334

Slip, 251, 445, 446, 450

Small outline IC (SOIC) package, 11, 15, 122-124, 132, 133, 295, 297, 562, 694, 698

Smear, metal, 618, 632, 742, 749

SMIF (standard mechanical interface), 391, 392

Software (ATE)

backup, 513, 514

quality assurance, 515-517

version control, 514

Software simulation, 347, 348

Solder attachment, 560-564, 657, 686, 694, 695, 701

Solder joint/interconnection, 134, 135, 560-564

Sources of contamination, 351-492

Sources of electrostatic charge, 470-472

Sources of poor quality (errors), 3, 4, 22, 565-585 (see also Design errors; Electrical test errors; ATE, sources of error; Manufacturing errors; and Wire bonding errors)

SPC (statistical process control) techniques, 178, 181, 182, 195-203, 596, 597

Spiking shorts, 268, 269, 444, 552, 617

Sputtering, metallization, 57, 74, 76, 286, 287, 409, 430, 431, 451, 453

Stacking fault, 62, 63, 248, 254, 255, 372, 410, 450, 576, 598

Static burn in, 763, 769

Static (ESD) control, 473-477

Static RAM (SRAM), 6, 7, 17, 641, 736, 764

Static susceptibility, 467, 468

Steady-state burn in, 762, 763

Step coverage (metal/oxide), 56, 256, 257, 267, 279, 335, 439, 450-452, 454, 549, 584, 589, 622-628, 636, 637, 640, 651, 690, 707, 747, 751, 769

Stitch wire bonding, 138, 139

Stress, manufacturing induced, 256, 280, 281, 282, 446, 527, 537, 541-547, 557, 558, 588, 616, 618, 638, 639, 651, 666, 667, 679, 681, 682, 684, 685, 686, 763 (See also Mechanical stress)

Stress concentrators, 529, 541-547, 558, 677, 739, 756

Stress coverage, 766-769

Stress screen (ESS) selection, 746

Stress voids, 78, 335, 582, 584, 617, 651, 730

Stringers, 582, 583, 635, 636, 645

Structured testing (electrical), 311, 314

Stuck open fault model, 332

Surface defects, 585, 587-589, 603-612, 714, 730, 741, 744

Surface instability (charge spreading), 604, 605, 712, 714, 730, 744, 769

Surface-mount technology (SMT), 11, 15, 110-113, 125-135, 302, 560, 562, 563, 657, 694-698, 701

Surface transport/charge, 455, 661, 714, 741, 744

Systems on silicon, 315, 317, 318, 319

T

Tape automated bonding (TAB), 143-149, 150, 151, 153, 302, 583

Tapered edge (sloped oxide), 623, 633, 636

Technology trends/innovations, 5-22, 205-225

Temperature cycle test, 576-581, 623, 644, 648, 652, 686, 687, 693, 738, 745, 747, 748, 751, 756, 758-760

Temperature-dependent failure mechanisms, 716-732, 761-767

Temperature humidity bias test, 661, 692, 744, 755

Test (see also Electrical test)

accuracy, 320

coverage, 330, 335, 766, 767, 768

development costs, 18

development time, 310

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[Test]

fixtures/performance boards, 163-167, 500, 518, 601

sequence, 168, 169

specifications, 321-323

structures, process, 37, 172, 177-203, 620, 764

time, 311, 314

Testability, 5, 19, 313, 317, 319, 324, 337, 338-341, 344

Test during burn-in (TDBI), 764-766, 769

Tester (ATE)

capability, 322, 325-328, 336

limitations, 325-328, 336, 337

repeatability, 517-522

reproducibility, 522

Testing relationships

third-party design houses, 320

user-foundry, 319-321

Test pattern

generation, 312, 329-337

sensitivity, 314

Test program generation, 309, 312, 313, 320, 323, 329-337, 345, 346, 494

automatic (ATPG), 309, 345, 346

manual, 309, 312, 313

Thermal oxidation, 25, 29, 30, 39, 43, 44, 48, 49, 243, 244, 258, 259, 260, 267, 430, 431, 444-448, 610

Thermal shock tests, 578, 678, 686, 751, 757, 759, 760

Thermal stress/acceleration tests, 544-546, 677, 680, 723, 724, 741-744, 747, 748, 751, 754, 755

Thermocompression wire bonding, 137, 138, 153, 480, 482, 557, 647, 649, 650, 668, 669

Thermosonic wire bonding, 140, 153, 480, 557, 669

Thin film (metal) cracking, 439, 628, 651, 687, 688, 701, 712, 741, 747, 759

Thin film layers, 53, 55, 56, 57

Thin small-outline package (TSOP), 123, 124, 295, 298

Three-dimensional structures, 209, 217, 218, 222-225

Threshold voltage shift, 369, 442, 493, 582, 585, 604, 606, 612, 615, 658, 725-728, 741, 742, 763

Through-hole packages, 15, 110-113, 118-122, 123, 125, 126, 127, 135, 136, 466, 657, 677-682, 698, 709

Time-dependent dielectric breakdown (TDDB), 192, 193, 203, 585, 595, 598, 599, 609, 634, 712, 723, 725, 730

Time-to-market, 21

Toggle testing, 337

TO style packages, 111, 112, 113, 135, 136, 466

Tunneling, 598, 622, 637, 761, 769

Type I errors, 22, 101, 503, 507, 512, 514, 517, 518, 519

Type II errors (test escapes), 22, 101, 503, 512, 514, 517, 721

U

Ultrasonic cleaning, 417, 418

Ultrasonic wire bonding, 139, 140, 153, 480, 557, 649, 650, 668, 669

Unspecified electrical parameters, 322

Useful life, 704, 713-715

V

Vertical diffusion furnaces, 245, 246

Vertical structures, 209, 210, 213, 214, 216-225

Via (contact) defects, 583, 584, 591, 593, 594, 595, 632, 637, 651, 742, 747

Vias, 632, 633, 637, 638-640, 651, 742 (see also Contacts)

Vibration, clean room, 377, 385, 386

Visual inspection, 576-581, 745, 747-749, 755

VLSI defects and failure machanisms, 650-652

Void (contact), 269

Voids, 269, 436, 539, 544, 554, 560, 578, 582, 583, 593, 607, 617-620, 625, 632, 637, 645-648, 651, 659, 661, 663, 664, 666, 675, 681, 712, 741, 757